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570c1a65 |
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05-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Compile time abstraction for calling getCurrentCPUIndex This defines a CURRENT_CPU_INDEX() macro that resolves to a constant 0 in the absence of SMP, or a call to getCurrentCPUIndex in the presence of SMP. This provides a way to use per-core data structures, without additional guards, in a way that is nearly invisible to verification
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8576758a |
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06-Nov-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Define SchedulerAction_ChooseNewThread as 1 1 is never a valid tcb, and ~0 on x64 results in 0x00000000FFFFFFFF, which could be a valid tcb.
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c6e4cc3e |
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23-Nov-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Correct L2 bitmap size calculation and put it in one place This corrects the calculation of the L2 bitmap size to correctly handle cases where the requested num priorities is not a clean multiple of the wordBits
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ee28936d |
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18-Jun-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Introduce ENABLE_SMP_SUPPORT - Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check
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40c61e5c |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Fix licenses (the rest)
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bb5ecb1b |
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29-May-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-880: add seL4_DebugDumpScheduler - when CONFIG_DEBUG is enabled, track all threads - when CONFIG_PRINTING is enabled, provide seL4_DebugDumpScheduler which allows the user to dump the state of the kernel scheduler.
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0707ae87 |
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23-Feb-2017 |
amrzar <azarrabi@nicta.com.au> |
Move arch independent functions to generic files and HAVE_FPU config
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ae8f2c99 |
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23-Feb-2017 |
amrzar <azarrabi@nicta.com.au> |
x86: move current active FPU owner to node state
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323e60a7 |
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23-Feb-2017 |
amrzar <azarrabi@nicta.com.au> |
x86: define number of restore since switch as node state
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eccaae51 |
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20-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
s/D61/DATA61/ in license headers for consistency
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48d17e1f |
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16-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
ARM/SMP: Prepare for ARM SMP adding stubs Currently building ARM/SMP is broken. This commit: 1- Makes it possible to build ARM/SMP with stubs. Run-time SMP for ARM DOES NOT WORK. 2- Can be a reference for future SMP targets to follow in order to layout/add the minimal required files and functions needed to support SMP. 3- Builds for Sabre only. In order to support other platforms, ipi interrupt ID should be defined in machine.h
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53c6b524 |
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12-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Abstract architecture/platform independent parts of smp.h and ipi.h This commit is a re-arrangement of SMP directory structure to make it easier for other architectures/platforms (in general) and ARM (in particular) to add SMP support. * new include/smp directory to act as a centralised container of "shared" architecture-independent SMP headers. This makes it clearer what's needed for other architecture/platform to support SMP. * Each platform can define its own unique ipi.[h|c] that make sense, since ipi implementation is SoC/platform dependent.
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cc685301 |
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23-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Remove unneeded usages of `VISIBLE` Using `VISIBLE` where it is not needed limits the ability for the compiler to optimize, especially when using whole program optimizations
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7f767494 |
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15-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Revert SELFOUR-242 This reverts commits 3aee0ab7b3ae5ff5294192526fb00823b49048b5 6b6b965528d16c1e4c946fb920fb95060f84424f a1421832acd19ed5ede71640af82b982708207c2
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a1421832 |
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15-Feb-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-242: invert bitfield scheduler & optimise This commit does the following: * invert the bit field scheduler for better cache performance for high priority threads * peeks into the bitfield scheduler to allow fastpath to be leveraged when IPC occurs from lo --> hi priority threads if correct
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63649f26 |
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19-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Remove arch/machine.h include from statedata.h statedata.h gets included from arch/machine.h, and statedata does not require any of the machine.h definitions. As a result of removing this various other, previously missing, includes need to be added
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b90238d0 |
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19-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Replace #pragma once with include guards
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3f9eb7c8 |
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06-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-632: implement cores non-architecture dependent structres
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2cbc7123 |
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28-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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4044e204 |
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21-Sep-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Revert "Merge pull request #358 in SEL4/sel4 from ~AZARRABI/sel4:multicore to master" This reverts commit ce2f666bb811c5e4c779829fcb09d5a189ebcdbb, reversing changes made to dc183f96b81f2344d7d0d910fc430f924eaae940.
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8ffc3531 |
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21-Sep-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Revert "[STYLE_FIX]" This reverts commit d29f743bbcc3acff2f61b40dedb4fe0839db38b8.
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d29f743b |
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21-Sep-2016 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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fbc071b4 |
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12-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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16c34811 |
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31-Jul-2016 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SELFOUR-518: User-level log buffer Remove global ksLog and use KS_LOG_PPTR instead Benchmark - Log buffer: use global page table
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c5b6a6a5 |
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06-Jun-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
Refactor duplicated code in hardware.h One copy to rule them all.
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bbdf7a89 |
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23-May-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Mark tlbLockCount as visible so it is not discarded This variable is referenced in assembler and needs to not get discarded by the optimizer prior to linking.
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b9a7f3c9 |
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05-May-2016 |
Felix Kam <felix.kam@nicta.com.au> |
Make lockTLBEntry comply with the decompiler lockTLBEntry, an assembly function, had tlb_lock_count as a symbol that needed to be placed sufficiently close to be loaded and stored with offset-from-pc addressing. When assembled, the symbol would turn up between functions, as opposed to within a literal pool (it's a variable, not a constant) or the .bss / data sections. The decompiler doesn't handle that use case, and likely won't. This change turns tlb_lock_count into a C global variable (so that it will be placed in the .bss / data sections), and splits lockTLBEntry into two parts so the critical section will still fit in a 64-byte aligned region, and therefore be guaranteed to live within a single page.
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0ecff9f3 |
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09-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
unsigned int -> word_t
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2d61910e |
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09-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Rename uint32_t -> word_t in any relevant places
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62727e30 |
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15-Jun-2015 |
Stephen Sherratt <stephen.sherratt@nicta.com.au> |
Using bitfields to track for which priorities there exist non-empty ready queues. Background seL4 organizes threads into ready queues, of which there is one for each domain, for each priority level. The ready queue for a given domain/priority combination can be found by indexing the array `ksReadyQueues` with "domain*num_priorities + priority". Current scheduler implementation To find the non-empty ready queue with the maximum priority for the current domain, seL4 iterates through `ksReadyQueues`, starting with the element corresponding to the current domain and maximum possible priority, and decrementing the priority until a non-empty queue is found. This is problematic in cases where the only ready threads have low priorities, as iterating through many elements of an array effectively flushes the cache. Changes in this patch This patch replaces the iteration with a lookup into a table of bitfields per domain. Using bitfields allows the kernel to determine the highest priority level with a non-empty ready queue for the current domain by counting the leading zeroes in bitfields. This removes the negative cache effects of iterating through an array. Implementation details For each domain, a multilevel table of bitfields is maintained which stores the priority levels within that domain for which there exist ready threads. On a 32-bit architecture, the top level of the table is a 32-bit bitfield where if the ith bit is set, there is at least 1 priority level in [i*32..i*32+31] with a non-empty ready queue. The positions of bits in this bitfield are used as indices into the second level table, which is an array of 32-bit bitfields. The ith bit of the jth bitfield in this array set to 1, indicates that priority level j*32+i has a non-empty ready queue.
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91b7da86 |
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17-Jul-2014 |
TrusthworthySystems <gatekeeper@sel4.systems> |
Release snapshot
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