ARM/SMP: Re-implement atomic exchange taking sel4 IPI into account

smp: Use explicit fences instead of volatile

This provides a more robust and efficient implementation that only forces memory reloads
at explicit known points, instead of the over approximation of every time they are
accessed that is forced by volatile.

SMP: Introduce ENABLE_SMP_SUPPORT

- Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check

SELFOUR-747: SMP/x86: generalize arch-independent IPI code

Fix licenses (the rest)

smp: fix bugs when stalling remote core

- Restart TCB from inside the lock if it is waiting for anything other than IRQ
- Only replace the TCB with idle thread if it is in ThreadState_RunningVM state

Also, this makes the design generic to be shared with arm.

s/D61/DATA61/ in license headers for consistency

[STYLE_FIX]

SMP: use C++11 __atomic builtins instead of legacy __sync buitins

SMP: move lock.h to architecture-independent include/smp

s/__sync_lock_test_and_set/__atomic_exchange_n in lock.h