Searched refs:PPTR_BASE (Results 1 - 11 of 11) sorted by relevance

/seL4-l4v-10.1.1/seL4/include/plat/spike/plat/32/plat_mode/machine/
H A Dhardware.h17 #define PPTR_BASE 0x80000000lu macro
/seL4-l4v-10.1.1/seL4/include/plat/spike/plat/64/plat_mode/machine/
H A Dhardware.h22 #define PPTR_BASE 0xFFFFFFC000000000lu macro
23 /* We steal the top 2 gb entries for the kernel, this means that between PPTR_BASE and
/seL4-l4v-10.1.1/seL4/include/plat/pc99/plat/32/plat_mode/machine/
H A Dhardware.h20 #define PPTR_BASE 0xe0000000 macro
22 #define PPTR_USER_TOP (PPTR_BASE & (~MASK(seL4_LargePageBits)))
46 #define BASE_OFFSET (PPTR_BASE - PADDR_BASE)
/seL4-l4v-10.1.1/seL4/include/plat/pc99/plat/64/plat_mode/machine/
H A Dhardware.h27 #define PPTR_BASE UL_CONST(0xffffff8000000000) macro
43 #define PADDR_TOP (KERNEL_BASE - PPTR_BASE)
50 #define TLBBITMAP_PPTR (PPTR_BASE - TLBBITMAP_PML4_RESERVED)
68 #define BASE_OFFSET PPTR_BASE
/seL4-l4v-10.1.1/seL4/include/plat/spike/plat/machine/
H A Dhardware.h45 #define PADDR_TOP (KERNEL_BASE - PPTR_BASE + PADDR_BASE)
56 #define PPTR_USER_TOP PPTR_BASE
57 #define BASE_OFFSET (PPTR_BASE - PADDR_BASE)
/seL4-l4v-10.1.1/seL4/src/arch/x86/32/kernel/
H A Dvspace_32paging.c73 /* identity mapping from 0 up to PPTR_BASE (virtual address) */
74 for (i = 0; i < (PPTR_BASE >> seL4_LargePageBits); i++) {
90 /* mapping of PPTR_BASE (virtual address) to PADDR_BASE up to end of virtual address space */
91 for (i = 0; i < ((-PPTR_BASE) >> seL4_LargePageBits); i++) {
92 *(_boot_pd + i + (PPTR_BASE >> seL4_LargePageBits)) = pde_pde_large_new_phys(
201 for (i = PPTR_BASE >> seL4_LargePageBits; i < BIT(PD_INDEX_BITS); i++) {
H A Dvspace.c222 /* Mapping of PPTR_BASE (virtual address) to kernel's PADDR_BASE
226 idx = PPTR_BASE >> LARGE_PAGE_BITS;
349 unsigned int virt_pd_start = (PPTR_BASE >> LARGE_PAGE_BITS) - large_pages;
350 unsigned int virt_pg_start = PPTR_BASE - (large_pages << LARGE_PAGE_BITS);
/seL4-l4v-10.1.1/seL4/src/arch/x86/64/kernel/
H A Dvspace.c61 assert(GET_PML4_INDEX(PPTR_BASE) == BIT(PML4_INDEX_BITS) - 1);
70 x64KSKernelPML4[GET_PML4_INDEX(PPTR_BASE)] = pml4e_new(
96 vaddr = PPTR_BASE;
145 assert(GET_PML4_INDEX(PPTR_BASE) == BIT(PML4_INDEX_BITS) - 1);
155 x64KSKernelPML4[GET_PML4_INDEX(PPTR_BASE)] = pml4e_new(
168 x64KSKernelPDPT[GET_PDPT_INDEX(PPTR_BASE) + pd_index] = pdpte_pdpte_pd_new(
192 vaddr = PPTR_BASE;
197 int pd_index = GET_PDPT_INDEX(vaddr) - GET_PDPT_INDEX(PPTR_BASE);
269 x64KSSKIMPML4[GET_PML4_INDEX(PPTR_BASE)] = pml4e_new(
784 * will be equivalent to copying from PPTR_BASE
[all...]
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/64/mode/fastpath/
H A Dfastpath.h32 return unlikely(ret) ? TCB_PTR(ret | PPTR_BASE) : NULL;
/seL4-l4v-10.1.1/seL4/src/arch/x86/machine/
H A Dcapdl.c137 if (exists != 0 && i < PPTR_BASE >> pageBitsForSize(X86_LargePage)) {
/seL4-l4v-10.1.1/seL4/src/arch/riscv/kernel/
H A Dvspace.c108 /* kernel window starts at PPTR_BASE */
109 word_t pptr = PPTR_BASE;
349 for (i = RISCV_GET_PT_INDEX(PPTR_BASE, 1); i < BIT(PT_INDEX_BITS); i++) {

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