Searched refs:PP32_DBG_CTRL (Results 1 - 15 of 15) sorted by relevance

/openwrt/package/kernel/lantiq/ltq-atm/src/
H A Difxmips_atm_ar9.c224 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
233 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
H A Difxmips_atm_amazon_se.c312 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);
331 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
H A Difxmips_atm_danube.c210 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
220 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
H A Difxmips_atm_ppe_amazon_se.h80 #define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) macro
H A Difxmips_atm_ppe_danube.h86 #define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) macro
H A Difxmips_atm_ppe_vr9.h81 #define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) macro
H A Difxmips_atm_ppe_ar9.h92 #define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) macro
/openwrt/package/kernel/lantiq/ltq-ptm/src/
H A Difxmips_ptm_amazon_se.c302 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(pp32));
321 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(pp32));
H A Difxmips_ptm_danube.c297 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
316 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
H A Difxmips_ptm_ar9.c325 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
344 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
H A Difxmips_ptm_ppe_danube.h84 #define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) macro
H A Difxmips_ptm_test.c355 *PP32_DBG_CTRL = DBG_CTRL_START_SET(1);
357 *PP32_DBG_CTRL = DBG_CTRL_STOP_SET(1);
359 *PP32_DBG_CTRL = DBG_CTRL_STEP_SET(1);
680 *PP32_DBG_CTRL(pp32) = DBG_CTRL_RESTART;
682 *PP32_DBG_CTRL(pp32) = DBG_CTRL_STOP;
H A Difxmips_ptm_ppe_amazon_se.h81 #define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) macro
H A Difxmips_ptm_ppe_ar9.h90 #define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) macro
H A Difxmips_ptm_ppe_vr9.h79 #define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) macro

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