1/******************************************************************************
2**
3** FILE NAME    : ifxmips_ptm_ppe_vr9.h
4** PROJECT      : UEIP
5** MODULES      : PTM
6**
7** DATE         : 7 Jul 2009
8** AUTHOR       : Xu Liang
9** DESCRIPTION  : PTM driver header file (PPE register for VR9)
10** COPYRIGHT    :       Copyright (c) 2006
11**                      Infineon Technologies AG
12**                      Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14**    This program is free software; you can redistribute it and/or modify
15**    it under the terms of the GNU General Public License as published by
16**    the Free Software Foundation; either version 2 of the License, or
17**    (at your option) any later version.
18**
19** HISTORY
20** $Date        $Author         $Comment
21** 07 JUL 2009  Xu Liang        Init Version
22*******************************************************************************/
23
24
25
26#ifndef IFXMIPS_PTM_PPE_VR9_H
27#define IFXMIPS_PTM_PPE_VR9_H
28
29
30
31/*
32 *  FPI Configuration Bus Register and Memory Address Mapping
33 */
34#define IFX_PPE                         (KSEG1 | 0x1E200000)
35#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x000000 + (i) * 0x00010000) << 2)))
36#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x001000 + (i) * 0x00010000) << 2)))
37#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x004000 + (i) * 0x00010000) << 2)))
38#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x008000) << 2)))
39#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x009000) << 2)))
40#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00A000) << 2)))
41#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00B000) << 2)))
42#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00D000) << 2)))
43#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00E000) << 2)))
44#define SB_RAM6_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x018000) << 2)))
45
46/*
47 *  DWORD-Length of Memory Blocks
48 */
49#define PP32_DEBUG_REG_DWLEN            0x0030
50#define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)
51#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)
52#define SB_RAM0_DWLEN                   0x1000
53#define SB_RAM1_DWLEN                   0x1000
54#define SB_RAM2_DWLEN                   0x1000
55#define SB_RAM3_DWLEN                   0x1000
56#define SB_RAM6_DWLEN                   0x8000
57#define QSB_CONF_REG_DWLEN              0x0100
58
59/*
60 *  PP32 to FPI Address Mapping
61 */
62#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x1FFF)) ? PPE_REG_ADDR((__sb_addr)) :           \
63                                                                   (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :  \
64                                                                   (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x3000) :  \
65                                                                   (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4FFF)) ? SB_RAM2_ADDR((__sb_addr) - 0x4000) :  \
66                                                                   (((__sb_addr) >= 0x5000) && ((__sb_addr) <= 0x5FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x5000) :  \
67                                                                   (((__sb_addr) >= 0x7000) && ((__sb_addr) <= 0x7FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x7000) :  \
68                                                                   (((__sb_addr) >= 0x8000) && ((__sb_addr) <= 0xFFFF)) ? SB_RAM6_ADDR((__sb_addr) - 0x8000) :  \
69                                                                0))
70
71/*
72 *  PP32 Debug Control Register
73 */
74#define NUM_OF_PP32                             2
75
76#define PP32_FREEZE                             PPE_REG_ADDR(0x0000)
77#define PP32_SRST                               PPE_REG_ADDR(0x0020)
78
79#define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)
80
81#define DBG_CTRL_RESTART                        0
82#define DBG_CTRL_STOP                           1
83
84#define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)
85  #define PP32_CTRL_CMD_RESTART                 (1 << 0)
86  #define PP32_CTRL_CMD_STOP                    (1 << 1)
87  #define PP32_CTRL_CMD_STEP                    (1 << 2)
88  #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)
89
90#define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)
91  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)
92  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)
93  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)
94  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)
95  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)
96  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)
97  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)
98  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)
99  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))
100  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))
101  #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))
102  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))
103
104#define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)
105#define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)
106#define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)
107#define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)
108#define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)
109#define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)
110#define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)
111#define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)
112  #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))
113  #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)
114  #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only
115  #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)
116  #define PP32_BRK_COMPARE_EN                   (1 << 7)
117
118#define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)
119  #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))
120  #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))
121  #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))
122  #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))
123  #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))
124  #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))
125  #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))
126  #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))
127  #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))
128  #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))
129  #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))
130  #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))
131
132#define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)
133#define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)
134#define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)
135  #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))
136  #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))
137  #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))
138  #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)
139
140#define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)
141  #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))
142  #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))
143  #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))
144  #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))
145  #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))
146  #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))
147  #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))
148  #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))
149  #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)
150
151#define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)
152#define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))
153
154/*
155 *  SAR Registers
156 */
157#define SAR_MODE_CFG                    PPE_REG_ADDR(0x080A)
158#define SAR_RX_CMD_CNT                  PPE_REG_ADDR(0x080B)
159#define SAR_TX_CMD_CNT                  PPE_REG_ADDR(0x080C)
160#define SAR_RX_CTX_CFG                  PPE_REG_ADDR(0x080D)
161#define SAR_TX_CTX_CFG                  PPE_REG_ADDR(0x080E)
162#define SAR_TX_CMD_DONE_CNT             PPE_REG_ADDR(0x080F)
163#define SAR_POLY_CFG_SET0               PPE_REG_ADDR(0x0812)
164#define SAR_POLY_CFG_SET1               PPE_REG_ADDR(0x0813)
165#define SAR_POLY_CFG_SET2               PPE_REG_ADDR(0x0814)
166#define SAR_POLY_CFG_SET3               PPE_REG_ADDR(0x0815)
167#define SAR_CRC_SIZE_CFG                PPE_REG_ADDR(0x0816)
168
169/*
170 *  PDMA/EMA Registers
171 */
172#define PDMA_CFG                        PPE_REG_ADDR(0x0A00)
173#define PDMA_RX_CMDCNT                  PPE_REG_ADDR(0x0A01)
174#define PDMA_TX_CMDCNT                  PPE_REG_ADDR(0x0A02)
175#define PDMA_RX_FWDATACNT               PPE_REG_ADDR(0x0A03)
176#define PDMA_TX_FWDATACNT               PPE_REG_ADDR(0x0A04)
177#define PDMA_RX_CTX_CFG                 PPE_REG_ADDR(0x0A05)
178#define PDMA_TX_CTX_CFG                 PPE_REG_ADDR(0x0A06)
179#define PDMA_RX_MAX_LEN_REG             PPE_REG_ADDR(0x0A07)
180#define PDMA_RX_DELAY_CFG               PPE_REG_ADDR(0x0A08)
181#define PDMA_INT_FIFO_RD                PPE_REG_ADDR(0x0A09)
182#define PDMA_ISR                        PPE_REG_ADDR(0x0A0A)
183#define PDMA_IER                        PPE_REG_ADDR(0x0A0B)
184#define PDMA_SUBID                      PPE_REG_ADDR(0x0A0C)
185#define PDMA_BAR0                       PPE_REG_ADDR(0x0A0D)
186#define PDMA_BAR1                       PPE_REG_ADDR(0x0A0E)
187
188#define SAR_PDMA_RX_CMDBUF_CFG          PPE_REG_ADDR(0x0F00)
189#define SAR_PDMA_TX_CMDBUF_CFG          PPE_REG_ADDR(0x0F01)
190#define SAR_PDMA_RX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F02)
191#define SAR_PDMA_TX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F03)
192#define SAR_PDMA_RX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F04)
193#define SAR_PDMA_TX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F05)
194
195#define PDMA_ALIGNMENT                  32              //  same as Central DMA because of descriptor swap
196#define EMA_ALIGNMENT                   PDMA_ALIGNMENT
197
198/*
199 *  Mailbox IGU1 Interrupt
200 */
201#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24
202
203
204
205#endif  //  IFXMIPS_PTM_PPE_VR9_H
206