1/****************************************************************************** 2** 3** FILE NAME : ifxmips_atm_ppe_ar9.h 4** PROJECT : UEIP 5** MODULES : ATM (ADSL) 6** 7** DATE : 1 AUG 2005 8** AUTHOR : Xu Liang 9** DESCRIPTION : ATM Driver (PPE Registers) 10** COPYRIGHT : Copyright (c) 2006 11** Infineon Technologies AG 12** Am Campeon 1-12, 85579 Neubiberg, Germany 13** 14** This program is free software; you can redistribute it and/or modify 15** it under the terms of the GNU General Public License as published by 16** the Free Software Foundation; either version 2 of the License, or 17** (at your option) any later version. 18** 19** HISTORY 20** $Date $Author $Comment 21** 4 AUG 2005 Xu Liang Initiate Version 22** 23 OCT 2006 Xu Liang Add GPL header. 23** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) 24*******************************************************************************/ 25 26 27 28#ifndef IFXMIPS_ATM_PPE_AR9_H 29#define IFXMIPS_ATM_PPE_AR9_H 30 31 32 33/* 34 * FPI Configuration Bus Register and Memory Address Mapping 35 */ 36#define IFX_PPE (KSEG1 | 0x1E180000) 37#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) 38#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) 39#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) 40#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) 41#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) 42#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) 43#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) 44#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) 45#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) 46#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) 47#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) 48#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2))) 49#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8800) << 2))) 50#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9000) << 2))) 51#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9800) << 2))) 52#define SB_RAM4_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xA000) << 2))) 53#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) 54 55/* 56 * DWORD-Length of Memory Blocks 57 */ 58#define PP32_DEBUG_REG_DWLEN 0x0030 59#define PPM_INT_REG_DWLEN 0x0010 60#define PP32_INTERNAL_RES_DWLEN 0x00C0 61#define CDM_CODE_MEMORYn_DWLEN(n) 0x1000 62#define PPE_REG_DWLEN 0x1000 63#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) 64#define PPM_INT_UNIT_DWLEN 0x0100 65#define PPM_TIMER0_DWLEN 0x0100 66#define PPM_TASK_IND_REG_DWLEN 0x0100 67#define PPS_BRK_DWLEN 0x0100 68#define PPM_TIMER1_DWLEN 0x0100 69#define SB_RAM0_DWLEN 0x0800 70#define SB_RAM1_DWLEN 0x0800 71#define SB_RAM2_DWLEN 0x0800 72#define SB_RAM3_DWLEN 0x0800 73#define SB_RAM4_DWLEN 0x0C00 74#define QSB_CONF_REG_DWLEN 0x0100 75 76/* 77 * PP32 to FPI Address Mapping 78 */ 79#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PPE_REG_ADDR((__sb_addr)): \ 80 (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x27FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \ 81 (((__sb_addr) >= 0x2800) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2800) : \ 82 (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x37FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x3000) : \ 83 (((__sb_addr) >= 0x3800) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3800) : \ 84 (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4BFF)) ? SB_RAM4_ADDR((__sb_addr) - 0x4000) : \ 85 0)) 86 87/* 88 * PP32 Debug Control Register 89 */ 90#define NUM_OF_PP32 1 91 92#define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) 93 94#define DBG_CTRL_RESTART 0 95#define DBG_CTRL_STOP 1 96 97#define PP32_CTRL_CMD(n) PP32_DEBUG_REG_ADDR(n, 0x0B00) 98 #define PP32_CTRL_CMD_RESTART (1 << 0) 99 #define PP32_CTRL_CMD_STOP (1 << 1) 100 #define PP32_CTRL_CMD_STEP (1 << 2) 101 #define PP32_CTRL_CMD_BREAKOUT (1 << 3) 102 103#define PP32_CTRL_OPT(n) PP32_DEBUG_REG_ADDR(n, 0x0C00) 104 #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON (3 << 0) 105 #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF (2 << 0) 106 #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON (3 << 2) 107 #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2) 108 #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON (3 << 4) 109 #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF (2 << 4) 110 #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON (3 << 6) 111 #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF (2 << 6) 112 #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n) (*PP32_CTRL_OPT(n) & (1 << 0)) 113 #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 2)) 114 #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 4)) 115 #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n) (*PP32_CTRL_OPT(n) & (1 << 6)) 116 117#define PP32_BRK_PC(n, i) PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2) 118#define PP32_BRK_PC_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2) 119#define PP32_BRK_DATA_ADDR(n, i) PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2) 120#define PP32_BRK_DATA_ADDR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2) 121#define PP32_BRK_DATA_VALUE_RD(n, i) PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2) 122#define PP32_BRK_DATA_VALUE_RD_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2) 123#define PP32_BRK_DATA_VALUE_WR(n, i) PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2) 124#define PP32_BRK_DATA_VALUE_WR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2) 125 #define PP32_BRK_CONTEXT_MASK(i) (1 << (i)) 126 #define PP32_BRK_CONTEXT_MASK_EN (1 << 4) 127 #define PP32_BRK_COMPARE_GREATER_EQUAL (1 << 5) // valid for break data value rd/wr only 128 #define PP32_BRK_COMPARE_LOWER_EQUAL (1 << 6) 129 #define PP32_BRK_COMPARE_EN (1 << 7) 130 131#define PP32_BRK_TRIG(n) PP32_DEBUG_REG_ADDR(n, 0x0F00) 132 #define PP32_BRK_GRPi_PCn_ON(i, n) ((3 << ((n) * 2)) << ((i) * 16)) 133 #define PP32_BRK_GRPi_PCn_OFF(i, n) ((2 << ((n) * 2)) << ((i) * 16)) 134 #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n) ((3 << ((n) * 2 + 4)) << ((i) * 16)) 135 #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n) ((2 << ((n) * 2 + 4)) << ((i) * 16)) 136 #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16)) 137 #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16)) 138 #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16)) 139 #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16)) 140 #define PP32_BRK_GRPi_PCn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8))) 141 #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8))) 142 #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8))) 143 #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8))) 144 145#define PP32_CPU_STATUS(n) PP32_DEBUG_REG_ADDR(n, 0x0D00) 146#define PP32_HALT_STAT(n) PP32_CPU_STATUS(n) 147#define PP32_DBG_CUR_PC(n) PP32_CPU_STATUS(n) 148 #define PP32_CPU_USER_STOPPED(n) (*PP32_CPU_STATUS(n) & (1 << 0)) 149 #define PP32_CPU_USER_BREAKIN_RCV(n) (*PP32_CPU_STATUS(n) & (1 << 1)) 150 #define PP32_CPU_USER_BREAKPOINT_MET(n) (*PP32_CPU_STATUS(n) & (1 << 2)) 151 #define PP32_CPU_CUR_PC(n) (*PP32_CPU_STATUS(n) >> 16) 152 153#define PP32_BREAKPOINT_REASONS(n) PP32_DEBUG_REG_ADDR(n, 0x0A00) 154 #define PP32_BRK_PC_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << (i))) 155 #define PP32_BRK_DATA_ADDR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2))) 156 #define PP32_BRK_DATA_VALUE_RD_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4))) 157 #define PP32_BRK_DATA_VALUE_WR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6))) 158 #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8))) 159 #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9))) 160 #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12))) 161 #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13))) 162 #define PP32_BRK_CUR_CONTEXT(n) ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03) 163 164#define PP32_GP_REG_BASE(n) PP32_DEBUG_REG_ADDR(n, 0x0E00) 165#define PP32_GP_CONTEXTi_REGn(n, i, j) PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j)) 166 167/* 168 * EMA Registers 169 */ 170#define EMA_CMDCFG PPE_REG_ADDR(0x0A00) 171#define EMA_DATACFG PPE_REG_ADDR(0x0A01) 172#define EMA_CMDCNT PPE_REG_ADDR(0x0A02) 173#define EMA_DATACNT PPE_REG_ADDR(0x0A03) 174#define EMA_ISR PPE_REG_ADDR(0x0A04) 175#define EMA_IER PPE_REG_ADDR(0x0A05) 176#define EMA_CFG PPE_REG_ADDR(0x0A06) 177#define EMA_SUBID PPE_REG_ADDR(0x0A07) 178 179#define EMA_ALIGNMENT 4 180 181/* 182 * Mailbox IGU1 Interrupt 183 */ 184#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 185 186 187 188#endif // IFXMIPS_ATM_PPE_AR9_H 189