Searched refs:reg_addr (Results 1 - 19 of 19) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/common/io/chxge/com/
H A Dcphy.h36 int reg_addr, unsigned int *val);
38 int reg_addr, unsigned int val);
93 int reg_addr, unsigned int *val);
95 int reg_addr, unsigned int val);
H A Dch_subr.c277 int reg_addr, unsigned int *val)
289 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
296 int reg_addr, unsigned int val)
308 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));
360 int reg_addr, unsigned int *valp)
362 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
378 int reg_addr, unsigned int val)
380 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
407 int reg_addr, unsigned int *valp)
415 (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
276 fpga_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *val) argument
295 fpga_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val) argument
359 mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *valp) argument
377 mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val) argument
432 mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *valp) argument
457 mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val) argument
[all...]
/opensolaris-onvv-gate/usr/src/uts/sun4u/io/
H A Diocache.c185 volatile uint64_t *reg_addr; local
191 for (i = 0, reg_addr = softsp->str_buf_pg_tag_diag;
192 i < STREAM_CACHE_LINES; i++, reg_addr++) {
195 reg = *reg_addr;
204 (void *)reg_addr, hi, lo));
H A Dpmubus.c595 addr = regp->reg_addr & ~MAPPING_SHARED_BITS_MASK;
620 if (regp->reg_addr & MAPPING_SHARED_BITS_MASK)
706 pmubus_rp.reg_addr = ((uint64_t)
741 if ((pmubus_rp.reg_addr + off) >
742 (pmubus_rp.reg_addr + pmubus_rp.reg_size)) {
747 pmubus_rp.reg_addr += off;
773 pmubus_mapreqp->mapreq_addr = pmubus_rp.reg_addr;
/opensolaris-onvv-gate/usr/src/uts/sun4u/sys/
H A Dpmubus.h47 uint64_t reg_addr; member in struct:__anon10281
/opensolaris-onvv-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_phy.h103 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
105 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.c436 * @reg_addr: 32 bit address of PHY register to read
442 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, argument
448 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
455 * @reg_addr: 32 bit PHY register to write
460 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, argument
466 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
H A Dixgbe_api.h56 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
58 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
H A Dixgbe_phy.c284 * @reg_addr: 32 bit address of PHY register to read
288 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, argument
309 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
341 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
385 * @reg_addr: 32 bit PHY register to write
389 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, argument
414 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
445 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
/opensolaris-onvv-gate/usr/src/grub/grub-0.97/netboot/
H A De1000.c110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
111 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
113 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
2810 * reg_addr - address of the PHY register to read
2814 uint32_t reg_addr,
2822 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2824 (uint16_t)reg_addr)))
2828 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2836 uint32_t reg_addr,
2813 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data) argument
2835 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data) argument
2916 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) argument
2938 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) argument
[all...]
/opensolaris-onvv-gate/usr/src/lib/udapl/libdat/include/dat/
H A Dudat_redirection.h59 lmr, lmr_context, rmr_context, reg_len, reg_addr) \
71 (reg_addr))
/opensolaris-onvv-gate/usr/src/uts/common/io/audio/drv/audiots/
H A Daudiots.c1151 uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg; local
1170 if (!(ddi_get16(handle, reg_addr) &
1173 ddi_put16(handle, reg_addr, reg);
1187 if (!(ddi_get16(handle, reg_addr) &
/opensolaris-onvv-gate/usr/src/uts/sun4u/io/i2c/nexus/
H A Dsmbus.c737 uint8_t *reg_addr = smbus->smbus_regaddr; local
741 ddi_put8(hp, &reg_addr[reg], data);
744 &reg_addr[reg], data));
/opensolaris-onvv-gate/usr/src/uts/common/io/e1000g/
H A De1000_ich8lan.c762 u16 word_addr, reg_data, reg_addr, phy_page = 0; local
846 1, &reg_addr);
851 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
861 if (reg_addr & LCD_CFG_PHY_ADDR_BIT) {
863 reg_addr &= PHY_REG_MASK;
867 reg_addr |= phy_page;
869 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
/opensolaris-onvv-gate/usr/src/uts/common/io/ntxn/
H A Dniu.c134 address.reg_addr = (unm_crbword_t)reg;
H A Dunm_inc.h984 reg_addr:5, /* which mgmt register we want to talk to */ member in struct:__anon6530
/opensolaris-onvv-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_mac_hw.h1325 uint32_t reg_addr : 5; member in struct:_mif_cfg_t::__anon8487::__anon8488
1335 uint32_t reg_addr : 5;
/opensolaris-onvv-gate/usr/src/uts/sun4u/io/pci/
H A Dpcisch.c1071 volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx; local
1074 if (!*reg_addr) {
1080 matchreg = *reg_addr; /* re-fetch after 1st flush */
1091 if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */
/opensolaris-onvv-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_mac.c3426 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */
3466 mif_cfg.bits.w0.reg_addr = device; /* Register address */

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