1/************************************************************************** 2Etherboot - BOOTP/TFTP Bootstrap Program 3Inter Pro 1000 for Etherboot 4Drivers are port from Intel's Linux driver e1000-4.3.15 5 6***************************************************************************/ 7/******************************************************************************* 8 9 10 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33*******************************************************************************/ 34/* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 * 44 * Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by 45 * Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc. 46 * 47 * 01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net> 48 */ 49 50/* to get some global routines like printf */ 51#include "etherboot.h" 52/* to get the interface to the body of the program */ 53#include "nic.h" 54/* to get the PCI support functions, if this is a PCI NIC */ 55#include "pci.h" 56#include "timer.h" 57 58typedef unsigned char *dma_addr_t; 59 60typedef enum { 61 FALSE = 0, 62 TRUE = 1 63} boolean_t; 64 65#define DEBUG 0 66 67 68/* Some pieces of code are disabled with #if 0 ... #endif. 69 * They are not deleted to show where the etherboot driver differs 70 * from the linux driver below the function level. 71 * Some member variables of the hw struct have been eliminated 72 * and the corresponding inplace checks inserted instead. 73 * Pieces such as LED handling that we definitely don't need are deleted. 74 * 75 * The following defines should not be needed normally, 76 * but may be helpful for debugging purposes. */ 77 78/* Define this if you want to program the transmission control register 79 * the way the Linux driver does it. */ 80#undef LINUX_DRIVER_TCTL 81 82/* Define this to behave more like the Linux driver. */ 83#undef LINUX_DRIVER 84 85#include "e1000_hw.h" 86 87/* NIC specific static variables go here */ 88static struct e1000_hw hw; 89static char tx_pool[128 + 16]; 90static char rx_pool[128 + 16]; 91static char packet[2096]; 92 93static struct e1000_tx_desc *tx_base; 94static struct e1000_rx_desc *rx_base; 95 96static int tx_tail; 97static int rx_tail, rx_last; 98 99/* Function forward declarations */ 100static int e1000_setup_link(struct e1000_hw *hw); 101static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 102static int e1000_setup_copper_link(struct e1000_hw *hw); 103static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 104static void e1000_config_collision_dist(struct e1000_hw *hw); 105static int e1000_config_mac_to_phy(struct e1000_hw *hw); 106static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 107static int e1000_check_for_link(struct e1000_hw *hw); 108static int e1000_wait_autoneg(struct e1000_hw *hw); 109static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex); 110static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 111static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 112static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data); 113static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data); 114static void e1000_phy_hw_reset(struct e1000_hw *hw); 115static int e1000_phy_reset(struct e1000_hw *hw); 116static int e1000_detect_gig_phy(struct e1000_hw *hw); 117 118/* Printing macros... */ 119 120#define E1000_ERR(args...) printf("e1000: " args) 121 122#if DEBUG >= 3 123#define E1000_DBG(args...) printf("e1000: " args) 124#else 125#define E1000_DBG(args...) 126#endif 127 128#define MSGOUT(S, A, B) printk(S "\n", A, B) 129#if DEBUG >= 2 130#define DEBUGFUNC(F) DEBUGOUT(F "\n"); 131#else 132#define DEBUGFUNC(F) 133#endif 134#if DEBUG >= 1 135#define DEBUGOUT(S) printf(S) 136#define DEBUGOUT1(S,A) printf(S,A) 137#define DEBUGOUT2(S,A,B) printf(S,A,B) 138#define DEBUGOUT3(S,A,B,C) printf(S,A,B,C) 139#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G) 140#else 141#define DEBUGOUT(S) 142#define DEBUGOUT1(S,A) 143#define DEBUGOUT2(S,A,B) 144#define DEBUGOUT3(S,A,B,C) 145#define DEBUGOUT7(S,A,B,C,D,E,F,G) 146#endif 147 148#define E1000_WRITE_REG(a, reg, value) ( \ 149 ((a)->mac_type >= e1000_82543) ? \ 150 (writel((value), ((a)->hw_addr + E1000_##reg))) : \ 151 (writel((value), ((a)->hw_addr + E1000_82542_##reg)))) 152 153#define E1000_READ_REG(a, reg) ( \ 154 ((a)->mac_type >= e1000_82543) ? \ 155 readl((a)->hw_addr + E1000_##reg) : \ 156 readl((a)->hw_addr + E1000_82542_##reg)) 157 158#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 159 ((a)->mac_type >= e1000_82543) ? \ 160 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \ 161 writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))) 162 163#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 164 ((a)->mac_type >= e1000_82543) ? \ 165 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \ 166 readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))) 167 168#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 169 170uint32_t 171e1000_io_read(struct e1000_hw *hw __unused, uint32_t port) 172{ 173 return inl(port); 174} 175 176void 177e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value) 178{ 179 outl(value, port); 180} 181 182static inline void e1000_pci_set_mwi(struct e1000_hw *hw) 183{ 184 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 185} 186 187static inline void e1000_pci_clear_mwi(struct e1000_hw *hw) 188{ 189 pci_write_config_word(hw->pdev, PCI_COMMAND, 190 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 191} 192 193/****************************************************************************** 194 * Raises the EEPROM's clock input. 195 * 196 * hw - Struct containing variables accessed by shared code 197 * eecd - EECD's current value 198 *****************************************************************************/ 199static void 200e1000_raise_ee_clk(struct e1000_hw *hw, 201 uint32_t *eecd) 202{ 203 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 204 * wait <delay> microseconds. 205 */ 206 *eecd = *eecd | E1000_EECD_SK; 207 E1000_WRITE_REG(hw, EECD, *eecd); 208 E1000_WRITE_FLUSH(hw); 209 udelay(hw->eeprom.delay_usec); 210} 211 212/****************************************************************************** 213 * Lowers the EEPROM's clock input. 214 * 215 * hw - Struct containing variables accessed by shared code 216 * eecd - EECD's current value 217 *****************************************************************************/ 218static void 219e1000_lower_ee_clk(struct e1000_hw *hw, 220 uint32_t *eecd) 221{ 222 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 223 * wait 50 microseconds. 224 */ 225 *eecd = *eecd & ~E1000_EECD_SK; 226 E1000_WRITE_REG(hw, EECD, *eecd); 227 E1000_WRITE_FLUSH(hw); 228 udelay(hw->eeprom.delay_usec); 229} 230 231/****************************************************************************** 232 * Shift data bits out to the EEPROM. 233 * 234 * hw - Struct containing variables accessed by shared code 235 * data - data to send to the EEPROM 236 * count - number of bits to shift out 237 *****************************************************************************/ 238static void 239e1000_shift_out_ee_bits(struct e1000_hw *hw, 240 uint16_t data, 241 uint16_t count) 242{ 243 struct e1000_eeprom_info *eeprom = &hw->eeprom; 244 uint32_t eecd; 245 uint32_t mask; 246 247 /* We need to shift "count" bits out to the EEPROM. So, value in the 248 * "data" parameter will be shifted out to the EEPROM one bit at a time. 249 * In order to do this, "data" must be broken down into bits. 250 */ 251 mask = 0x01 << (count - 1); 252 eecd = E1000_READ_REG(hw, EECD); 253 if (eeprom->type == e1000_eeprom_microwire) { 254 eecd &= ~E1000_EECD_DO; 255 } else if (eeprom->type == e1000_eeprom_spi) { 256 eecd |= E1000_EECD_DO; 257 } 258 do { 259 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 260 * and then raising and then lowering the clock (the SK bit controls 261 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 262 * by setting "DI" to "0" and then raising and then lowering the clock. 263 */ 264 eecd &= ~E1000_EECD_DI; 265 266 if(data & mask) 267 eecd |= E1000_EECD_DI; 268 269 E1000_WRITE_REG(hw, EECD, eecd); 270 E1000_WRITE_FLUSH(hw); 271 272 udelay(eeprom->delay_usec); 273 274 e1000_raise_ee_clk(hw, &eecd); 275 e1000_lower_ee_clk(hw, &eecd); 276 277 mask = mask >> 1; 278 279 } while(mask); 280 281 /* We leave the "DI" bit set to "0" when we leave this routine. */ 282 eecd &= ~E1000_EECD_DI; 283 E1000_WRITE_REG(hw, EECD, eecd); 284} 285 286/****************************************************************************** 287 * Shift data bits in from the EEPROM 288 * 289 * hw - Struct containing variables accessed by shared code 290 *****************************************************************************/ 291static uint16_t 292e1000_shift_in_ee_bits(struct e1000_hw *hw, 293 uint16_t count) 294{ 295 uint32_t eecd; 296 uint32_t i; 297 uint16_t data; 298 299 /* In order to read a register from the EEPROM, we need to shift 'count' 300 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 301 * input to the EEPROM (setting the SK bit), and then reading the value of 302 * the "DO" bit. During this "shifting in" process the "DI" bit should 303 * always be clear. 304 */ 305 306 eecd = E1000_READ_REG(hw, EECD); 307 308 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 309 data = 0; 310 311 for(i = 0; i < count; i++) { 312 data = data << 1; 313 e1000_raise_ee_clk(hw, &eecd); 314 315 eecd = E1000_READ_REG(hw, EECD); 316 317 eecd &= ~(E1000_EECD_DI); 318 if(eecd & E1000_EECD_DO) 319 data |= 1; 320 321 e1000_lower_ee_clk(hw, &eecd); 322 } 323 324 return data; 325} 326 327/****************************************************************************** 328 * Prepares EEPROM for access 329 * 330 * hw - Struct containing variables accessed by shared code 331 * 332 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 333 * function should be called before issuing a command to the EEPROM. 334 *****************************************************************************/ 335static int32_t 336e1000_acquire_eeprom(struct e1000_hw *hw) 337{ 338 struct e1000_eeprom_info *eeprom = &hw->eeprom; 339 uint32_t eecd, i=0; 340 341 eecd = E1000_READ_REG(hw, EECD); 342 343 /* Request EEPROM Access */ 344 if(hw->mac_type > e1000_82544) { 345 eecd |= E1000_EECD_REQ; 346 E1000_WRITE_REG(hw, EECD, eecd); 347 eecd = E1000_READ_REG(hw, EECD); 348 while((!(eecd & E1000_EECD_GNT)) && 349 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 350 i++; 351 udelay(5); 352 eecd = E1000_READ_REG(hw, EECD); 353 } 354 if(!(eecd & E1000_EECD_GNT)) { 355 eecd &= ~E1000_EECD_REQ; 356 E1000_WRITE_REG(hw, EECD, eecd); 357 DEBUGOUT("Could not acquire EEPROM grant\n"); 358 return -E1000_ERR_EEPROM; 359 } 360 } 361 362 /* Setup EEPROM for Read/Write */ 363 364 if (eeprom->type == e1000_eeprom_microwire) { 365 /* Clear SK and DI */ 366 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 367 E1000_WRITE_REG(hw, EECD, eecd); 368 369 /* Set CS */ 370 eecd |= E1000_EECD_CS; 371 E1000_WRITE_REG(hw, EECD, eecd); 372 } else if (eeprom->type == e1000_eeprom_spi) { 373 /* Clear SK and CS */ 374 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 375 E1000_WRITE_REG(hw, EECD, eecd); 376 udelay(1); 377 } 378 379 return E1000_SUCCESS; 380} 381 382/****************************************************************************** 383 * Returns EEPROM to a "standby" state 384 * 385 * hw - Struct containing variables accessed by shared code 386 *****************************************************************************/ 387static void 388e1000_standby_eeprom(struct e1000_hw *hw) 389{ 390 struct e1000_eeprom_info *eeprom = &hw->eeprom; 391 uint32_t eecd; 392 393 eecd = E1000_READ_REG(hw, EECD); 394 395 if(eeprom->type == e1000_eeprom_microwire) { 396 397 /* Deselect EEPROM */ 398 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 399 E1000_WRITE_REG(hw, EECD, eecd); 400 E1000_WRITE_FLUSH(hw); 401 udelay(eeprom->delay_usec); 402 403 /* Clock high */ 404 eecd |= E1000_EECD_SK; 405 E1000_WRITE_REG(hw, EECD, eecd); 406 E1000_WRITE_FLUSH(hw); 407 udelay(eeprom->delay_usec); 408 409 /* Select EEPROM */ 410 eecd |= E1000_EECD_CS; 411 E1000_WRITE_REG(hw, EECD, eecd); 412 E1000_WRITE_FLUSH(hw); 413 udelay(eeprom->delay_usec); 414 415 /* Clock low */ 416 eecd &= ~E1000_EECD_SK; 417 E1000_WRITE_REG(hw, EECD, eecd); 418 E1000_WRITE_FLUSH(hw); 419 udelay(eeprom->delay_usec); 420 } else if(eeprom->type == e1000_eeprom_spi) { 421 /* Toggle CS to flush commands */ 422 eecd |= E1000_EECD_CS; 423 E1000_WRITE_REG(hw, EECD, eecd); 424 E1000_WRITE_FLUSH(hw); 425 udelay(eeprom->delay_usec); 426 eecd &= ~E1000_EECD_CS; 427 E1000_WRITE_REG(hw, EECD, eecd); 428 E1000_WRITE_FLUSH(hw); 429 udelay(eeprom->delay_usec); 430 } 431} 432 433/****************************************************************************** 434 * Terminates a command by inverting the EEPROM's chip select pin 435 * 436 * hw - Struct containing variables accessed by shared code 437 *****************************************************************************/ 438static void 439e1000_release_eeprom(struct e1000_hw *hw) 440{ 441 uint32_t eecd; 442 443 eecd = E1000_READ_REG(hw, EECD); 444 445 if (hw->eeprom.type == e1000_eeprom_spi) { 446 eecd |= E1000_EECD_CS; /* Pull CS high */ 447 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 448 449 E1000_WRITE_REG(hw, EECD, eecd); 450 451 udelay(hw->eeprom.delay_usec); 452 } else if(hw->eeprom.type == e1000_eeprom_microwire) { 453 /* cleanup eeprom */ 454 455 /* CS on Microwire is active-high */ 456 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 457 458 E1000_WRITE_REG(hw, EECD, eecd); 459 460 /* Rising edge of clock */ 461 eecd |= E1000_EECD_SK; 462 E1000_WRITE_REG(hw, EECD, eecd); 463 E1000_WRITE_FLUSH(hw); 464 udelay(hw->eeprom.delay_usec); 465 466 /* Falling edge of clock */ 467 eecd &= ~E1000_EECD_SK; 468 E1000_WRITE_REG(hw, EECD, eecd); 469 E1000_WRITE_FLUSH(hw); 470 udelay(hw->eeprom.delay_usec); 471 } 472 473 /* Stop requesting EEPROM access */ 474 if(hw->mac_type > e1000_82544) { 475 eecd &= ~E1000_EECD_REQ; 476 E1000_WRITE_REG(hw, EECD, eecd); 477 } 478} 479 480/****************************************************************************** 481 * Reads a 16 bit word from the EEPROM. 482 * 483 * hw - Struct containing variables accessed by shared code 484 *****************************************************************************/ 485static int32_t 486e1000_spi_eeprom_ready(struct e1000_hw *hw) 487{ 488 uint16_t retry_count = 0; 489 uint8_t spi_stat_reg; 490 491 /* Read "Status Register" repeatedly until the LSB is cleared. The 492 * EEPROM will signal that the command has been completed by clearing 493 * bit 0 of the internal status register. If it's not cleared within 494 * 5 milliseconds, then error out. 495 */ 496 retry_count = 0; 497 do { 498 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 499 hw->eeprom.opcode_bits); 500 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 501 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 502 break; 503 504 udelay(5); 505 retry_count += 5; 506 507 } while(retry_count < EEPROM_MAX_RETRY_SPI); 508 509 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 510 * only 0-5mSec on 5V devices) 511 */ 512 if(retry_count >= EEPROM_MAX_RETRY_SPI) { 513 DEBUGOUT("SPI EEPROM Status error\n"); 514 return -E1000_ERR_EEPROM; 515 } 516 517 return E1000_SUCCESS; 518} 519 520/****************************************************************************** 521 * Reads a 16 bit word from the EEPROM. 522 * 523 * hw - Struct containing variables accessed by shared code 524 * offset - offset of word in the EEPROM to read 525 * data - word read from the EEPROM 526 * words - number of words to read 527 *****************************************************************************/ 528static int 529e1000_read_eeprom(struct e1000_hw *hw, 530 uint16_t offset, 531 uint16_t words, 532 uint16_t *data) 533{ 534 struct e1000_eeprom_info *eeprom = &hw->eeprom; 535 uint32_t i = 0; 536 537 DEBUGFUNC("e1000_read_eeprom"); 538 539 /* A check for invalid values: offset too large, too many words, and not 540 * enough words. 541 */ 542 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) || 543 (words == 0)) { 544 DEBUGOUT("\"words\" parameter out of bounds\n"); 545 return -E1000_ERR_EEPROM; 546 } 547 548 /* Prepare the EEPROM for reading */ 549 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) 550 return -E1000_ERR_EEPROM; 551 552 if(eeprom->type == e1000_eeprom_spi) { 553 uint16_t word_in; 554 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 555 556 if(e1000_spi_eeprom_ready(hw)) { 557 e1000_release_eeprom(hw); 558 return -E1000_ERR_EEPROM; 559 } 560 561 e1000_standby_eeprom(hw); 562 563 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 564 if((eeprom->address_bits == 8) && (offset >= 128)) 565 read_opcode |= EEPROM_A8_OPCODE_SPI; 566 567 /* Send the READ command (opcode + addr) */ 568 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 569 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); 570 571 /* Read the data. The address of the eeprom internally increments with 572 * each byte (spi) being read, saving on the overhead of eeprom setup 573 * and tear-down. The address counter will roll over if reading beyond 574 * the size of the eeprom, thus allowing the entire memory to be read 575 * starting from any offset. */ 576 for (i = 0; i < words; i++) { 577 word_in = e1000_shift_in_ee_bits(hw, 16); 578 data[i] = (word_in >> 8) | (word_in << 8); 579 } 580 } else if(eeprom->type == e1000_eeprom_microwire) { 581 for (i = 0; i < words; i++) { 582 /* Send the READ command (opcode + addr) */ 583 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 584 eeprom->opcode_bits); 585 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 586 eeprom->address_bits); 587 588 /* Read the data. For microwire, each word requires the overhead 589 * of eeprom setup and tear-down. */ 590 data[i] = e1000_shift_in_ee_bits(hw, 16); 591 e1000_standby_eeprom(hw); 592 } 593 } 594 595 /* End this read operation */ 596 e1000_release_eeprom(hw); 597 598 return E1000_SUCCESS; 599} 600 601/****************************************************************************** 602 * Verifies that the EEPROM has a valid checksum 603 * 604 * hw - Struct containing variables accessed by shared code 605 * 606 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 607 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 608 * valid. 609 *****************************************************************************/ 610static int 611e1000_validate_eeprom_checksum(struct e1000_hw *hw) 612{ 613 uint16_t checksum = 0; 614 uint16_t i, eeprom_data; 615 616 DEBUGFUNC("e1000_validate_eeprom_checksum"); 617 618 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 619 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 620 DEBUGOUT("EEPROM Read Error\n"); 621 return -E1000_ERR_EEPROM; 622 } 623 checksum += eeprom_data; 624 } 625 626 if(checksum == (uint16_t) EEPROM_SUM) 627 return E1000_SUCCESS; 628 else { 629 DEBUGOUT("EEPROM Checksum Invalid\n"); 630 return -E1000_ERR_EEPROM; 631 } 632} 633 634/****************************************************************************** 635 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 636 * second function of dual function devices 637 * 638 * hw - Struct containing variables accessed by shared code 639 *****************************************************************************/ 640static int 641e1000_read_mac_addr(struct e1000_hw *hw) 642{ 643 uint16_t offset; 644 uint16_t eeprom_data; 645 int i; 646 647 DEBUGFUNC("e1000_read_mac_addr"); 648 649 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 650 offset = i >> 1; 651 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 652 DEBUGOUT("EEPROM Read Error\n"); 653 return -E1000_ERR_EEPROM; 654 } 655 hw->mac_addr[i] = eeprom_data & 0xff; 656 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff; 657 } 658 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) && 659 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) 660 /* Invert the last bit if this is the second device */ 661 hw->mac_addr[5] ^= 1; 662 return E1000_SUCCESS; 663} 664 665/****************************************************************************** 666 * Initializes receive address filters. 667 * 668 * hw - Struct containing variables accessed by shared code 669 * 670 * Places the MAC address in receive address register 0 and clears the rest 671 * of the receive addresss registers. Clears the multicast table. Assumes 672 * the receiver is in reset when the routine is called. 673 *****************************************************************************/ 674static void 675e1000_init_rx_addrs(struct e1000_hw *hw) 676{ 677 uint32_t i; 678 uint32_t addr_low; 679 uint32_t addr_high; 680 681 DEBUGFUNC("e1000_init_rx_addrs"); 682 683 /* Setup the receive address. */ 684 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 685 addr_low = (hw->mac_addr[0] | 686 (hw->mac_addr[1] << 8) | 687 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24)); 688 689 addr_high = (hw->mac_addr[4] | 690 (hw->mac_addr[5] << 8) | E1000_RAH_AV); 691 692 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 693 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 694 695 /* Zero out the other 15 receive addresses. */ 696 DEBUGOUT("Clearing RAR[1-15]\n"); 697 for(i = 1; i < E1000_RAR_ENTRIES; i++) { 698 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 699 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 700 } 701} 702 703/****************************************************************************** 704 * Clears the VLAN filer table 705 * 706 * hw - Struct containing variables accessed by shared code 707 *****************************************************************************/ 708static void 709e1000_clear_vfta(struct e1000_hw *hw) 710{ 711 uint32_t offset; 712 713 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 714 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 715} 716 717/****************************************************************************** 718* Writes a value to one of the devices registers using port I/O (as opposed to 719* memory mapped I/O). Only 82544 and newer devices support port I/O. * 720* hw - Struct containing variables accessed by shared code 721* offset - offset to write to * value - value to write 722*****************************************************************************/ 723void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){ 724 uint32_t io_addr = hw->io_base; 725 uint32_t io_data = hw->io_base + 4; 726 e1000_io_write(hw, io_addr, offset); 727 e1000_io_write(hw, io_data, value); 728} 729 730/****************************************************************************** 731 * Set the phy type member in the hw struct. 732 * 733 * hw - Struct containing variables accessed by shared code 734 *****************************************************************************/ 735static int32_t 736e1000_set_phy_type(struct e1000_hw *hw) 737{ 738 DEBUGFUNC("e1000_set_phy_type"); 739 740 switch(hw->phy_id) { 741 case M88E1000_E_PHY_ID: 742 case M88E1000_I_PHY_ID: 743 case M88E1011_I_PHY_ID: 744 hw->phy_type = e1000_phy_m88; 745 break; 746 case IGP01E1000_I_PHY_ID: 747 hw->phy_type = e1000_phy_igp; 748 break; 749 default: 750 /* Should never have loaded on this device */ 751 hw->phy_type = e1000_phy_undefined; 752 return -E1000_ERR_PHY_TYPE; 753 } 754 755 return E1000_SUCCESS; 756} 757 758/****************************************************************************** 759 * IGP phy init script - initializes the GbE PHY 760 * 761 * hw - Struct containing variables accessed by shared code 762 *****************************************************************************/ 763static void 764e1000_phy_init_script(struct e1000_hw *hw) 765{ 766 DEBUGFUNC("e1000_phy_init_script"); 767 768#if 0 769 /* See e1000_sw_init() of the Linux driver */ 770 if(hw->phy_init_script) { 771#else 772 if((hw->mac_type == e1000_82541) || 773 (hw->mac_type == e1000_82547) || 774 (hw->mac_type == e1000_82541_rev_2) || 775 (hw->mac_type == e1000_82547_rev_2)) { 776#endif 777 mdelay(20); 778 779 e1000_write_phy_reg(hw,0x0000,0x0140); 780 781 mdelay(5); 782 783 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) { 784 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 785 786 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 787 788 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 789 790 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 791 792 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 793 794 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 795 796 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 797 798 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 799 800 e1000_write_phy_reg(hw, 0x2010, 0x0008); 801 } else { 802 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 803 } 804 805 e1000_write_phy_reg(hw, 0x0000, 0x3300); 806 807 808 if(hw->mac_type == e1000_82547) { 809 uint16_t fused, fine, coarse; 810 811 /* Move to analog registers page */ 812 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 813 814 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 815 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); 816 817 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 818 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 819 820 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 821 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 822 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 823 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 824 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 825 826 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 827 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 828 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 829 830 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); 831 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, 832 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 833 } 834 } 835 } 836} 837 838/****************************************************************************** 839 * Set the mac type member in the hw struct. 840 * 841 * hw - Struct containing variables accessed by shared code 842 *****************************************************************************/ 843static int 844e1000_set_mac_type(struct e1000_hw *hw) 845{ 846 DEBUGFUNC("e1000_set_mac_type"); 847 848 switch (hw->device_id) { 849 case E1000_DEV_ID_82542: 850 switch (hw->revision_id) { 851 case E1000_82542_2_0_REV_ID: 852 hw->mac_type = e1000_82542_rev2_0; 853 break; 854 case E1000_82542_2_1_REV_ID: 855 hw->mac_type = e1000_82542_rev2_1; 856 break; 857 default: 858 /* Invalid 82542 revision ID */ 859 return -E1000_ERR_MAC_TYPE; 860 } 861 break; 862 case E1000_DEV_ID_82543GC_FIBER: 863 case E1000_DEV_ID_82543GC_COPPER: 864 hw->mac_type = e1000_82543; 865 break; 866 case E1000_DEV_ID_82544EI_COPPER: 867 case E1000_DEV_ID_82544EI_FIBER: 868 case E1000_DEV_ID_82544GC_COPPER: 869 case E1000_DEV_ID_82544GC_LOM: 870 hw->mac_type = e1000_82544; 871 break; 872 case E1000_DEV_ID_82540EM: 873 case E1000_DEV_ID_82540EM_LOM: 874 case E1000_DEV_ID_82540EP: 875 case E1000_DEV_ID_82540EP_LOM: 876 case E1000_DEV_ID_82540EP_LP: 877 hw->mac_type = e1000_82540; 878 break; 879 case E1000_DEV_ID_82545EM_COPPER: 880 case E1000_DEV_ID_82545EM_FIBER: 881 hw->mac_type = e1000_82545; 882 break; 883 case E1000_DEV_ID_82545GM_COPPER: 884 case E1000_DEV_ID_82545GM_FIBER: 885 case E1000_DEV_ID_82545GM_SERDES: 886 hw->mac_type = e1000_82545_rev_3; 887 break; 888 case E1000_DEV_ID_82546EB_COPPER: 889 case E1000_DEV_ID_82546EB_FIBER: 890 case E1000_DEV_ID_82546EB_QUAD_COPPER: 891 hw->mac_type = e1000_82546; 892 break; 893 case E1000_DEV_ID_82546GB_COPPER: 894 case E1000_DEV_ID_82546GB_FIBER: 895 case E1000_DEV_ID_82546GB_SERDES: 896 hw->mac_type = e1000_82546_rev_3; 897 break; 898 case E1000_DEV_ID_82541EI: 899 case E1000_DEV_ID_82541EI_MOBILE: 900 hw->mac_type = e1000_82541; 901 break; 902 case E1000_DEV_ID_82541ER: 903 case E1000_DEV_ID_82541GI: 904 case E1000_DEV_ID_82541GI_MOBILE: 905 hw->mac_type = e1000_82541_rev_2; 906 break; 907 case E1000_DEV_ID_82547EI: 908 hw->mac_type = e1000_82547; 909 break; 910 case E1000_DEV_ID_82547GI: 911 hw->mac_type = e1000_82547_rev_2; 912 break; 913 default: 914 /* Should never have loaded on this device */ 915 return -E1000_ERR_MAC_TYPE; 916 } 917 918 return E1000_SUCCESS; 919} 920 921/***************************************************************************** 922 * Set media type and TBI compatibility. 923 * 924 * hw - Struct containing variables accessed by shared code 925 * **************************************************************************/ 926static void 927e1000_set_media_type(struct e1000_hw *hw) 928{ 929 uint32_t status; 930 931 DEBUGFUNC("e1000_set_media_type"); 932 933 if(hw->mac_type != e1000_82543) { 934 /* tbi_compatibility is only valid on 82543 */ 935 hw->tbi_compatibility_en = FALSE; 936 } 937 938 switch (hw->device_id) { 939 case E1000_DEV_ID_82545GM_SERDES: 940 case E1000_DEV_ID_82546GB_SERDES: 941 hw->media_type = e1000_media_type_internal_serdes; 942 break; 943 default: 944 if(hw->mac_type >= e1000_82543) { 945 status = E1000_READ_REG(hw, STATUS); 946 if(status & E1000_STATUS_TBIMODE) { 947 hw->media_type = e1000_media_type_fiber; 948 /* tbi_compatibility not valid on fiber */ 949 hw->tbi_compatibility_en = FALSE; 950 } else { 951 hw->media_type = e1000_media_type_copper; 952 } 953 } else { 954 /* This is an 82542 (fiber only) */ 955 hw->media_type = e1000_media_type_fiber; 956 } 957 } 958} 959 960/****************************************************************************** 961 * Reset the transmit and receive units; mask and clear all interrupts. 962 * 963 * hw - Struct containing variables accessed by shared code 964 *****************************************************************************/ 965static void 966e1000_reset_hw(struct e1000_hw *hw) 967{ 968 uint32_t ctrl; 969 uint32_t ctrl_ext; 970 uint32_t icr; 971 uint32_t manc; 972 973 DEBUGFUNC("e1000_reset_hw"); 974 975 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 976 if(hw->mac_type == e1000_82542_rev2_0) { 977 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 978 e1000_pci_clear_mwi(hw); 979 } 980 981 /* Clear interrupt mask to stop board from generating interrupts */ 982 DEBUGOUT("Masking off all interrupts\n"); 983 E1000_WRITE_REG(hw, IMC, 0xffffffff); 984 985 /* Disable the Transmit and Receive units. Then delay to allow 986 * any pending transactions to complete before we hit the MAC with 987 * the global reset. 988 */ 989 E1000_WRITE_REG(hw, RCTL, 0); 990 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 991 E1000_WRITE_FLUSH(hw); 992 993 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 994 hw->tbi_compatibility_on = FALSE; 995 996 /* Delay to allow any outstanding PCI transactions to complete before 997 * resetting the device 998 */ 999 mdelay(10); 1000 1001 ctrl = E1000_READ_REG(hw, CTRL); 1002 1003 /* Must reset the PHY before resetting the MAC */ 1004 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1005 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 1006 mdelay(5); 1007 } 1008 1009 /* Issue a global reset to the MAC. This will reset the chip's 1010 * transmit, receive, DMA, and link units. It will not effect 1011 * the current PCI configuration. The global reset bit is self- 1012 * clearing, and should clear within a microsecond. 1013 */ 1014 DEBUGOUT("Issuing a global reset to MAC\n"); 1015 1016 switch(hw->mac_type) { 1017 case e1000_82544: 1018 case e1000_82540: 1019 case e1000_82545: 1020 case e1000_82546: 1021 case e1000_82541: 1022 case e1000_82541_rev_2: 1023 /* These controllers can't ack the 64-bit write when issuing the 1024 * reset, so use IO-mapping as a workaround to issue the reset */ 1025 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1026 break; 1027 case e1000_82545_rev_3: 1028 case e1000_82546_rev_3: 1029 /* Reset is performed on a shadow of the control register */ 1030 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 1031 break; 1032 default: 1033 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1034 break; 1035 } 1036 1037 /* After MAC reset, force reload of EEPROM to restore power-on settings to 1038 * device. Later controllers reload the EEPROM automatically, so just wait 1039 * for reload to complete. 1040 */ 1041 switch(hw->mac_type) { 1042 case e1000_82542_rev2_0: 1043 case e1000_82542_rev2_1: 1044 case e1000_82543: 1045 case e1000_82544: 1046 /* Wait for reset to complete */ 1047 udelay(10); 1048 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1049 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1050 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1051 E1000_WRITE_FLUSH(hw); 1052 /* Wait for EEPROM reload */ 1053 mdelay(2); 1054 break; 1055 case e1000_82541: 1056 case e1000_82541_rev_2: 1057 case e1000_82547: 1058 case e1000_82547_rev_2: 1059 /* Wait for EEPROM reload */ 1060 mdelay(20); 1061 break; 1062 default: 1063 /* Wait for EEPROM reload (it happens automatically) */ 1064 mdelay(5); 1065 break; 1066 } 1067 1068 /* Disable HW ARPs on ASF enabled adapters */ 1069 if(hw->mac_type >= e1000_82540) { 1070 manc = E1000_READ_REG(hw, MANC); 1071 manc &= ~(E1000_MANC_ARP_EN); 1072 E1000_WRITE_REG(hw, MANC, manc); 1073 } 1074 1075 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1076 e1000_phy_init_script(hw); 1077 } 1078 1079 /* Clear interrupt mask to stop board from generating interrupts */ 1080 DEBUGOUT("Masking off all interrupts\n"); 1081 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1082 1083 /* Clear any pending interrupt events. */ 1084 icr = E1000_READ_REG(hw, ICR); 1085 1086 /* If MWI was previously enabled, reenable it. */ 1087 if(hw->mac_type == e1000_82542_rev2_0) { 1088#ifdef LINUX_DRIVER 1089 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1090#endif 1091 e1000_pci_set_mwi(hw); 1092 } 1093} 1094 1095/****************************************************************************** 1096 * Performs basic configuration of the adapter. 1097 * 1098 * hw - Struct containing variables accessed by shared code 1099 * 1100 * Assumes that the controller has previously been reset and is in a 1101 * post-reset uninitialized state. Initializes the receive address registers, 1102 * multicast table, and VLAN filter table. Calls routines to setup link 1103 * configuration and flow control settings. Clears all on-chip counters. Leaves 1104 * the transmit and receive units disabled and uninitialized. 1105 *****************************************************************************/ 1106static int 1107e1000_init_hw(struct e1000_hw *hw) 1108{ 1109 uint32_t ctrl, status; 1110 uint32_t i; 1111 int32_t ret_val; 1112 uint16_t pcix_cmd_word; 1113 uint16_t pcix_stat_hi_word; 1114 uint16_t cmd_mmrbc; 1115 uint16_t stat_mmrbc; 1116 e1000_bus_type bus_type = e1000_bus_type_unknown; 1117 1118 DEBUGFUNC("e1000_init_hw"); 1119 1120 /* Set the media type and TBI compatibility */ 1121 e1000_set_media_type(hw); 1122 1123 /* Disabling VLAN filtering. */ 1124 DEBUGOUT("Initializing the IEEE VLAN\n"); 1125 E1000_WRITE_REG(hw, VET, 0); 1126 1127 e1000_clear_vfta(hw); 1128 1129 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1130 if(hw->mac_type == e1000_82542_rev2_0) { 1131 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1132 e1000_pci_clear_mwi(hw); 1133 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1134 E1000_WRITE_FLUSH(hw); 1135 mdelay(5); 1136 } 1137 1138 /* Setup the receive address. This involves initializing all of the Receive 1139 * Address Registers (RARs 0 - 15). 1140 */ 1141 e1000_init_rx_addrs(hw); 1142 1143 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1144 if(hw->mac_type == e1000_82542_rev2_0) { 1145 E1000_WRITE_REG(hw, RCTL, 0); 1146 E1000_WRITE_FLUSH(hw); 1147 mdelay(1); 1148#ifdef LINUX_DRIVER 1149 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1150#endif 1151 e1000_pci_set_mwi(hw); 1152 } 1153 1154 /* Zero out the Multicast HASH table */ 1155 DEBUGOUT("Zeroing the MTA\n"); 1156 for(i = 0; i < E1000_MC_TBL_SIZE; i++) 1157 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1158 1159#if 0 1160 /* Set the PCI priority bit correctly in the CTRL register. This 1161 * determines if the adapter gives priority to receives, or if it 1162 * gives equal priority to transmits and receives. 1163 */ 1164 if(hw->dma_fairness) { 1165 ctrl = E1000_READ_REG(hw, CTRL); 1166 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1167 } 1168#endif 1169 1170 switch(hw->mac_type) { 1171 case e1000_82545_rev_3: 1172 case e1000_82546_rev_3: 1173 break; 1174 default: 1175 if (hw->mac_type >= e1000_82543) { 1176 /* See e1000_get_bus_info() of the Linux driver */ 1177 status = E1000_READ_REG(hw, STATUS); 1178 bus_type = (status & E1000_STATUS_PCIX_MODE) ? 1179 e1000_bus_type_pcix : e1000_bus_type_pci; 1180 } 1181 1182 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1183 if(bus_type == e1000_bus_type_pcix) { 1184 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 1185 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 1186 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1187 PCIX_COMMAND_MMRBC_SHIFT; 1188 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1189 PCIX_STATUS_HI_MMRBC_SHIFT; 1190 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1191 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1192 if(cmd_mmrbc > stat_mmrbc) { 1193 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1194 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1195 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word); 1196 } 1197 } 1198 break; 1199 } 1200 1201 /* Call a subroutine to configure the link and setup flow control. */ 1202 ret_val = e1000_setup_link(hw); 1203 1204 /* Set the transmit descriptor write-back policy */ 1205 if(hw->mac_type > e1000_82544) { 1206 ctrl = E1000_READ_REG(hw, TXDCTL); 1207 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1208 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1209 } 1210 1211#if 0 1212 /* Clear all of the statistics registers (clear on read). It is 1213 * important that we do this after we have tried to establish link 1214 * because the symbol error count will increment wildly if there 1215 * is no link. 1216 */ 1217 e1000_clear_hw_cntrs(hw); 1218#endif 1219 1220 return ret_val; 1221} 1222 1223/****************************************************************************** 1224 * Adjust SERDES output amplitude based on EEPROM setting. 1225 * 1226 * hw - Struct containing variables accessed by shared code. 1227 *****************************************************************************/ 1228static int32_t 1229e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 1230{ 1231 uint16_t eeprom_data; 1232 int32_t ret_val; 1233 1234 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 1235 1236 if(hw->media_type != e1000_media_type_internal_serdes) 1237 return E1000_SUCCESS; 1238 1239 switch(hw->mac_type) { 1240 case e1000_82545_rev_3: 1241 case e1000_82546_rev_3: 1242 break; 1243 default: 1244 return E1000_SUCCESS; 1245 } 1246 1247 if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, 1248 &eeprom_data))) { 1249 return ret_val; 1250 } 1251 1252 if(eeprom_data != EEPROM_RESERVED_WORD) { 1253 /* Adjust SERDES output amplitude only. */ 1254 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1255 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1256 eeprom_data))) 1257 return ret_val; 1258 } 1259 1260 return E1000_SUCCESS; 1261} 1262 1263/****************************************************************************** 1264 * Configures flow control and link settings. 1265 * 1266 * hw - Struct containing variables accessed by shared code 1267 * 1268 * Determines which flow control settings to use. Calls the apropriate media- 1269 * specific link configuration function. Configures the flow control settings. 1270 * Assuming the adapter has a valid link partner, a valid link should be 1271 * established. Assumes the hardware has previously been reset and the 1272 * transmitter and receiver are not enabled. 1273 *****************************************************************************/ 1274static int 1275e1000_setup_link(struct e1000_hw *hw) 1276{ 1277 uint32_t ctrl_ext; 1278 int32_t ret_val; 1279 uint16_t eeprom_data; 1280 1281 DEBUGFUNC("e1000_setup_link"); 1282 1283 /* Read and store word 0x0F of the EEPROM. This word contains bits 1284 * that determine the hardware's default PAUSE (flow control) mode, 1285 * a bit that determines whether the HW defaults to enabling or 1286 * disabling auto-negotiation, and the direction of the 1287 * SW defined pins. If there is no SW over-ride of the flow 1288 * control setting, then the variable hw->fc will 1289 * be initialized based on a value in the EEPROM. 1290 */ 1291 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { 1292 DEBUGOUT("EEPROM Read Error\n"); 1293 return -E1000_ERR_EEPROM; 1294 } 1295 1296 if(hw->fc == e1000_fc_default) { 1297 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1298 hw->fc = e1000_fc_none; 1299 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1300 EEPROM_WORD0F_ASM_DIR) 1301 hw->fc = e1000_fc_tx_pause; 1302 else 1303 hw->fc = e1000_fc_full; 1304 } 1305 1306 /* We want to save off the original Flow Control configuration just 1307 * in case we get disconnected and then reconnected into a different 1308 * hub or switch with different Flow Control capabilities. 1309 */ 1310 if(hw->mac_type == e1000_82542_rev2_0) 1311 hw->fc &= (~e1000_fc_tx_pause); 1312 1313#if 0 1314 /* See e1000_sw_init() of the Linux driver */ 1315 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1316#else 1317 if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543)) 1318#endif 1319 hw->fc &= (~e1000_fc_rx_pause); 1320 1321#if 0 1322 hw->original_fc = hw->fc; 1323#endif 1324 1325 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1326 1327 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1328 * polarity value for the SW controlled pins, and setup the 1329 * Extended Device Control reg with that info. 1330 * This is needed because one of the SW controlled pins is used for 1331 * signal detection. So this should be done before e1000_setup_pcs_link() 1332 * or e1000_phy_setup() is called. 1333 */ 1334 if(hw->mac_type == e1000_82543) { 1335 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1336 SWDPIO__EXT_SHIFT); 1337 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1338 } 1339 1340 /* Call the necessary subroutine to configure the link. */ 1341 ret_val = (hw->media_type == e1000_media_type_copper) ? 1342 e1000_setup_copper_link(hw) : 1343 e1000_setup_fiber_serdes_link(hw); 1344 if (ret_val < 0) { 1345 return ret_val; 1346 } 1347 1348 /* Initialize the flow control address, type, and PAUSE timer 1349 * registers to their default values. This is done even if flow 1350 * control is disabled, because it does not hurt anything to 1351 * initialize these registers. 1352 */ 1353 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1354 1355 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1356 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1357 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1358#if 0 1359 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1360#else 1361 E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER); 1362#endif 1363 1364 /* Set the flow control receive threshold registers. Normally, 1365 * these registers will be set to a default threshold that may be 1366 * adjusted later by the driver's runtime code. However, if the 1367 * ability to transmit pause frames in not enabled, then these 1368 * registers will be set to 0. 1369 */ 1370 if(!(hw->fc & e1000_fc_tx_pause)) { 1371 E1000_WRITE_REG(hw, FCRTL, 0); 1372 E1000_WRITE_REG(hw, FCRTH, 0); 1373 } else { 1374 /* We need to set up the Receive Threshold high and low water marks 1375 * as well as (optionally) enabling the transmission of XON frames. 1376 */ 1377#if 0 1378 if(hw->fc_send_xon) { 1379 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1380 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1381 } else { 1382 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1383 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1384 } 1385#else 1386 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE)); 1387 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH); 1388#endif 1389 } 1390 return ret_val; 1391} 1392 1393/****************************************************************************** 1394 * Sets up link for a fiber based or serdes based adapter 1395 * 1396 * hw - Struct containing variables accessed by shared code 1397 * 1398 * Manipulates Physical Coding Sublayer functions in order to configure 1399 * link. Assumes the hardware has been previously reset and the transmitter 1400 * and receiver are not enabled. 1401 *****************************************************************************/ 1402static int 1403e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 1404{ 1405 uint32_t ctrl; 1406 uint32_t status; 1407 uint32_t txcw = 0; 1408 uint32_t i; 1409 uint32_t signal = 0; 1410 int32_t ret_val; 1411 1412 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 1413 1414 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 1415 * set when the optics detect a signal. On older adapters, it will be 1416 * cleared when there is a signal. This applies to fiber media only. 1417 * If we're on serdes media, adjust the output amplitude to value set in 1418 * the EEPROM. 1419 */ 1420 ctrl = E1000_READ_REG(hw, CTRL); 1421 if(hw->media_type == e1000_media_type_fiber) 1422 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1423 1424 if((ret_val = e1000_adjust_serdes_amplitude(hw))) 1425 return ret_val; 1426 1427 /* Take the link out of reset */ 1428 ctrl &= ~(E1000_CTRL_LRST); 1429 1430#if 0 1431 /* Adjust VCO speed to improve BER performance */ 1432 if((ret_val = e1000_set_vco_speed(hw))) 1433 return ret_val; 1434#endif 1435 1436 e1000_config_collision_dist(hw); 1437 1438 /* Check for a software override of the flow control settings, and setup 1439 * the device accordingly. If auto-negotiation is enabled, then software 1440 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1441 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1442 * auto-negotiation is disabled, then software will have to manually 1443 * configure the two flow control enable bits in the CTRL register. 1444 * 1445 * The possible values of the "fc" parameter are: 1446 * 0: Flow control is completely disabled 1447 * 1: Rx flow control is enabled (we can receive pause frames, but 1448 * not send pause frames). 1449 * 2: Tx flow control is enabled (we can send pause frames but we do 1450 * not support receiving pause frames). 1451 * 3: Both Rx and TX flow control (symmetric) are enabled. 1452 */ 1453 switch (hw->fc) { 1454 case e1000_fc_none: 1455 /* Flow control is completely disabled by a software over-ride. */ 1456 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1457 break; 1458 case e1000_fc_rx_pause: 1459 /* RX Flow control is enabled and TX Flow control is disabled by a 1460 * software over-ride. Since there really isn't a way to advertise 1461 * that we are capable of RX Pause ONLY, we will advertise that we 1462 * support both symmetric and asymmetric RX PAUSE. Later, we will 1463 * disable the adapter's ability to send PAUSE frames. 1464 */ 1465 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1466 break; 1467 case e1000_fc_tx_pause: 1468 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1469 * software over-ride. 1470 */ 1471 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1472 break; 1473 case e1000_fc_full: 1474 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1475 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1476 break; 1477 default: 1478 DEBUGOUT("Flow control param set incorrectly\n"); 1479 return -E1000_ERR_CONFIG; 1480 break; 1481 } 1482 1483 /* Since auto-negotiation is enabled, take the link out of reset (the link 1484 * will be in reset, because we previously reset the chip). This will 1485 * restart auto-negotiation. If auto-neogtiation is successful then the 1486 * link-up status bit will be set and the flow control enable bits (RFCE 1487 * and TFCE) will be set according to their negotiated value. 1488 */ 1489 DEBUGOUT("Auto-negotiation enabled\n"); 1490 1491 E1000_WRITE_REG(hw, TXCW, txcw); 1492 E1000_WRITE_REG(hw, CTRL, ctrl); 1493 E1000_WRITE_FLUSH(hw); 1494 1495 hw->txcw = txcw; 1496 mdelay(1); 1497 1498 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1499 * indication in the Device Status Register. Time-out if a link isn't 1500 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1501 * less than 500 milliseconds even if the other end is doing it in SW). 1502 * For internal serdes, we just assume a signal is present, then poll. 1503 */ 1504 if(hw->media_type == e1000_media_type_internal_serdes || 1505 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1506 DEBUGOUT("Looking for Link\n"); 1507 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1508 mdelay(10); 1509 status = E1000_READ_REG(hw, STATUS); 1510 if(status & E1000_STATUS_LU) break; 1511 } 1512 if(i == (LINK_UP_TIMEOUT / 10)) { 1513 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1514 hw->autoneg_failed = 1; 1515 /* AutoNeg failed to achieve a link, so we'll call 1516 * e1000_check_for_link. This routine will force the link up if 1517 * we detect a signal. This will allow us to communicate with 1518 * non-autonegotiating link partners. 1519 */ 1520 if((ret_val = e1000_check_for_link(hw))) { 1521 DEBUGOUT("Error while checking for link\n"); 1522 return ret_val; 1523 } 1524 hw->autoneg_failed = 0; 1525 } else { 1526 hw->autoneg_failed = 0; 1527 DEBUGOUT("Valid Link Found\n"); 1528 } 1529 } else { 1530 DEBUGOUT("No Signal Detected\n"); 1531 } 1532 return E1000_SUCCESS; 1533} 1534 1535/****************************************************************************** 1536* Detects which PHY is present and the speed and duplex 1537* 1538* hw - Struct containing variables accessed by shared code 1539******************************************************************************/ 1540static int 1541e1000_setup_copper_link(struct e1000_hw *hw) 1542{ 1543 uint32_t ctrl; 1544 int32_t ret_val; 1545 uint16_t i; 1546 uint16_t phy_data; 1547 1548 DEBUGFUNC("e1000_setup_copper_link"); 1549 1550 ctrl = E1000_READ_REG(hw, CTRL); 1551 /* With 82543, we need to force speed and duplex on the MAC equal to what 1552 * the PHY speed and duplex configuration is. In addition, we need to 1553 * perform a hardware reset on the PHY to take it out of reset. 1554 */ 1555 if(hw->mac_type > e1000_82543) { 1556 ctrl |= E1000_CTRL_SLU; 1557 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1558 E1000_WRITE_REG(hw, CTRL, ctrl); 1559 } else { 1560 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1561 E1000_WRITE_REG(hw, CTRL, ctrl); 1562 e1000_phy_hw_reset(hw); 1563 } 1564 1565 /* Make sure we have a valid PHY */ 1566 if((ret_val = e1000_detect_gig_phy(hw))) { 1567 DEBUGOUT("Error, did not detect valid phy.\n"); 1568 return ret_val; 1569 } 1570 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1571 1572 if(hw->mac_type <= e1000_82543 || 1573 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1574#if 0 1575 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1576 hw->phy_reset_disable = FALSE; 1577 1578 if(!hw->phy_reset_disable) { 1579#else 1580 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 1581#endif 1582 if (hw->phy_type == e1000_phy_igp) { 1583 1584 if((ret_val = e1000_phy_reset(hw))) { 1585 DEBUGOUT("Error Resetting the PHY\n"); 1586 return ret_val; 1587 } 1588 1589 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1590 mdelay(15); 1591 1592#if 0 1593 /* disable lplu d3 during driver init */ 1594 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) { 1595 DEBUGOUT("Error Disabling LPLU D3\n"); 1596 return ret_val; 1597 } 1598 1599 /* Configure mdi-mdix settings */ 1600 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 1601 &phy_data))) 1602 return ret_val; 1603 1604 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1605 hw->dsp_config_state = e1000_dsp_config_disabled; 1606 /* Force MDI for IGP B-0 PHY */ 1607 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1608 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1609 hw->mdix = 1; 1610 1611 } else { 1612 hw->dsp_config_state = e1000_dsp_config_enabled; 1613 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1614 1615 switch (hw->mdix) { 1616 case 1: 1617 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1618 break; 1619 case 2: 1620 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1621 break; 1622 case 0: 1623 default: 1624 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1625 break; 1626 } 1627 } 1628 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 1629 phy_data))) 1630 return ret_val; 1631 1632 /* set auto-master slave resolution settings */ 1633 e1000_ms_type phy_ms_setting = hw->master_slave; 1634 1635 if(hw->ffe_config_state == e1000_ffe_config_active) 1636 hw->ffe_config_state = e1000_ffe_config_enabled; 1637 1638 if(hw->dsp_config_state == e1000_dsp_config_activated) 1639 hw->dsp_config_state = e1000_dsp_config_enabled; 1640#endif 1641 1642 /* when autonegotiation advertisment is only 1000Mbps then we 1643 * should disable SmartSpeed and enable Auto MasterSlave 1644 * resolution as hardware default. */ 1645 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1646 /* Disable SmartSpeed */ 1647 if((ret_val = e1000_read_phy_reg(hw, 1648 IGP01E1000_PHY_PORT_CONFIG, 1649 &phy_data))) 1650 return ret_val; 1651 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1652 if((ret_val = e1000_write_phy_reg(hw, 1653 IGP01E1000_PHY_PORT_CONFIG, 1654 phy_data))) 1655 return ret_val; 1656 /* Set auto Master/Slave resolution process */ 1657 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 1658 &phy_data))) 1659 return ret_val; 1660 phy_data &= ~CR_1000T_MS_ENABLE; 1661 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 1662 phy_data))) 1663 return ret_val; 1664 } 1665 1666 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 1667 &phy_data))) 1668 return ret_val; 1669 1670#if 0 1671 /* load defaults for future use */ 1672 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1673 ((phy_data & CR_1000T_MS_VALUE) ? 1674 e1000_ms_force_master : 1675 e1000_ms_force_slave) : 1676 e1000_ms_auto; 1677 1678 switch (phy_ms_setting) { 1679 case e1000_ms_force_master: 1680 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1681 break; 1682 case e1000_ms_force_slave: 1683 phy_data |= CR_1000T_MS_ENABLE; 1684 phy_data &= ~(CR_1000T_MS_VALUE); 1685 break; 1686 case e1000_ms_auto: 1687 phy_data &= ~CR_1000T_MS_ENABLE; 1688 default: 1689 break; 1690 } 1691#endif 1692 1693 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 1694 phy_data))) 1695 return ret_val; 1696 } else { 1697 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1698 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1699 &phy_data))) 1700 return ret_val; 1701 1702 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1703 1704 /* Options: 1705 * MDI/MDI-X = 0 (default) 1706 * 0 - Auto for all speeds 1707 * 1 - MDI mode 1708 * 2 - MDI-X mode 1709 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1710 */ 1711#if 0 1712 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1713 1714 switch (hw->mdix) { 1715 case 1: 1716 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1717 break; 1718 case 2: 1719 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1720 break; 1721 case 3: 1722 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1723 break; 1724 case 0: 1725 default: 1726#endif 1727 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1728#if 0 1729 break; 1730 } 1731#endif 1732 1733 /* Options: 1734 * disable_polarity_correction = 0 (default) 1735 * Automatic Correction for Reversed Cable Polarity 1736 * 0 - Disabled 1737 * 1 - Enabled 1738 */ 1739 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1740 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1741 phy_data))) 1742 return ret_val; 1743 1744 /* Force TX_CLK in the Extended PHY Specific Control Register 1745 * to 25MHz clock. 1746 */ 1747 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1748 &phy_data))) 1749 return ret_val; 1750 1751 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1752 1753#ifdef LINUX_DRIVER 1754 if (hw->phy_revision < M88E1011_I_REV_4) { 1755#endif 1756 /* Configure Master and Slave downshift values */ 1757 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1758 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1759 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1760 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1761 if((ret_val = e1000_write_phy_reg(hw, 1762 M88E1000_EXT_PHY_SPEC_CTRL, 1763 phy_data))) 1764 return ret_val; 1765 } 1766 1767 /* SW Reset the PHY so all changes take effect */ 1768 if((ret_val = e1000_phy_reset(hw))) { 1769 DEBUGOUT("Error Resetting the PHY\n"); 1770 return ret_val; 1771#ifdef LINUX_DRIVER 1772 } 1773#endif 1774 } 1775 1776 /* Options: 1777 * autoneg = 1 (default) 1778 * PHY will advertise value(s) parsed from 1779 * autoneg_advertised and fc 1780 * autoneg = 0 1781 * PHY will be set to 10H, 10F, 100H, or 100F 1782 * depending on value parsed from forced_speed_duplex. 1783 */ 1784 1785 /* Is autoneg enabled? This is enabled by default or by software 1786 * override. If so, call e1000_phy_setup_autoneg routine to parse the 1787 * autoneg_advertised and fc options. If autoneg is NOT enabled, then 1788 * the user should have provided a speed/duplex override. If so, then 1789 * call e1000_phy_force_speed_duplex to parse and set this up. 1790 */ 1791 /* Perform some bounds checking on the hw->autoneg_advertised 1792 * parameter. If this variable is zero, then set it to the default. 1793 */ 1794 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1795 1796 /* If autoneg_advertised is zero, we assume it was not defaulted 1797 * by the calling code so we set to advertise full capability. 1798 */ 1799 if(hw->autoneg_advertised == 0) 1800 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1801 1802 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1803 if((ret_val = e1000_phy_setup_autoneg(hw))) { 1804 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1805 return ret_val; 1806 } 1807 DEBUGOUT("Restarting Auto-Neg\n"); 1808 1809 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1810 * the Auto Neg Restart bit in the PHY control register. 1811 */ 1812 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data))) 1813 return ret_val; 1814 1815 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1816 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data))) 1817 return ret_val; 1818 1819#if 0 1820 /* Does the user want to wait for Auto-Neg to complete here, or 1821 * check at a later time (for example, callback routine). 1822 */ 1823 if(hw->wait_autoneg_complete) { 1824 if((ret_val = e1000_wait_autoneg(hw))) { 1825 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1826 return ret_val; 1827 } 1828 } 1829#else 1830 /* If we do not wait for autonegotiation to complete I 1831 * do not see a valid link status. 1832 */ 1833 if((ret_val = e1000_wait_autoneg(hw))) { 1834 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1835 return ret_val; 1836 } 1837#endif 1838 } /* !hw->phy_reset_disable */ 1839 1840 /* Check link status. Wait up to 100 microseconds for link to become 1841 * valid. 1842 */ 1843 for(i = 0; i < 10; i++) { 1844 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data))) 1845 return ret_val; 1846 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data))) 1847 return ret_val; 1848 1849 if(phy_data & MII_SR_LINK_STATUS) { 1850 /* We have link, so we need to finish the config process: 1851 * 1) Set up the MAC to the current PHY speed/duplex 1852 * if we are on 82543. If we 1853 * are on newer silicon, we only need to configure 1854 * collision distance in the Transmit Control Register. 1855 * 2) Set up flow control on the MAC to that established with 1856 * the link partner. 1857 */ 1858 if(hw->mac_type >= e1000_82544) { 1859 e1000_config_collision_dist(hw); 1860 } else { 1861 if((ret_val = e1000_config_mac_to_phy(hw))) { 1862 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1863 return ret_val; 1864 } 1865 } 1866 if((ret_val = e1000_config_fc_after_link_up(hw))) { 1867 DEBUGOUT("Error Configuring Flow Control\n"); 1868 return ret_val; 1869 } 1870#if 0 1871 if(hw->phy_type == e1000_phy_igp) { 1872 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) { 1873 DEBUGOUT("Error Configuring DSP after link up\n"); 1874 return ret_val; 1875 } 1876 } 1877#endif 1878 DEBUGOUT("Valid link established!!!\n"); 1879 return E1000_SUCCESS; 1880 } 1881 udelay(10); 1882 } 1883 1884 DEBUGOUT("Unable to establish link!!!\n"); 1885 return -E1000_ERR_NOLINK; 1886} 1887 1888/****************************************************************************** 1889* Configures PHY autoneg and flow control advertisement settings 1890* 1891* hw - Struct containing variables accessed by shared code 1892******************************************************************************/ 1893static int 1894e1000_phy_setup_autoneg(struct e1000_hw *hw) 1895{ 1896 int32_t ret_val; 1897 uint16_t mii_autoneg_adv_reg; 1898 uint16_t mii_1000t_ctrl_reg; 1899 1900 DEBUGFUNC("e1000_phy_setup_autoneg"); 1901 1902 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1903 if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 1904 &mii_autoneg_adv_reg))) 1905 return ret_val; 1906 1907 /* Read the MII 1000Base-T Control Register (Address 9). */ 1908 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg))) 1909 return ret_val; 1910 1911 /* Need to parse both autoneg_advertised and fc and set up 1912 * the appropriate PHY registers. First we will parse for 1913 * autoneg_advertised software override. Since we can advertise 1914 * a plethora of combinations, we need to check each bit 1915 * individually. 1916 */ 1917 1918 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1919 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1920 * the 1000Base-T Control Register (Address 9). 1921 */ 1922 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1923 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1924 1925 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 1926 1927 /* Do we want to advertise 10 Mb Half Duplex? */ 1928 if(hw->autoneg_advertised & ADVERTISE_10_HALF) { 1929 DEBUGOUT("Advertise 10mb Half duplex\n"); 1930 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1931 } 1932 1933 /* Do we want to advertise 10 Mb Full Duplex? */ 1934 if(hw->autoneg_advertised & ADVERTISE_10_FULL) { 1935 DEBUGOUT("Advertise 10mb Full duplex\n"); 1936 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1937 } 1938 1939 /* Do we want to advertise 100 Mb Half Duplex? */ 1940 if(hw->autoneg_advertised & ADVERTISE_100_HALF) { 1941 DEBUGOUT("Advertise 100mb Half duplex\n"); 1942 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1943 } 1944 1945 /* Do we want to advertise 100 Mb Full Duplex? */ 1946 if(hw->autoneg_advertised & ADVERTISE_100_FULL) { 1947 DEBUGOUT("Advertise 100mb Full duplex\n"); 1948 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1949 } 1950 1951 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1952 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1953 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 1954 } 1955 1956 /* Do we want to advertise 1000 Mb Full Duplex? */ 1957 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1958 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1959 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1960 } 1961 1962 /* Check for a software override of the flow control settings, and 1963 * setup the PHY advertisement registers accordingly. If 1964 * auto-negotiation is enabled, then software will have to set the 1965 * "PAUSE" bits to the correct value in the Auto-Negotiation 1966 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1967 * 1968 * The possible values of the "fc" parameter are: 1969 * 0: Flow control is completely disabled 1970 * 1: Rx flow control is enabled (we can receive pause frames 1971 * but not send pause frames). 1972 * 2: Tx flow control is enabled (we can send pause frames 1973 * but we do not support receiving pause frames). 1974 * 3: Both Rx and TX flow control (symmetric) are enabled. 1975 * other: No software override. The flow control configuration 1976 * in the EEPROM is used. 1977 */ 1978 switch (hw->fc) { 1979 case e1000_fc_none: /* 0 */ 1980 /* Flow control (RX & TX) is completely disabled by a 1981 * software over-ride. 1982 */ 1983 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1984 break; 1985 case e1000_fc_rx_pause: /* 1 */ 1986 /* RX Flow control is enabled, and TX Flow control is 1987 * disabled, by a software over-ride. 1988 */ 1989 /* Since there really isn't a way to advertise that we are 1990 * capable of RX Pause ONLY, we will advertise that we 1991 * support both symmetric and asymmetric RX PAUSE. Later 1992 * (in e1000_config_fc_after_link_up) we will disable the 1993 *hw's ability to send PAUSE frames. 1994 */ 1995 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1996 break; 1997 case e1000_fc_tx_pause: /* 2 */ 1998 /* TX Flow control is enabled, and RX Flow control is 1999 * disabled, by a software over-ride. 2000 */ 2001 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2002 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2003 break; 2004 case e1000_fc_full: /* 3 */ 2005 /* Flow control (both RX and TX) is enabled by a software 2006 * over-ride. 2007 */ 2008 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2009 break; 2010 default: 2011 DEBUGOUT("Flow control param set incorrectly\n"); 2012 return -E1000_ERR_CONFIG; 2013 } 2014 2015 if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, 2016 mii_autoneg_adv_reg))) 2017 return ret_val; 2018 2019 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2020 2021 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg))) 2022 return ret_val; 2023 2024 return E1000_SUCCESS; 2025} 2026 2027/****************************************************************************** 2028* Sets the collision distance in the Transmit Control register 2029* 2030* hw - Struct containing variables accessed by shared code 2031* 2032* Link should have been established previously. Reads the speed and duplex 2033* information from the Device Status register. 2034******************************************************************************/ 2035static void 2036e1000_config_collision_dist(struct e1000_hw *hw) 2037{ 2038 uint32_t tctl; 2039 2040 tctl = E1000_READ_REG(hw, TCTL); 2041 2042 tctl &= ~E1000_TCTL_COLD; 2043 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2044 2045 E1000_WRITE_REG(hw, TCTL, tctl); 2046 E1000_WRITE_FLUSH(hw); 2047} 2048 2049/****************************************************************************** 2050* Sets MAC speed and duplex settings to reflect the those in the PHY 2051* 2052* hw - Struct containing variables accessed by shared code 2053* mii_reg - data to write to the MII control register 2054* 2055* The contents of the PHY register containing the needed information need to 2056* be passed in. 2057******************************************************************************/ 2058static int 2059e1000_config_mac_to_phy(struct e1000_hw *hw) 2060{ 2061 uint32_t ctrl; 2062 int32_t ret_val; 2063 uint16_t phy_data; 2064 2065 DEBUGFUNC("e1000_config_mac_to_phy"); 2066 2067 /* Read the Device Control Register and set the bits to Force Speed 2068 * and Duplex. 2069 */ 2070 ctrl = E1000_READ_REG(hw, CTRL); 2071 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2072 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 2073 2074 /* Set up duplex in the Device Control and Transmit Control 2075 * registers depending on negotiated values. 2076 */ 2077 if (hw->phy_type == e1000_phy_igp) { 2078 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 2079 &phy_data))) 2080 return ret_val; 2081 2082 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD; 2083 else ctrl &= ~E1000_CTRL_FD; 2084 2085 e1000_config_collision_dist(hw); 2086 2087 /* Set up speed in the Device Control register depending on 2088 * negotiated values. 2089 */ 2090 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 2091 IGP01E1000_PSSR_SPEED_1000MBPS) 2092 ctrl |= E1000_CTRL_SPD_1000; 2093 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 2094 IGP01E1000_PSSR_SPEED_100MBPS) 2095 ctrl |= E1000_CTRL_SPD_100; 2096 } else { 2097 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 2098 &phy_data))) 2099 return ret_val; 2100 2101 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; 2102 else ctrl &= ~E1000_CTRL_FD; 2103 2104 e1000_config_collision_dist(hw); 2105 2106 /* Set up speed in the Device Control register depending on 2107 * negotiated values. 2108 */ 2109 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2110 ctrl |= E1000_CTRL_SPD_1000; 2111 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 2112 ctrl |= E1000_CTRL_SPD_100; 2113 } 2114 /* Write the configured values back to the Device Control Reg. */ 2115 E1000_WRITE_REG(hw, CTRL, ctrl); 2116 return E1000_SUCCESS; 2117} 2118 2119/****************************************************************************** 2120 * Forces the MAC's flow control settings. 2121 * 2122 * hw - Struct containing variables accessed by shared code 2123 * 2124 * Sets the TFCE and RFCE bits in the device control register to reflect 2125 * the adapter settings. TFCE and RFCE need to be explicitly set by 2126 * software when a Copper PHY is used because autonegotiation is managed 2127 * by the PHY rather than the MAC. Software must also configure these 2128 * bits when link is forced on a fiber connection. 2129 *****************************************************************************/ 2130static int 2131e1000_force_mac_fc(struct e1000_hw *hw) 2132{ 2133 uint32_t ctrl; 2134 2135 DEBUGFUNC("e1000_force_mac_fc"); 2136 2137 /* Get the current configuration of the Device Control Register */ 2138 ctrl = E1000_READ_REG(hw, CTRL); 2139 2140 /* Because we didn't get link via the internal auto-negotiation 2141 * mechanism (we either forced link or we got link via PHY 2142 * auto-neg), we have to manually enable/disable transmit an 2143 * receive flow control. 2144 * 2145 * The "Case" statement below enables/disable flow control 2146 * according to the "hw->fc" parameter. 2147 * 2148 * The possible values of the "fc" parameter are: 2149 * 0: Flow control is completely disabled 2150 * 1: Rx flow control is enabled (we can receive pause 2151 * frames but not send pause frames). 2152 * 2: Tx flow control is enabled (we can send pause frames 2153 * frames but we do not receive pause frames). 2154 * 3: Both Rx and TX flow control (symmetric) is enabled. 2155 * other: No other values should be possible at this point. 2156 */ 2157 2158 switch (hw->fc) { 2159 case e1000_fc_none: 2160 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2161 break; 2162 case e1000_fc_rx_pause: 2163 ctrl &= (~E1000_CTRL_TFCE); 2164 ctrl |= E1000_CTRL_RFCE; 2165 break; 2166 case e1000_fc_tx_pause: 2167 ctrl &= (~E1000_CTRL_RFCE); 2168 ctrl |= E1000_CTRL_TFCE; 2169 break; 2170 case e1000_fc_full: 2171 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2172 break; 2173 default: 2174 DEBUGOUT("Flow control param set incorrectly\n"); 2175 return -E1000_ERR_CONFIG; 2176 } 2177 2178 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2179 if(hw->mac_type == e1000_82542_rev2_0) 2180 ctrl &= (~E1000_CTRL_TFCE); 2181 2182 E1000_WRITE_REG(hw, CTRL, ctrl); 2183 return E1000_SUCCESS; 2184} 2185 2186/****************************************************************************** 2187 * Configures flow control settings after link is established 2188 * 2189 * hw - Struct containing variables accessed by shared code 2190 * 2191 * Should be called immediately after a valid link has been established. 2192 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2193 * and autonegotiation is enabled, the MAC flow control settings will be set 2194 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2195 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 2196 *****************************************************************************/ 2197static int 2198e1000_config_fc_after_link_up(struct e1000_hw *hw) 2199{ 2200 int32_t ret_val; 2201 uint16_t mii_status_reg; 2202 uint16_t mii_nway_adv_reg; 2203 uint16_t mii_nway_lp_ability_reg; 2204 uint16_t speed; 2205 uint16_t duplex; 2206 2207 DEBUGFUNC("e1000_config_fc_after_link_up"); 2208 2209 /* Check for the case where we have fiber media and auto-neg failed 2210 * so we had to force link. In this case, we need to force the 2211 * configuration of the MAC to match the "fc" parameter. 2212 */ 2213 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 2214 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 2215 if((ret_val = e1000_force_mac_fc(hw))) { 2216 DEBUGOUT("Error forcing flow control settings\n"); 2217 return ret_val; 2218 } 2219 } 2220 2221 /* Check for the case where we have copper media and auto-neg is 2222 * enabled. In this case, we need to check and see if Auto-Neg 2223 * has completed, and if so, how the PHY and link partner has 2224 * flow control configured. 2225 */ 2226 if(hw->media_type == e1000_media_type_copper) { 2227 /* Read the MII Status Register and check to see if AutoNeg 2228 * has completed. We read this twice because this reg has 2229 * some "sticky" (latched) bits. 2230 */ 2231 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg))) 2232 return ret_val; 2233 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg))) 2234 return ret_val; 2235 2236 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2237 /* The AutoNeg process has completed, so we now need to 2238 * read both the Auto Negotiation Advertisement Register 2239 * (Address 4) and the Auto_Negotiation Base Page Ability 2240 * Register (Address 5) to determine how flow control was 2241 * negotiated. 2242 */ 2243 if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2244 &mii_nway_adv_reg))) 2245 return ret_val; 2246 if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2247 &mii_nway_lp_ability_reg))) 2248 return ret_val; 2249 2250 /* Two bits in the Auto Negotiation Advertisement Register 2251 * (Address 4) and two bits in the Auto Negotiation Base 2252 * Page Ability Register (Address 5) determine flow control 2253 * for both the PHY and the link partner. The following 2254 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2255 * 1999, describes these PAUSE resolution bits and how flow 2256 * control is determined based upon these settings. 2257 * NOTE: DC = Don't Care 2258 * 2259 * LOCAL DEVICE | LINK PARTNER 2260 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2261 *-------|---------|-------|---------|-------------------- 2262 * 0 | 0 | DC | DC | e1000_fc_none 2263 * 0 | 1 | 0 | DC | e1000_fc_none 2264 * 0 | 1 | 1 | 0 | e1000_fc_none 2265 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2266 * 1 | 0 | 0 | DC | e1000_fc_none 2267 * 1 | DC | 1 | DC | e1000_fc_full 2268 * 1 | 1 | 0 | 0 | e1000_fc_none 2269 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2270 * 2271 */ 2272 /* Are both PAUSE bits set to 1? If so, this implies 2273 * Symmetric Flow Control is enabled at both ends. The 2274 * ASM_DIR bits are irrelevant per the spec. 2275 * 2276 * For Symmetric Flow Control: 2277 * 2278 * LOCAL DEVICE | LINK PARTNER 2279 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2280 *-------|---------|-------|---------|-------------------- 2281 * 1 | DC | 1 | DC | e1000_fc_full 2282 * 2283 */ 2284 if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2285 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2286 /* Now we need to check if the user selected RX ONLY 2287 * of pause frames. In this case, we had to advertise 2288 * FULL flow control because we could not advertise RX 2289 * ONLY. Hence, we must now check to see if we need to 2290 * turn OFF the TRANSMISSION of PAUSE frames. 2291 */ 2292#if 0 2293 if(hw->original_fc == e1000_fc_full) { 2294 hw->fc = e1000_fc_full; 2295#else 2296 if(hw->fc == e1000_fc_full) { 2297#endif 2298 DEBUGOUT("Flow Control = FULL.\r\n"); 2299 } else { 2300 hw->fc = e1000_fc_rx_pause; 2301 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 2302 } 2303 } 2304 /* For receiving PAUSE frames ONLY. 2305 * 2306 * LOCAL DEVICE | LINK PARTNER 2307 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2308 *-------|---------|-------|---------|-------------------- 2309 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2310 * 2311 */ 2312 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2313 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2314 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2315 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2316 hw->fc = e1000_fc_tx_pause; 2317 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 2318 } 2319 /* For transmitting PAUSE frames ONLY. 2320 * 2321 * LOCAL DEVICE | LINK PARTNER 2322 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2323 *-------|---------|-------|---------|-------------------- 2324 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2325 * 2326 */ 2327 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2328 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2329 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2330 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2331 hw->fc = e1000_fc_rx_pause; 2332 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 2333 } 2334 /* Per the IEEE spec, at this point flow control should be 2335 * disabled. However, we want to consider that we could 2336 * be connected to a legacy switch that doesn't advertise 2337 * desired flow control, but can be forced on the link 2338 * partner. So if we advertised no flow control, that is 2339 * what we will resolve to. If we advertised some kind of 2340 * receive capability (Rx Pause Only or Full Flow Control) 2341 * and the link partner advertised none, we will configure 2342 * ourselves to enable Rx Flow Control only. We can do 2343 * this safely for two reasons: If the link partner really 2344 * didn't want flow control enabled, and we enable Rx, no 2345 * harm done since we won't be receiving any PAUSE frames 2346 * anyway. If the intent on the link partner was to have 2347 * flow control enabled, then by us enabling RX only, we 2348 * can at least receive pause frames and process them. 2349 * This is a good idea because in most cases, since we are 2350 * predominantly a server NIC, more times than not we will 2351 * be asked to delay transmission of packets than asking 2352 * our link partner to pause transmission of frames. 2353 */ 2354#if 0 2355 else if(hw->original_fc == e1000_fc_none || 2356 hw->original_fc == e1000_fc_tx_pause) { 2357#else 2358 else if(hw->fc == e1000_fc_none) 2359 DEBUGOUT("Flow Control = NONE.\r\n"); 2360 else if(hw->fc == e1000_fc_tx_pause) { 2361#endif 2362 hw->fc = e1000_fc_none; 2363 DEBUGOUT("Flow Control = NONE.\r\n"); 2364 } else { 2365 hw->fc = e1000_fc_rx_pause; 2366 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 2367 } 2368 2369 /* Now we need to do one last check... If we auto- 2370 * negotiated to HALF DUPLEX, flow control should not be 2371 * enabled per IEEE 802.3 spec. 2372 */ 2373 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2374 2375 if(duplex == HALF_DUPLEX) 2376 hw->fc = e1000_fc_none; 2377 2378 /* Now we call a subroutine to actually force the MAC 2379 * controller to use the correct flow control settings. 2380 */ 2381 if((ret_val = e1000_force_mac_fc(hw))) { 2382 DEBUGOUT("Error forcing flow control settings\n"); 2383 return ret_val; 2384 } 2385 } else { 2386 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n"); 2387 } 2388 } 2389 return E1000_SUCCESS; 2390} 2391 2392/****************************************************************************** 2393 * Checks to see if the link status of the hardware has changed. 2394 * 2395 * hw - Struct containing variables accessed by shared code 2396 * 2397 * Called by any function that needs to check the link status of the adapter. 2398 *****************************************************************************/ 2399static int 2400e1000_check_for_link(struct e1000_hw *hw) 2401{ 2402 uint32_t rxcw; 2403 uint32_t ctrl; 2404 uint32_t status; 2405 uint32_t rctl; 2406 uint32_t signal = 0; 2407 int32_t ret_val; 2408 uint16_t phy_data; 2409 uint16_t lp_capability; 2410 2411 DEBUGFUNC("e1000_check_for_link"); 2412 2413 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2414 * set when the optics detect a signal. On older adapters, it will be 2415 * cleared when there is a signal. This applies to fiber media only. 2416 */ 2417 if(hw->media_type == e1000_media_type_fiber) 2418 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2419 2420 ctrl = E1000_READ_REG(hw, CTRL); 2421 status = E1000_READ_REG(hw, STATUS); 2422 rxcw = E1000_READ_REG(hw, RXCW); 2423 2424 /* If we have a copper PHY then we only want to go out to the PHY 2425 * registers to see if Auto-Neg has completed and/or if our link 2426 * status has changed. The get_link_status flag will be set if we 2427 * receive a Link Status Change interrupt or we have Rx Sequence 2428 * Errors. 2429 */ 2430#if 0 2431 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2432#else 2433 if(hw->media_type == e1000_media_type_copper) { 2434#endif 2435 /* First we want to see if the MII Status Register reports 2436 * link. If so, then we want to get the current speed/duplex 2437 * of the PHY. 2438 * Read the register twice since the link bit is sticky. 2439 */ 2440 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data))) 2441 return ret_val; 2442 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data))) 2443 return ret_val; 2444 2445 if(phy_data & MII_SR_LINK_STATUS) { 2446#if 0 2447 hw->get_link_status = FALSE; 2448#endif 2449 } else { 2450 /* No link detected */ 2451 return -E1000_ERR_NOLINK; 2452 } 2453 2454 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2455 * have Si on board that is 82544 or newer, Auto 2456 * Speed Detection takes care of MAC speed/duplex 2457 * configuration. So we only need to configure Collision 2458 * Distance in the MAC. Otherwise, we need to force 2459 * speed/duplex on the MAC to the current PHY speed/duplex 2460 * settings. 2461 */ 2462 if(hw->mac_type >= e1000_82544) 2463 e1000_config_collision_dist(hw); 2464 else { 2465 if((ret_val = e1000_config_mac_to_phy(hw))) { 2466 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2467 return ret_val; 2468 } 2469 } 2470 2471 /* Configure Flow Control now that Auto-Neg has completed. First, we 2472 * need to restore the desired flow control settings because we may 2473 * have had to re-autoneg with a different link partner. 2474 */ 2475 if((ret_val = e1000_config_fc_after_link_up(hw))) { 2476 DEBUGOUT("Error configuring flow control\n"); 2477 return ret_val; 2478 } 2479 2480 /* At this point we know that we are on copper and we have 2481 * auto-negotiated link. These are conditions for checking the link 2482 * parter capability register. We use the link partner capability to 2483 * determine if TBI Compatibility needs to be turned on or off. If 2484 * the link partner advertises any speed in addition to Gigabit, then 2485 * we assume that they are GMII-based, and TBI compatibility is not 2486 * needed. If no other speeds are advertised, we assume the link 2487 * partner is TBI-based, and we turn on TBI Compatibility. 2488 */ 2489 if(hw->tbi_compatibility_en) { 2490 if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2491 &lp_capability))) 2492 return ret_val; 2493 if(lp_capability & (NWAY_LPAR_10T_HD_CAPS | 2494 NWAY_LPAR_10T_FD_CAPS | 2495 NWAY_LPAR_100TX_HD_CAPS | 2496 NWAY_LPAR_100TX_FD_CAPS | 2497 NWAY_LPAR_100T4_CAPS)) { 2498 /* If our link partner advertises anything in addition to 2499 * gigabit, we do not need to enable TBI compatibility. 2500 */ 2501 if(hw->tbi_compatibility_on) { 2502 /* If we previously were in the mode, turn it off. */ 2503 rctl = E1000_READ_REG(hw, RCTL); 2504 rctl &= ~E1000_RCTL_SBP; 2505 E1000_WRITE_REG(hw, RCTL, rctl); 2506 hw->tbi_compatibility_on = FALSE; 2507 } 2508 } else { 2509 /* If TBI compatibility is was previously off, turn it on. For 2510 * compatibility with a TBI link partner, we will store bad 2511 * packets. Some frames have an additional byte on the end and 2512 * will look like CRC errors to to the hardware. 2513 */ 2514 if(!hw->tbi_compatibility_on) { 2515 hw->tbi_compatibility_on = TRUE; 2516 rctl = E1000_READ_REG(hw, RCTL); 2517 rctl |= E1000_RCTL_SBP; 2518 E1000_WRITE_REG(hw, RCTL, rctl); 2519 } 2520 } 2521 } 2522 } 2523 /* If we don't have link (auto-negotiation failed or link partner cannot 2524 * auto-negotiate), the cable is plugged in (we have signal), and our 2525 * link partner is not trying to auto-negotiate with us (we are receiving 2526 * idles or data), we need to force link up. We also need to give 2527 * auto-negotiation time to complete, in case the cable was just plugged 2528 * in. The autoneg_failed flag does this. 2529 */ 2530 else if((((hw->media_type == e1000_media_type_fiber) && 2531 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 2532 (hw->media_type == e1000_media_type_internal_serdes)) && 2533 (!(status & E1000_STATUS_LU)) && 2534 (!(rxcw & E1000_RXCW_C))) { 2535 if(hw->autoneg_failed == 0) { 2536 hw->autoneg_failed = 1; 2537 return 0; 2538 } 2539 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 2540 2541 /* Disable auto-negotiation in the TXCW register */ 2542 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2543 2544 /* Force link-up and also force full-duplex. */ 2545 ctrl = E1000_READ_REG(hw, CTRL); 2546 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2547 E1000_WRITE_REG(hw, CTRL, ctrl); 2548 2549 /* Configure Flow Control after forcing link up. */ 2550 if((ret_val = e1000_config_fc_after_link_up(hw))) { 2551 DEBUGOUT("Error configuring flow control\n"); 2552 return ret_val; 2553 } 2554 } 2555 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 2556 * auto-negotiation in the TXCW register and disable forced link in the 2557 * Device Control register in an attempt to auto-negotiate with our link 2558 * partner. 2559 */ 2560 else if(((hw->media_type == e1000_media_type_fiber) || 2561 (hw->media_type == e1000_media_type_internal_serdes)) && 2562 (ctrl & E1000_CTRL_SLU) && 2563 (rxcw & E1000_RXCW_C)) { 2564 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 2565 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2566 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2567 } 2568#if 0 2569 /* If we force link for non-auto-negotiation switch, check link status 2570 * based on MAC synchronization for internal serdes media type. 2571 */ 2572 else if((hw->media_type == e1000_media_type_internal_serdes) && 2573 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 2574 /* SYNCH bit and IV bit are sticky. */ 2575 udelay(10); 2576 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 2577 if(!(rxcw & E1000_RXCW_IV)) { 2578 hw->serdes_link_down = FALSE; 2579 DEBUGOUT("SERDES: Link is up.\n"); 2580 } 2581 } else { 2582 hw->serdes_link_down = TRUE; 2583 DEBUGOUT("SERDES: Link is down.\n"); 2584 } 2585 } 2586#endif 2587 return E1000_SUCCESS; 2588} 2589 2590/****************************************************************************** 2591 * Detects the current speed and duplex settings of the hardware. 2592 * 2593 * hw - Struct containing variables accessed by shared code 2594 * speed - Speed of the connection 2595 * duplex - Duplex setting of the connection 2596 *****************************************************************************/ 2597static void 2598e1000_get_speed_and_duplex(struct e1000_hw *hw, 2599 uint16_t *speed, 2600 uint16_t *duplex) 2601{ 2602 uint32_t status; 2603 2604 DEBUGFUNC("e1000_get_speed_and_duplex"); 2605 2606 if(hw->mac_type >= e1000_82543) { 2607 status = E1000_READ_REG(hw, STATUS); 2608 if(status & E1000_STATUS_SPEED_1000) { 2609 *speed = SPEED_1000; 2610 DEBUGOUT("1000 Mbs, "); 2611 } else if(status & E1000_STATUS_SPEED_100) { 2612 *speed = SPEED_100; 2613 DEBUGOUT("100 Mbs, "); 2614 } else { 2615 *speed = SPEED_10; 2616 DEBUGOUT("10 Mbs, "); 2617 } 2618 2619 if(status & E1000_STATUS_FD) { 2620 *duplex = FULL_DUPLEX; 2621 DEBUGOUT("Full Duplex\r\n"); 2622 } else { 2623 *duplex = HALF_DUPLEX; 2624 DEBUGOUT(" Half Duplex\r\n"); 2625 } 2626 } else { 2627 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 2628 *speed = SPEED_1000; 2629 *duplex = FULL_DUPLEX; 2630 } 2631} 2632 2633/****************************************************************************** 2634* Blocks until autoneg completes or times out (~4.5 seconds) 2635* 2636* hw - Struct containing variables accessed by shared code 2637******************************************************************************/ 2638static int 2639e1000_wait_autoneg(struct e1000_hw *hw) 2640{ 2641 int32_t ret_val; 2642 uint16_t i; 2643 uint16_t phy_data; 2644 2645 DEBUGFUNC("e1000_wait_autoneg"); 2646 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2647 2648 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2649 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2650 /* Read the MII Status Register and wait for Auto-Neg 2651 * Complete bit to be set. 2652 */ 2653 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data))) 2654 return ret_val; 2655 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data))) 2656 return ret_val; 2657 if(phy_data & MII_SR_AUTONEG_COMPLETE) { 2658 DEBUGOUT("Auto-Neg complete.\n"); 2659 return E1000_SUCCESS; 2660 } 2661 mdelay(100); 2662 } 2663 DEBUGOUT("Auto-Neg timedout.\n"); 2664 return -E1000_ERR_TIMEOUT; 2665} 2666 2667/****************************************************************************** 2668* Raises the Management Data Clock 2669* 2670* hw - Struct containing variables accessed by shared code 2671* ctrl - Device control register's current value 2672******************************************************************************/ 2673static void 2674e1000_raise_mdi_clk(struct e1000_hw *hw, 2675 uint32_t *ctrl) 2676{ 2677 /* Raise the clock input to the Management Data Clock (by setting the MDC 2678 * bit), and then delay 10 microseconds. 2679 */ 2680 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2681 E1000_WRITE_FLUSH(hw); 2682 udelay(10); 2683} 2684 2685/****************************************************************************** 2686* Lowers the Management Data Clock 2687* 2688* hw - Struct containing variables accessed by shared code 2689* ctrl - Device control register's current value 2690******************************************************************************/ 2691static void 2692e1000_lower_mdi_clk(struct e1000_hw *hw, 2693 uint32_t *ctrl) 2694{ 2695 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2696 * bit), and then delay 10 microseconds. 2697 */ 2698 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2699 E1000_WRITE_FLUSH(hw); 2700 udelay(10); 2701} 2702 2703/****************************************************************************** 2704* Shifts data bits out to the PHY 2705* 2706* hw - Struct containing variables accessed by shared code 2707* data - Data to send out to the PHY 2708* count - Number of bits to shift out 2709* 2710* Bits are shifted out in MSB to LSB order. 2711******************************************************************************/ 2712static void 2713e1000_shift_out_mdi_bits(struct e1000_hw *hw, 2714 uint32_t data, 2715 uint16_t count) 2716{ 2717 uint32_t ctrl; 2718 uint32_t mask; 2719 2720 /* We need to shift "count" number of bits out to the PHY. So, the value 2721 * in the "data" parameter will be shifted out to the PHY one bit at a 2722 * time. In order to do this, "data" must be broken down into bits. 2723 */ 2724 mask = 0x01; 2725 mask <<= (count - 1); 2726 2727 ctrl = E1000_READ_REG(hw, CTRL); 2728 2729 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2730 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2731 2732 while(mask) { 2733 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2734 * then raising and lowering the Management Data Clock. A "0" is 2735 * shifted out to the PHY by setting the MDIO bit to "0" and then 2736 * raising and lowering the clock. 2737 */ 2738 if(data & mask) ctrl |= E1000_CTRL_MDIO; 2739 else ctrl &= ~E1000_CTRL_MDIO; 2740 2741 E1000_WRITE_REG(hw, CTRL, ctrl); 2742 E1000_WRITE_FLUSH(hw); 2743 2744 udelay(10); 2745 2746 e1000_raise_mdi_clk(hw, &ctrl); 2747 e1000_lower_mdi_clk(hw, &ctrl); 2748 2749 mask = mask >> 1; 2750 } 2751} 2752 2753/****************************************************************************** 2754* Shifts data bits in from the PHY 2755* 2756* hw - Struct containing variables accessed by shared code 2757* 2758* Bits are shifted in in MSB to LSB order. 2759******************************************************************************/ 2760static uint16_t 2761e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2762{ 2763 uint32_t ctrl; 2764 uint16_t data = 0; 2765 uint8_t i; 2766 2767 /* In order to read a register from the PHY, we need to shift in a total 2768 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2769 * to avoid contention on the MDIO pin when a read operation is performed. 2770 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2771 * by raising the input to the Management Data Clock (setting the MDC bit), 2772 * and then reading the value of the MDIO bit. 2773 */ 2774 ctrl = E1000_READ_REG(hw, CTRL); 2775 2776 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2777 ctrl &= ~E1000_CTRL_MDIO_DIR; 2778 ctrl &= ~E1000_CTRL_MDIO; 2779 2780 E1000_WRITE_REG(hw, CTRL, ctrl); 2781 E1000_WRITE_FLUSH(hw); 2782 2783 /* Raise and Lower the clock before reading in the data. This accounts for 2784 * the turnaround bits. The first clock occurred when we clocked out the 2785 * last bit of the Register Address. 2786 */ 2787 e1000_raise_mdi_clk(hw, &ctrl); 2788 e1000_lower_mdi_clk(hw, &ctrl); 2789 2790 for(data = 0, i = 0; i < 16; i++) { 2791 data = data << 1; 2792 e1000_raise_mdi_clk(hw, &ctrl); 2793 ctrl = E1000_READ_REG(hw, CTRL); 2794 /* Check to see if we shifted in a "1". */ 2795 if(ctrl & E1000_CTRL_MDIO) data |= 1; 2796 e1000_lower_mdi_clk(hw, &ctrl); 2797 } 2798 2799 e1000_raise_mdi_clk(hw, &ctrl); 2800 e1000_lower_mdi_clk(hw, &ctrl); 2801 2802 return data; 2803} 2804 2805/***************************************************************************** 2806* Reads the value from a PHY register, if the value is on a specific non zero 2807* page, sets the page first. 2808* 2809* hw - Struct containing variables accessed by shared code 2810* reg_addr - address of the PHY register to read 2811******************************************************************************/ 2812static int 2813e1000_read_phy_reg(struct e1000_hw *hw, 2814 uint32_t reg_addr, 2815 uint16_t *phy_data) 2816{ 2817 uint32_t ret_val; 2818 2819 DEBUGFUNC("e1000_read_phy_reg"); 2820 2821 if(hw->phy_type == e1000_phy_igp && 2822 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2823 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2824 (uint16_t)reg_addr))) 2825 return ret_val; 2826 } 2827 2828 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr, 2829 phy_data); 2830 2831 return ret_val; 2832} 2833 2834static int 2835e1000_read_phy_reg_ex(struct e1000_hw *hw, 2836 uint32_t reg_addr, 2837 uint16_t *phy_data) 2838{ 2839 uint32_t i; 2840 uint32_t mdic = 0; 2841 const uint32_t phy_addr = 1; 2842 2843 DEBUGFUNC("e1000_read_phy_reg_ex"); 2844 2845 if(reg_addr > MAX_PHY_REG_ADDRESS) { 2846 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2847 return -E1000_ERR_PARAM; 2848 } 2849 2850 if(hw->mac_type > e1000_82543) { 2851 /* Set up Op-code, Phy Address, and register address in the MDI 2852 * Control register. The MAC will take care of interfacing with the 2853 * PHY to retrieve the desired data. 2854 */ 2855 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2856 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2857 (E1000_MDIC_OP_READ)); 2858 2859 E1000_WRITE_REG(hw, MDIC, mdic); 2860 2861 /* Poll the ready bit to see if the MDI read completed */ 2862 for(i = 0; i < 64; i++) { 2863 udelay(50); 2864 mdic = E1000_READ_REG(hw, MDIC); 2865 if(mdic & E1000_MDIC_READY) break; 2866 } 2867 if(!(mdic & E1000_MDIC_READY)) { 2868 DEBUGOUT("MDI Read did not complete\n"); 2869 return -E1000_ERR_PHY; 2870 } 2871 if(mdic & E1000_MDIC_ERROR) { 2872 DEBUGOUT("MDI Error\n"); 2873 return -E1000_ERR_PHY; 2874 } 2875 *phy_data = (uint16_t) mdic; 2876 } else { 2877 /* We must first send a preamble through the MDIO pin to signal the 2878 * beginning of an MII instruction. This is done by sending 32 2879 * consecutive "1" bits. 2880 */ 2881 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2882 2883 /* Now combine the next few fields that are required for a read 2884 * operation. We use this method instead of calling the 2885 * e1000_shift_out_mdi_bits routine five different times. The format of 2886 * a MII read instruction consists of a shift out of 14 bits and is 2887 * defined as follows: 2888 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2889 * followed by a shift in of 18 bits. This first two bits shifted in 2890 * are TurnAround bits used to avoid contention on the MDIO pin when a 2891 * READ operation is performed. These two bits are thrown away 2892 * followed by a shift in of 16 bits which contains the desired data. 2893 */ 2894 mdic = ((reg_addr) | (phy_addr << 5) | 2895 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2896 2897 e1000_shift_out_mdi_bits(hw, mdic, 14); 2898 2899 /* Now that we've shifted out the read command to the MII, we need to 2900 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2901 * register address. 2902 */ 2903 *phy_data = e1000_shift_in_mdi_bits(hw); 2904 } 2905 return E1000_SUCCESS; 2906} 2907 2908/****************************************************************************** 2909* Writes a value to a PHY register 2910* 2911* hw - Struct containing variables accessed by shared code 2912* reg_addr - address of the PHY register to write 2913* data - data to write to the PHY 2914******************************************************************************/ 2915static int 2916e1000_write_phy_reg(struct e1000_hw *hw, 2917 uint32_t reg_addr, 2918 uint16_t phy_data) 2919{ 2920 uint32_t ret_val; 2921 2922 DEBUGFUNC("e1000_write_phy_reg"); 2923 2924 if(hw->phy_type == e1000_phy_igp && 2925 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2926 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2927 (uint16_t)reg_addr))) 2928 return ret_val; 2929 } 2930 2931 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr, 2932 phy_data); 2933 2934 return ret_val; 2935} 2936 2937static int 2938e1000_write_phy_reg_ex(struct e1000_hw *hw, 2939 uint32_t reg_addr, 2940 uint16_t phy_data) 2941{ 2942 uint32_t i; 2943 uint32_t mdic = 0; 2944 const uint32_t phy_addr = 1; 2945 2946 DEBUGFUNC("e1000_write_phy_reg_ex"); 2947 2948 if(reg_addr > MAX_PHY_REG_ADDRESS) { 2949 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2950 return -E1000_ERR_PARAM; 2951 } 2952 2953 if(hw->mac_type > e1000_82543) { 2954 /* Set up Op-code, Phy Address, register address, and data intended 2955 * for the PHY register in the MDI Control register. The MAC will take 2956 * care of interfacing with the PHY to send the desired data. 2957 */ 2958 mdic = (((uint32_t) phy_data) | 2959 (reg_addr << E1000_MDIC_REG_SHIFT) | 2960 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2961 (E1000_MDIC_OP_WRITE)); 2962 2963 E1000_WRITE_REG(hw, MDIC, mdic); 2964 2965 /* Poll the ready bit to see if the MDI read completed */ 2966 for(i = 0; i < 640; i++) { 2967 udelay(5); 2968 mdic = E1000_READ_REG(hw, MDIC); 2969 if(mdic & E1000_MDIC_READY) break; 2970 } 2971 if(!(mdic & E1000_MDIC_READY)) { 2972 DEBUGOUT("MDI Write did not complete\n"); 2973 return -E1000_ERR_PHY; 2974 } 2975 } else { 2976 /* We'll need to use the SW defined pins to shift the write command 2977 * out to the PHY. We first send a preamble to the PHY to signal the 2978 * beginning of the MII instruction. This is done by sending 32 2979 * consecutive "1" bits. 2980 */ 2981 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2982 2983 /* Now combine the remaining required fields that will indicate a 2984 * write operation. We use this method instead of calling the 2985 * e1000_shift_out_mdi_bits routine for each field in the command. The 2986 * format of a MII write instruction is as follows: 2987 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2988 */ 2989 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2990 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2991 mdic <<= 16; 2992 mdic |= (uint32_t) phy_data; 2993 2994 e1000_shift_out_mdi_bits(hw, mdic, 32); 2995 } 2996 2997 return E1000_SUCCESS; 2998} 2999 3000/****************************************************************************** 3001* Returns the PHY to the power-on reset state 3002* 3003* hw - Struct containing variables accessed by shared code 3004******************************************************************************/ 3005static void 3006e1000_phy_hw_reset(struct e1000_hw *hw) 3007{ 3008 uint32_t ctrl, ctrl_ext; 3009 3010 DEBUGFUNC("e1000_phy_hw_reset"); 3011 3012 DEBUGOUT("Resetting Phy...\n"); 3013 3014 if(hw->mac_type > e1000_82543) { 3015 /* Read the device control register and assert the E1000_CTRL_PHY_RST 3016 * bit. Then, take it out of reset. 3017 */ 3018 ctrl = E1000_READ_REG(hw, CTRL); 3019 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 3020 E1000_WRITE_FLUSH(hw); 3021 mdelay(10); 3022 E1000_WRITE_REG(hw, CTRL, ctrl); 3023 E1000_WRITE_FLUSH(hw); 3024 } else { 3025 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3026 * bit to put the PHY into reset. Then, take it out of reset. 3027 */ 3028 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3029 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3030 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3031 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3032 E1000_WRITE_FLUSH(hw); 3033 mdelay(10); 3034 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3035 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3036 E1000_WRITE_FLUSH(hw); 3037 } 3038 udelay(150); 3039} 3040 3041/****************************************************************************** 3042* Resets the PHY 3043* 3044* hw - Struct containing variables accessed by shared code 3045* 3046* Sets bit 15 of the MII Control regiser 3047******************************************************************************/ 3048static int 3049e1000_phy_reset(struct e1000_hw *hw) 3050{ 3051 int32_t ret_val; 3052 uint16_t phy_data; 3053 3054 DEBUGFUNC("e1000_phy_reset"); 3055 3056 if(hw->mac_type != e1000_82541_rev_2) { 3057 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data))) 3058 return ret_val; 3059 3060 phy_data |= MII_CR_RESET; 3061 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data))) 3062 return ret_val; 3063 3064 udelay(1); 3065 } else e1000_phy_hw_reset(hw); 3066 3067 if(hw->phy_type == e1000_phy_igp) 3068 e1000_phy_init_script(hw); 3069 3070 return E1000_SUCCESS; 3071} 3072 3073/****************************************************************************** 3074* Probes the expected PHY address for known PHY IDs 3075* 3076* hw - Struct containing variables accessed by shared code 3077******************************************************************************/ 3078static int 3079e1000_detect_gig_phy(struct e1000_hw *hw) 3080{ 3081 int32_t phy_init_status, ret_val; 3082 uint16_t phy_id_high, phy_id_low; 3083 boolean_t match = FALSE; 3084 3085 DEBUGFUNC("e1000_detect_gig_phy"); 3086 3087 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3088 if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high))) 3089 return ret_val; 3090 3091 hw->phy_id = (uint32_t) (phy_id_high << 16); 3092 udelay(20); 3093 if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low))) 3094 return ret_val; 3095 3096 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 3097#ifdef LINUX_DRIVER 3098 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 3099#endif 3100 3101 switch(hw->mac_type) { 3102 case e1000_82543: 3103 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 3104 break; 3105 case e1000_82544: 3106 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 3107 break; 3108 case e1000_82540: 3109 case e1000_82545: 3110 case e1000_82545_rev_3: 3111 case e1000_82546: 3112 case e1000_82546_rev_3: 3113 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 3114 break; 3115 case e1000_82541: 3116 case e1000_82541_rev_2: 3117 case e1000_82547: 3118 case e1000_82547_rev_2: 3119 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3120 break; 3121 default: 3122 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3123 return -E1000_ERR_CONFIG; 3124 } 3125 phy_init_status = e1000_set_phy_type(hw); 3126 3127 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3128 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 3129 return E1000_SUCCESS; 3130 } 3131 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 3132 return -E1000_ERR_PHY; 3133} 3134 3135/****************************************************************************** 3136 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3137 * is configured. 3138 * 3139 * hw - Struct containing variables accessed by shared code 3140 *****************************************************************************/ 3141static void 3142e1000_init_eeprom_params(struct e1000_hw *hw) 3143{ 3144 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3145 uint32_t eecd = E1000_READ_REG(hw, EECD); 3146 uint16_t eeprom_size; 3147 3148 DEBUGFUNC("e1000_init_eeprom_params"); 3149 3150 switch (hw->mac_type) { 3151 case e1000_82542_rev2_0: 3152 case e1000_82542_rev2_1: 3153 case e1000_82543: 3154 case e1000_82544: 3155 eeprom->type = e1000_eeprom_microwire; 3156 eeprom->word_size = 64; 3157 eeprom->opcode_bits = 3; 3158 eeprom->address_bits = 6; 3159 eeprom->delay_usec = 50; 3160 break; 3161 case e1000_82540: 3162 case e1000_82545: 3163 case e1000_82545_rev_3: 3164 case e1000_82546: 3165 case e1000_82546_rev_3: 3166 eeprom->type = e1000_eeprom_microwire; 3167 eeprom->opcode_bits = 3; 3168 eeprom->delay_usec = 50; 3169 if(eecd & E1000_EECD_SIZE) { 3170 eeprom->word_size = 256; 3171 eeprom->address_bits = 8; 3172 } else { 3173 eeprom->word_size = 64; 3174 eeprom->address_bits = 6; 3175 } 3176 break; 3177 case e1000_82541: 3178 case e1000_82541_rev_2: 3179 case e1000_82547: 3180 case e1000_82547_rev_2: 3181 if (eecd & E1000_EECD_TYPE) { 3182 eeprom->type = e1000_eeprom_spi; 3183 if (eecd & E1000_EECD_ADDR_BITS) { 3184 eeprom->page_size = 32; 3185 eeprom->address_bits = 16; 3186 } else { 3187 eeprom->page_size = 8; 3188 eeprom->address_bits = 8; 3189 } 3190 } else { 3191 eeprom->type = e1000_eeprom_microwire; 3192 eeprom->opcode_bits = 3; 3193 eeprom->delay_usec = 50; 3194 if (eecd & E1000_EECD_ADDR_BITS) { 3195 eeprom->word_size = 256; 3196 eeprom->address_bits = 8; 3197 } else { 3198 eeprom->word_size = 64; 3199 eeprom->address_bits = 6; 3200 } 3201 } 3202 break; 3203 default: 3204 eeprom->type = e1000_eeprom_spi; 3205 if (eecd & E1000_EECD_ADDR_BITS) { 3206 eeprom->page_size = 32; 3207 eeprom->address_bits = 16; 3208 } else { 3209 eeprom->page_size = 8; 3210 eeprom->address_bits = 8; 3211 } 3212 break; 3213 } 3214 3215 if (eeprom->type == e1000_eeprom_spi) { 3216 eeprom->opcode_bits = 8; 3217 eeprom->delay_usec = 1; 3218 eeprom->word_size = 64; 3219 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { 3220 eeprom_size &= EEPROM_SIZE_MASK; 3221 3222 switch (eeprom_size) { 3223 case EEPROM_SIZE_16KB: 3224 eeprom->word_size = 8192; 3225 break; 3226 case EEPROM_SIZE_8KB: 3227 eeprom->word_size = 4096; 3228 break; 3229 case EEPROM_SIZE_4KB: 3230 eeprom->word_size = 2048; 3231 break; 3232 case EEPROM_SIZE_2KB: 3233 eeprom->word_size = 1024; 3234 break; 3235 case EEPROM_SIZE_1KB: 3236 eeprom->word_size = 512; 3237 break; 3238 case EEPROM_SIZE_512B: 3239 eeprom->word_size = 256; 3240 break; 3241 case EEPROM_SIZE_128B: 3242 default: 3243 break; 3244 } 3245 } 3246 } 3247} 3248 3249/** 3250 * e1000_reset - Reset the adapter 3251 */ 3252 3253static int 3254e1000_reset(struct e1000_hw *hw) 3255{ 3256 uint32_t pba; 3257 /* Repartition Pba for greater than 9k mtu 3258 * To take effect CTRL.RST is required. 3259 */ 3260 3261 if(hw->mac_type < e1000_82547) { 3262 pba = E1000_PBA_48K; 3263 } else { 3264 pba = E1000_PBA_30K; 3265 } 3266 E1000_WRITE_REG(hw, PBA, pba); 3267 3268 /* flow control settings */ 3269#if 0 3270 hw->fc_high_water = FC_DEFAULT_HI_THRESH; 3271 hw->fc_low_water = FC_DEFAULT_LO_THRESH; 3272 hw->fc_pause_time = FC_DEFAULT_TX_TIMER; 3273 hw->fc_send_xon = 1; 3274 hw->fc = hw->original_fc; 3275#endif 3276 3277 e1000_reset_hw(hw); 3278 if(hw->mac_type >= e1000_82544) 3279 E1000_WRITE_REG(hw, WUC, 0); 3280 return e1000_init_hw(hw); 3281} 3282 3283/** 3284 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 3285 * @adapter: board private structure to initialize 3286 * 3287 * e1000_sw_init initializes the Adapter private data structure. 3288 * Fields are initialized based on PCI device information and 3289 * OS network device settings (MTU size). 3290 **/ 3291 3292static int 3293e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw) 3294{ 3295 int result; 3296 3297 /* PCI config space info */ 3298 pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id); 3299 pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id); 3300 pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id); 3301#if 0 3302 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, 3303 &hw->subsystem_vendor_id); 3304 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 3305#endif 3306 3307 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 3308 3309 /* identify the MAC */ 3310 3311 result = e1000_set_mac_type(hw); 3312 if (result) { 3313 E1000_ERR("Unknown MAC Type\n"); 3314 return result; 3315 } 3316 3317 /* initialize eeprom parameters */ 3318 3319 e1000_init_eeprom_params(hw); 3320 3321#if 0 3322 if((hw->mac_type == e1000_82541) || 3323 (hw->mac_type == e1000_82547) || 3324 (hw->mac_type == e1000_82541_rev_2) || 3325 (hw->mac_type == e1000_82547_rev_2)) 3326 hw->phy_init_script = 1; 3327#endif 3328 3329 e1000_set_media_type(hw); 3330 3331#if 0 3332 if(hw->mac_type < e1000_82543) 3333 hw->report_tx_early = 0; 3334 else 3335 hw->report_tx_early = 1; 3336 3337 hw->wait_autoneg_complete = FALSE; 3338#endif 3339 hw->tbi_compatibility_en = TRUE; 3340#if 0 3341 hw->adaptive_ifs = TRUE; 3342 3343 /* Copper options */ 3344 3345 if(hw->media_type == e1000_media_type_copper) { 3346 hw->mdix = AUTO_ALL_MODES; 3347 hw->disable_polarity_correction = FALSE; 3348 hw->master_slave = E1000_MASTER_SLAVE; 3349 } 3350#endif 3351 return E1000_SUCCESS; 3352} 3353 3354static void fill_rx (void) 3355{ 3356 struct e1000_rx_desc *rd; 3357 rx_last = rx_tail; 3358 rd = rx_base + rx_tail; 3359 rx_tail = (rx_tail + 1) % 8; 3360 memset (rd, 0, 16); 3361 rd->buffer_addr = virt_to_bus(&packet); 3362 E1000_WRITE_REG (&hw, RDT, rx_tail); 3363} 3364 3365static void init_descriptor (void) 3366{ 3367 unsigned long ptr; 3368 unsigned long tctl; 3369 3370 ptr = virt_to_phys(tx_pool); 3371 if (ptr & 0xf) 3372 ptr = (ptr + 0x10) & (~0xf); 3373 3374 tx_base = phys_to_virt(ptr); 3375 3376 E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base)); 3377 E1000_WRITE_REG (&hw, TDBAH, 0); 3378 E1000_WRITE_REG (&hw, TDLEN, 128); 3379 3380 /* Setup the HW Tx Head and Tail descriptor pointers */ 3381 3382 E1000_WRITE_REG (&hw, TDH, 0); 3383 E1000_WRITE_REG (&hw, TDT, 0); 3384 tx_tail = 0; 3385 3386 /* Program the Transmit Control Register */ 3387 3388#ifdef LINUX_DRIVER_TCTL 3389 tctl = E1000_READ_REG(&hw, TCTL); 3390 3391 tctl &= ~E1000_TCTL_CT; 3392 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 3393 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3394#else 3395 tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 3396 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 3397 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT); 3398#endif 3399 3400 E1000_WRITE_REG (&hw, TCTL, tctl); 3401 3402 e1000_config_collision_dist(&hw); 3403 3404 3405 rx_tail = 0; 3406 /* disable receive */ 3407 E1000_WRITE_REG (&hw, RCTL, 0); 3408 ptr = virt_to_phys(rx_pool); 3409 if (ptr & 0xf) 3410 ptr = (ptr + 0x10) & (~0xf); 3411 rx_base = phys_to_virt(ptr); 3412 3413 /* Setup the Base and Length of the Rx Descriptor Ring */ 3414 3415 E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base)); 3416 E1000_WRITE_REG (&hw, RDBAH, 0); 3417 3418 E1000_WRITE_REG (&hw, RDLEN, 128); 3419 3420 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 3421 E1000_WRITE_REG (&hw, RDH, 0); 3422 E1000_WRITE_REG (&hw, RDT, 0); 3423 3424 E1000_WRITE_REG (&hw, RCTL, 3425 E1000_RCTL_EN | 3426 E1000_RCTL_BAM | 3427 E1000_RCTL_SZ_2048 | 3428 E1000_RCTL_MPE); 3429 fill_rx(); 3430} 3431 3432 3433 3434/************************************************************************** 3435POLL - Wait for a frame 3436***************************************************************************/ 3437static int 3438e1000_poll (struct nic *nic, int retrieve) 3439{ 3440 /* return true if there's an ethernet packet ready to read */ 3441 /* nic->packet should contain data on return */ 3442 /* nic->packetlen should contain length of data */ 3443 struct e1000_rx_desc *rd; 3444 3445 rd = rx_base + rx_last; 3446 if (!rd->status & E1000_RXD_STAT_DD) 3447 return 0; 3448 3449 if ( ! retrieve ) return 1; 3450 3451 // printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length); 3452 memcpy (nic->packet, packet, rd->length); 3453 nic->packetlen = rd->length; 3454 fill_rx (); 3455 return 1; 3456} 3457 3458/************************************************************************** 3459TRANSMIT - Transmit a frame 3460***************************************************************************/ 3461static void 3462e1000_transmit (struct nic *nic, const char *d, /* Destination */ 3463 unsigned int type, /* Type */ 3464 unsigned int size, /* size */ 3465 const char *p) /* Packet */ 3466{ 3467 /* send the packet to destination */ 3468 struct eth_hdr { 3469 unsigned char dst_addr[ETH_ALEN]; 3470 unsigned char src_addr[ETH_ALEN]; 3471 unsigned short type; 3472 } hdr; 3473 struct e1000_tx_desc *txhd; /* header */ 3474 struct e1000_tx_desc *txp; /* payload */ 3475 DEBUGFUNC("send"); 3476 3477 memcpy (&hdr.dst_addr, d, ETH_ALEN); 3478 memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN); 3479 3480 hdr.type = htons (type); 3481 txhd = tx_base + tx_tail; 3482 tx_tail = (tx_tail + 1) % 8; 3483 txp = tx_base + tx_tail; 3484 tx_tail = (tx_tail + 1) % 8; 3485 3486 txhd->buffer_addr = virt_to_bus (&hdr); 3487 txhd->lower.data = sizeof (hdr); 3488 txhd->upper.data = 0; 3489 3490 txp->buffer_addr = virt_to_bus(p); 3491 txp->lower.data = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | size; 3492 txp->upper.data = 0; 3493 3494 E1000_WRITE_REG (&hw, TDT, tx_tail); 3495 while (!(txp->upper.data & E1000_TXD_STAT_DD)) { 3496 udelay(10); /* give the nic a chance to write to the register */ 3497 poll_interruptions(); 3498 } 3499 DEBUGFUNC("send end"); 3500} 3501 3502 3503/************************************************************************** 3504DISABLE - Turn off ethernet interface 3505***************************************************************************/ 3506static void e1000_disable (struct dev *dev __unused) 3507{ 3508 /* Clear the transmit ring */ 3509 E1000_WRITE_REG (&hw, TDH, 0); 3510 E1000_WRITE_REG (&hw, TDT, 0); 3511 3512 /* Clear the receive ring */ 3513 E1000_WRITE_REG (&hw, RDH, 0); 3514 E1000_WRITE_REG (&hw, RDT, 0); 3515 3516 /* put the card in its initial state */ 3517 E1000_WRITE_REG (&hw, CTRL, E1000_CTRL_RST); 3518 3519 /* Turn off the ethernet interface */ 3520 E1000_WRITE_REG (&hw, RCTL, 0); 3521 E1000_WRITE_REG (&hw, TCTL, 0); 3522 mdelay (10); 3523 3524 /* Unmap my window to the device */ 3525 iounmap(hw.hw_addr); 3526} 3527 3528/************************************************************************** 3529IRQ - Enable, Disable, or Force interrupts 3530***************************************************************************/ 3531static void e1000_irq(struct nic *nic __unused, irq_action_t action __unused) 3532{ 3533 switch ( action ) { 3534 case DISABLE : 3535 break; 3536 case ENABLE : 3537 break; 3538 case FORCE : 3539 break; 3540 } 3541} 3542 3543#define IORESOURCE_IO 0x00000100 /* Resource type */ 3544#define BAR_0 0 3545#define BAR_1 1 3546#define BAR_5 5 3547 3548/************************************************************************** 3549PROBE - Look for an adapter, this routine's visible to the outside 3550You should omit the last argument struct pci_device * for a non-PCI NIC 3551***************************************************************************/ 3552static int e1000_probe(struct dev *dev, struct pci_device *p) 3553{ 3554 struct nic *nic = (struct nic *)dev; 3555 unsigned long mmio_start, mmio_len; 3556 int ret_val, i; 3557 3558 if (p == 0) 3559 return 0; 3560 /* Initialize hw with default values */ 3561 memset(&hw, 0, sizeof(hw)); 3562 hw.pdev = p; 3563 3564#if 1 3565 /* Are these variables needed? */ 3566 hw.fc = e1000_fc_none; 3567#if 0 3568 hw.original_fc = e1000_fc_none; 3569#endif 3570 hw.autoneg_failed = 0; 3571#if 0 3572 hw.get_link_status = TRUE; 3573#endif 3574#endif 3575 3576 mmio_start = pci_bar_start(p, PCI_BASE_ADDRESS_0); 3577 mmio_len = pci_bar_size(p, PCI_BASE_ADDRESS_0); 3578 hw.hw_addr = ioremap(mmio_start, mmio_len); 3579 3580 for(i = BAR_1; i <= BAR_5; i++) { 3581 if(pci_bar_size(p, i) == 0) 3582 continue; 3583 if(pci_find_capability(p, i) & IORESOURCE_IO) { 3584 hw.io_base = pci_bar_start(p, i); 3585 break; 3586 } 3587 } 3588 3589 adjust_pci_device(p); 3590 3591 nic->ioaddr = p->ioaddr & ~3; 3592 nic->irqno = 0; 3593 3594 /* From Matt Hortman <mbhortman@acpthinclient.com> */ 3595 /* MAC and Phy settings */ 3596 3597 /* setup the private structure */ 3598 if (e1000_sw_init(p, &hw) < 0) { 3599 iounmap(hw.hw_addr); 3600 return 0; 3601 } 3602 3603 /* make sure the EEPROM is good */ 3604 3605 if (e1000_validate_eeprom_checksum(&hw) < 0) { 3606 printf ("The EEPROM Checksum Is Not Valid\n"); 3607 iounmap(hw.hw_addr); 3608 return 0; 3609 } 3610 3611 /* copy the MAC address out of the EEPROM */ 3612 3613 e1000_read_mac_addr(&hw); 3614 memcpy (nic->node_addr, hw.mac_addr, ETH_ALEN); 3615 3616 printf("Ethernet addr: %!\n", nic->node_addr); 3617 3618 /* reset the hardware with the new settings */ 3619 3620 ret_val = e1000_reset(&hw); 3621 if (ret_val < 0) { 3622 if ((ret_val == -E1000_ERR_NOLINK) || 3623 (ret_val == -E1000_ERR_TIMEOUT)) { 3624 E1000_ERR("Valid Link not detected\n"); 3625 } else { 3626 E1000_ERR("Hardware Initialization Failed\n"); 3627 } 3628 iounmap(hw.hw_addr); 3629 return 0; 3630 } 3631 init_descriptor(); 3632 3633 /* point to NIC specific routines */ 3634 dev->disable = e1000_disable; 3635 nic->poll = e1000_poll; 3636 nic->transmit = e1000_transmit; 3637 nic->irq = e1000_irq; 3638 3639 return 1; 3640} 3641 3642static struct pci_id e1000_nics[] = { 3643PCI_ROM(0x8086, 0x1000, "e1000-82542", "Intel EtherExpressPro1000"), 3644PCI_ROM(0x8086, 0x1001, "e1000-82543gc-fiber", "Intel EtherExpressPro1000 82543GC Fiber"), 3645PCI_ROM(0x8086, 0x1004, "e1000-82543gc-copper", "Intel EtherExpressPro1000 82543GC Copper"), 3646PCI_ROM(0x8086, 0x1008, "e1000-82544ei-copper", "Intel EtherExpressPro1000 82544EI Copper"), 3647PCI_ROM(0x8086, 0x1009, "e1000-82544ei-fiber", "Intel EtherExpressPro1000 82544EI Fiber"), 3648PCI_ROM(0x8086, 0x100C, "e1000-82544gc-copper", "Intel EtherExpressPro1000 82544GC Copper"), 3649PCI_ROM(0x8086, 0x100D, "e1000-82544gc-lom", "Intel EtherExpressPro1000 82544GC LOM"), 3650PCI_ROM(0x8086, 0x100E, "e1000-82540em", "Intel EtherExpressPro1000 82540EM"), 3651PCI_ROM(0x8086, 0x100F, "e1000-82545em-copper", "Intel EtherExpressPro1000 82545EM Copper"), 3652PCI_ROM(0x8086, 0x1010, "e1000-82546eb-copper", "Intel EtherExpressPro1000 82546EB Copper"), 3653PCI_ROM(0x8086, 0x1011, "e1000-82545em-fiber", "Intel EtherExpressPro1000 82545EM Fiber"), 3654PCI_ROM(0x8086, 0x1012, "e1000-82546eb-fiber", "Intel EtherExpressPro1000 82546EB Copper"), 3655PCI_ROM(0x8086, 0x1013, "e1000-82541ei", "Intel EtherExpressPro1000 82541EI"), 3656PCI_ROM(0x8086, 0x1015, "e1000-82540em-lom", "Intel EtherExpressPro1000 82540EM LOM"), 3657PCI_ROM(0x8086, 0x1016, "e1000-82540ep-lom", "Intel EtherExpressPro1000 82540EP LOM"), 3658PCI_ROM(0x8086, 0x1017, "e1000-82540ep", "Intel EtherExpressPro1000 82540EP"), 3659PCI_ROM(0x8086, 0x1018, "e1000-82541ep", "Intel EtherExpressPro1000 82541EP"), 3660PCI_ROM(0x8086, 0x1019, "e1000-82547ei", "Intel EtherExpressPro1000 82547EI"), 3661PCI_ROM(0x8086, 0x101d, "e1000-82546eb-quad-copper", "Intel EtherExpressPro1000 82546EB Quad Copper"), 3662PCI_ROM(0x8086, 0x101e, "e1000-82540ep-lp", "Intel EtherExpressPro1000 82540EP LP"), 3663PCI_ROM(0x8086, 0x1026, "e1000-82545gm-copper", "Intel EtherExpressPro1000 82545GM Copper"), 3664PCI_ROM(0x8086, 0x1027, "e1000-82545gm-fiber", "Intel EtherExpressPro1000 82545GM Fiber"), 3665PCI_ROM(0x8086, 0x1028, "e1000-82545gm-serdes", "Intel EtherExpressPro1000 82545GM SERDES"), 3666PCI_ROM(0x8086, 0x1075, "e1000-82547gi", "Intel EtherExpressPro1000 82547GI"), 3667PCI_ROM(0x8086, 0x1076, "e1000-82541gi", "Intel EtherExpressPro1000 82541GI"), 3668PCI_ROM(0x8086, 0x1077, "e1000-82541gi-mobile", "Intel EtherExpressPro1000 82541GI Mobile"), 3669PCI_ROM(0x8086, 0x1078, "e1000-82541er", "Intel EtherExpressPro1000 82541ER"), 3670PCI_ROM(0x8086, 0x1079, "e1000-82546gb-copper", "Intel EtherExpressPro1000 82546GB Copper"), 3671PCI_ROM(0x8086, 0x107a, "e1000-82546gb-fiber", "Intel EtherExpressPro1000 82546GB Fiber"), 3672PCI_ROM(0x8086, 0x107b, "e1000-82546gb-serdes", "Intel EtherExpressPro1000 82546GB SERDES"), 3673}; 3674 3675struct pci_driver e1000_driver = { 3676 .type = NIC_DRIVER, 3677 .name = "E1000", 3678 .probe = e1000_probe, 3679 .ids = e1000_nics, 3680 .id_count = sizeof(e1000_nics)/sizeof(e1000_nics[0]), 3681 .class = 0, 3682}; 3683