1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27/* 28 * audiots Audio Driver 29 * 30 * This Audio Driver controls the T2 audio core in the ALI M1553 31 * southbridge chip. This chip supports multiple play streams, but just 32 * a single record stream. It also supports wave table synthesis and 33 * hardware MIDI and joystick ports. Unfortunately the MIDI ports are 34 * not available because their pins have been re-assigned to expose 35 * interrupts. We also aren't going to do anything with the joystick 36 * ports. The audio core controls an AC-97 V2.1 Codec. 37 * 38 * The DMA engine uses a single buffer which is large enough to hold 39 * two interrupts worth of data. When it gets to the mid point an 40 * interrupt is generated and data is either sent (for record) or 41 * requested and put in that half of the buffer (for play). When the 42 * second half is played we do the same, but the audio core loops the 43 * pointer back to the beginning. 44 * 45 * The audio core has a bug in silicon that doesn't let it read the AC-97 46 * Codec's register. T2 has provided an algorithm that attempts to read the 47 * the Codec several times. This is probably heuristic and thus isn't 48 * absolutely guaranteed to work. However we do have to place a limit on 49 * the looping, otherwise when we read a valid 0x00 we would never exit 50 * the loop. Unfortunately there is also a problem with writing the AC-97 51 * Codec's registers as well. Thus we read it back to verify the write. 52 * 53 * The AC'97 common code provides shadow state for AC'97 registers for us, 54 * so we only need to read those registers during early startup (primarily 55 * to determine codec id and capabilities.) 56 * 57 * We don't save any of the audio controller registers during normal 58 * operation. When we need to save register state we only have to save 59 * the aram and eram. The rest of the controller state is never modified 60 * from the initial programming. Thus restoring the controller state 61 * can be done from audiots_chip_init() as well. 62 * 63 * 64 * WARNING: The SME birdsnest platform uses a PCI bridge chip between the 65 * CPU and the southbridge containing the audio core. There is 66 * a bug in silicon that causes a bogus parity error. With the mixer 67 * reimplementation project, Bug 4374774, the audio driver is always 68 * set to the best precision and number of channels. Thus when turning 69 * the mixer on and off the only thing that changes is the sample rate. 70 * This change in programming doesn't trigger the silicon error. 71 * Thus the supported channels must always be 2 and the precision 72 * must always be 16-bits. This will keep any future change in the 73 * mixer from exposing this bug. 74 * 75 * Due to a hardware bug, system power management is not supported by this 76 * driver. 77 * 78 * CAUTION: If audio controller state is changed outside of aram 79 * and eram then that information must be saved and restored 80 * during power management shutdown and bringup. 81 * 82 * NOTE: The AC-97 Codec's reset pin is set to PCI reset, so we 83 * can't power down the Codec all the way. 84 * 85 * NOTE: This driver depends on the drv/audio and misc/ac97 86 * modules being loaded first. 87 * 88 * NOTE: Don't OR the ap_stop register to stop a play or record. This 89 * will just stop all active channels because a read of ap_stop 90 * returns ap_start. Just set the ap_stop register with the 91 * channels you want to stop. The same goes for ap_start. 92 * 93 * NOTE: There is a hardware problem with P2 rev motherboards. After 94 * prolonged use, reading the AC97 register will always return 95 * busy. The AC97 register is now useless. Consequently, we are no 96 * longer able to program the Codec. This work around disables 97 * audio when this state is detected. It's not great, but its 98 * better than having audio blasting out at 100% all the time. 99 * 100 * NOTE: Power Management testing has also exposed this AC97 timeout 101 * problem. Management has decided this is too risky for customers 102 * and hence they want power management support removed from the 103 * audio subsystem. All PM support is now removed. 104 */ 105 106/* 107 * Synchronization notes: 108 * 109 * The audio framework guarantees that our entry points are exclusive 110 * with suspend and resume. This includes data flow and control entry 111 * points alike. 112 * 113 * The audio framework guarantees that only one control is being 114 * accessed on any given audio device at a time. 115 * 116 * The audio framework guarantees that entry points are themselves 117 * serialized for a given engine. 118 * 119 * We have no interrupt routine or other internal asynchronous routines. 120 * 121 * Our device uses completely separate registers for each engine, 122 * except for the start/stop registers, which are implemented in a 123 * manner that allows for them to be accessed concurrently safely from 124 * different threads. 125 * 126 * Hence, it turns out that we simply don't need any locking in this 127 * driver. 128 */ 129 130#include <sys/modctl.h> 131#include <sys/kmem.h> 132#include <sys/pci.h> 133#include <sys/ddi.h> 134#include <sys/sunddi.h> 135#include <sys/debug.h> 136#include <sys/note.h> 137#include <sys/audio/audio_driver.h> 138#include <sys/audio/ac97.h> 139#include "audiots.h" 140 141/* 142 * Module linkage routines for the kernel 143 */ 144static int audiots_attach(dev_info_t *, ddi_attach_cmd_t); 145static int audiots_detach(dev_info_t *, ddi_detach_cmd_t); 146static int audiots_quiesce(dev_info_t *); 147 148/* 149 * Entry point routine prototypes 150 */ 151static int audiots_open(void *, int, unsigned *, caddr_t *); 152static void audiots_close(void *); 153static int audiots_start(void *); 154static void audiots_stop(void *); 155static int audiots_format(void *); 156static int audiots_channels(void *); 157static int audiots_rate(void *); 158static void audiots_chinfo(void *, int, unsigned *, unsigned *); 159static uint64_t audiots_count(void *); 160static void audiots_sync(void *, unsigned); 161 162static audio_engine_ops_t audiots_engine_ops = { 163 AUDIO_ENGINE_VERSION, 164 audiots_open, 165 audiots_close, 166 audiots_start, 167 audiots_stop, 168 audiots_count, 169 audiots_format, 170 audiots_channels, 171 audiots_rate, 172 audiots_sync, 173 NULL, 174 audiots_chinfo, 175 NULL, 176}; 177 178/* 179 * Local Routine Prototypes 180 */ 181static void audiots_power_up(audiots_state_t *); 182static void audiots_chip_init(audiots_state_t *); 183static uint16_t audiots_get_ac97(void *, uint8_t); 184static void audiots_set_ac97(void *, uint8_t, uint16_t); 185static int audiots_init_state(audiots_state_t *, dev_info_t *); 186static int audiots_map_regs(dev_info_t *, audiots_state_t *); 187static uint16_t audiots_read_ac97(audiots_state_t *, int); 188static void audiots_stop_everything(audiots_state_t *); 189static void audiots_destroy(audiots_state_t *); 190static int audiots_alloc_port(audiots_state_t *, int); 191 192/* 193 * Global variables, but viewable only by this file. 194 */ 195 196/* anchor for soft state structures */ 197static void *audiots_statep; 198 199/* 200 * DDI Structures 201 */ 202 203/* Device operations structure */ 204static struct dev_ops audiots_dev_ops = { 205 DEVO_REV, /* devo_rev */ 206 0, /* devo_refcnt */ 207 NULL, /* devo_getinfo */ 208 nulldev, /* devo_identify - obsolete */ 209 nulldev, /* devo_probe */ 210 audiots_attach, /* devo_attach */ 211 audiots_detach, /* devo_detach */ 212 nodev, /* devo_reset */ 213 NULL, /* devo_cb_ops */ 214 NULL, /* devo_bus_ops */ 215 NULL, /* devo_power */ 216 audiots_quiesce, /* devo_quiesce */ 217}; 218 219/* Linkage structure for loadable drivers */ 220static struct modldrv audiots_modldrv = { 221 &mod_driverops, /* drv_modops */ 222 TS_MOD_NAME, /* drv_linkinfo */ 223 &audiots_dev_ops /* drv_dev_ops */ 224}; 225 226/* Module linkage structure */ 227static struct modlinkage audiots_modlinkage = { 228 MODREV_1, /* ml_rev */ 229 (void *)&audiots_modldrv, /* ml_linkage */ 230 NULL /* NULL terminates the list */ 231}; 232 233 234/* 235 * NOTE: Grover OBP v4.0.166 and rev G of the ALI Southbridge chip force the 236 * audiots driver to use the upper 2 GB DMA address range. However to maintain 237 * backwards compatibility with older systems/OBP, we're going to try the full 238 * 4 GB DMA range. 239 * 240 * Eventually, this will be set back to using the proper high 2 GB DMA range. 241 */ 242 243/* Device attribute structure - full 4 gig address range */ 244static ddi_dma_attr_t audiots_attr = { 245 DMA_ATTR_VERSION, /* version */ 246 0x0000000000000000LL, /* dlim_addr_lo */ 247 0x00000000ffffffffLL, /* dlim_addr_hi */ 248 0x0000000000003fffLL, /* DMA counter register - 16 bits */ 249 0x0000000000000008LL, /* DMA address alignment, 64-bit */ 250 0x0000007f, /* 1 through 64 byte burst sizes */ 251 0x00000001, /* min effective DMA size */ 252 0x0000000000003fffLL, /* maximum transfer size, 16k */ 253 0x000000000000ffffLL, /* segment boundary, 64k */ 254 0x00000001, /* s/g list length, no s/g */ 255 0x00000001, /* granularity of device, don't care */ 256 0 /* DMA flags */ 257}; 258 259static ddi_device_acc_attr_t ts_acc_attr = { 260 DDI_DEVICE_ATTR_V0, 261 DDI_NEVERSWAP_ACC, 262 DDI_STRICTORDER_ACC 263}; 264 265static ddi_device_acc_attr_t ts_regs_attr = { 266 DDI_DEVICE_ATTR_V0, 267 DDI_STRUCTURE_LE_ACC, 268 DDI_STRICTORDER_ACC 269}; 270 271/* 272 * _init() 273 * 274 * Description: 275 * Driver initialization, called when driver is first loaded. 276 * This is how access is initially given to all the static structures. 277 * 278 * Arguments: 279 * None 280 * 281 * Returns: 282 * ddi_soft_state_init() status, see ddi_soft_state_init(9f), or 283 * mod_install() status, see mod_install(9f) 284 */ 285int 286_init(void) 287{ 288 int error; 289 290 audio_init_ops(&audiots_dev_ops, TS_NAME); 291 292 /* initialize the soft state */ 293 if ((error = ddi_soft_state_init(&audiots_statep, 294 sizeof (audiots_state_t), 1)) != 0) { 295 audio_fini_ops(&audiots_dev_ops); 296 return (error); 297 } 298 299 if ((error = mod_install(&audiots_modlinkage)) != 0) { 300 audio_fini_ops(&audiots_dev_ops); 301 ddi_soft_state_fini(&audiots_statep); 302 } 303 304 return (error); 305} 306 307/* 308 * _fini() 309 * 310 * Description: 311 * Module de-initialization, called when the driver is to be unloaded. 312 * 313 * Arguments: 314 * None 315 * 316 * Returns: 317 * mod_remove() status, see mod_remove(9f) 318 */ 319int 320_fini(void) 321{ 322 int error; 323 324 if ((error = mod_remove(&audiots_modlinkage)) != 0) { 325 return (error); 326 } 327 328 /* free the soft state internal structures */ 329 ddi_soft_state_fini(&audiots_statep); 330 331 /* clean up ops */ 332 audio_fini_ops(&audiots_dev_ops); 333 334 return (0); 335} 336 337/* 338 * _info() 339 * 340 * Description: 341 * Module information, returns infomation about the driver. 342 * 343 * Arguments: 344 * modinfo *modinfop Pointer to the opaque modinfo structure 345 * 346 * Returns: 347 * mod_info() status, see mod_info(9f) 348 */ 349int 350_info(struct modinfo *modinfop) 351{ 352 int error; 353 354 error = mod_info(&audiots_modlinkage, modinfop); 355 356 return (error); 357} 358 359 360/* 361 * audiots_attach() 362 * 363 * Description: 364 * Attach an instance of the audiots driver. This routine does the 365 * device dependent attach tasks. 366 * 367 * Arguments: 368 * dev_info_t *dip Pointer to the device's dev_info struct 369 * ddi_attach_cmd_t cmd Attach command 370 * 371 * Returns: 372 * DDI_SUCCESS The driver was initialized properly 373 * DDI_FAILURE The driver couldn't be initialized properly 374 */ 375static int 376audiots_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 377{ 378 audiots_state_t *state; 379 int instance; 380 381 instance = ddi_get_instance(dip); 382 383 switch (cmd) { 384 case DDI_ATTACH: 385 break; 386 case DDI_RESUME: 387 388 /* we've already allocated the state structure so get ptr */ 389 state = ddi_get_soft_state(audiots_statep, instance); 390 ASSERT(dip == state->ts_dip); 391 392 /* suspend/resume resets the chip, so we have no more faults */ 393 if (state->ts_flags & TS_AUDIO_READ_FAILED) { 394 ddi_dev_report_fault(state->ts_dip, 395 DDI_SERVICE_RESTORED, 396 DDI_DEVICE_FAULT, 397 "check port, gain, balance, and mute settings"); 398 /* and clear the fault state flags */ 399 state->ts_flags &= 400 ~(TS_AUDIO_READ_FAILED|TS_READ_FAILURE_PRINTED); 401 } 402 403 audiots_power_up(state); 404 audiots_chip_init(state); 405 406 ac97_reset(state->ts_ac97); 407 408 audio_dev_resume(state->ts_adev); 409 410 return (DDI_SUCCESS); 411 412 default: 413 return (DDI_FAILURE); 414 } 415 416 /* before we do anything make sure that we haven't had a h/w failure */ 417 if (ddi_get_devstate(dip) == DDI_DEVSTATE_DOWN) { 418 cmn_err(CE_WARN, "%s%d: The audio hardware has " 419 "been disabled.", ddi_driver_name(dip), instance); 420 cmn_err(CE_CONT, "Please reboot to restore audio."); 421 return (DDI_FAILURE); 422 } 423 424 /* allocate the state structure */ 425 if (ddi_soft_state_zalloc(audiots_statep, instance) == DDI_FAILURE) { 426 cmn_err(CE_WARN, "!%s%d: soft state allocate failed", 427 ddi_driver_name(dip), instance); 428 return (DDI_FAILURE); 429 } 430 431 /* 432 * WARNING: From here on all errors require that we free memory, 433 * including the state structure. 434 */ 435 436 /* get the state structure - cannot fail */ 437 state = ddi_get_soft_state(audiots_statep, instance); 438 ASSERT(state != NULL); 439 440 if ((state->ts_adev = audio_dev_alloc(dip, 0)) == NULL) { 441 cmn_err(CE_WARN, "unable to allocate audio dev"); 442 goto error; 443 } 444 445 /* map in the registers, allocate DMA buffers, etc. */ 446 if (audiots_map_regs(dip, state) == DDI_FAILURE) { 447 audio_dev_warn(state->ts_adev, "unable to map registers"); 448 goto error; 449 } 450 451 /* initialize the audio state structures */ 452 if (audiots_init_state(state, dip) == DDI_FAILURE) { 453 audio_dev_warn(state->ts_adev, "init state structure failed"); 454 goto error; 455 } 456 457 /* power up */ 458 audiots_power_up(state); 459 460 /* initialize the audio controller */ 461 audiots_chip_init(state); 462 463 /* initialize the AC-97 Codec */ 464 if (ac97_init(state->ts_ac97, state->ts_adev) != 0) { 465 goto error; 466 } 467 468 /* put the engine interrupts into a known state -- all off */ 469 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten, 470 TS_ALL_DMA_OFF); 471 472 /* call the framework attach routine */ 473 if (audio_dev_register(state->ts_adev) != DDI_SUCCESS) { 474 audio_dev_warn(state->ts_adev, "unable to register audio"); 475 goto error; 476 } 477 478 /* everything worked out, so report the device */ 479 ddi_report_dev(dip); 480 481 return (DDI_SUCCESS); 482 483error: 484 audiots_destroy(state); 485 return (DDI_FAILURE); 486} 487 488/* 489 * audiots_detach() 490 * 491 * Description: 492 * Detach an instance of the audiots driver. 493 * 494 * Arguments: 495 * dev_info_t *dip Pointer to the device's dev_info struct 496 * ddi_detach_cmd_t cmd Detach command 497 * 498 * Returns: 499 * DDI_SUCCESS The driver was detached 500 * DDI_FAILURE The driver couldn't be detached 501 */ 502static int 503audiots_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 504{ 505 audiots_state_t *state; 506 int instance; 507 508 instance = ddi_get_instance(dip); 509 510 /* get the state structure */ 511 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) { 512 cmn_err(CE_WARN, "!%s%d: detach get soft state failed", 513 ddi_driver_name(dip), instance); 514 return (DDI_FAILURE); 515 } 516 517 switch (cmd) { 518 case DDI_DETACH: 519 break; 520 case DDI_SUSPEND: 521 522 audio_dev_suspend(state->ts_adev); 523 524 /* stop playing and recording */ 525 (void) audiots_stop_everything(state); 526 527 return (DDI_SUCCESS); 528 529 default: 530 return (DDI_FAILURE); 531 } 532 533 /* attempt to unregister from the framework first */ 534 if (audio_dev_unregister(state->ts_adev) != DDI_SUCCESS) { 535 return (DDI_FAILURE); 536 } 537 538 audiots_destroy(state); 539 540 return (DDI_SUCCESS); 541 542} 543 544/* 545 * audiots_quiesce() 546 * 547 * Description: 548 * Quiesce an instance of the audiots driver. Stops all DMA and 549 * interrupts. 550 * 551 * Arguments: 552 * dev_info_t *dip Pointer to the device's dev_info struct 553 * 554 * Returns: 555 * DDI_SUCCESS The driver was quiesced 556 * DDI_SUCCESS The driver was NOT quiesced 557 */ 558static int 559audiots_quiesce(dev_info_t *dip) 560{ 561 audiots_state_t *state; 562 int instance; 563 564 instance = ddi_get_instance(dip); 565 566 /* get the state structure */ 567 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) { 568 return (DDI_FAILURE); 569 } 570 571 audiots_stop_everything(state); 572 573 return (DDI_SUCCESS); 574} 575 576/* 577 * audiots_power_up() 578 * 579 * Description 580 * Ensure that the device is running in PCI power state D0. 581 */ 582static void 583audiots_power_up(audiots_state_t *state) 584{ 585 ddi_acc_handle_t pcih = state->ts_pcih; 586 uint8_t ptr; 587 uint16_t pmcsr; 588 589 if ((pci_config_get16(pcih, PCI_CONF_STAT) & PCI_STAT_CAP) == 0) { 590 /* does not implement PCI capabilities -- no PM */ 591 return; 592 } 593 594 ptr = pci_config_get8(pcih, PCI_CONF_CAP_PTR); 595 for (;;) { 596 if (ptr == PCI_CAP_NEXT_PTR_NULL) { 597 /* PM capability not found */ 598 return; 599 } 600 if (pci_config_get8(pcih, ptr + PCI_CAP_ID) == PCI_CAP_ID_PM) { 601 /* found it */ 602 break; 603 } 604 ptr = pci_config_get8(pcih, ptr + PCI_CAP_NEXT_PTR); 605 } 606 607 /* if we got here, then got valid PMCSR pointer */ 608 ptr += PCI_PMCSR; 609 610 /* check to see if we are already in state D0 */ 611 pmcsr = pci_config_get16(pcih, ptr); 612 if ((pmcsr & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 613 614 /* D3hot (or any other state) -> D0 */ 615 pmcsr &= ~PCI_PMCSR_STATE_MASK; 616 pmcsr |= PCI_PMCSR_D0; 617 pci_config_put16(pcih, ptr, pmcsr); 618 } 619 620 /* 621 * Wait for it to power up - PCI spec says 10 ms is enough. 622 * We double it. Note that no locks are held when this routine 623 * is called, so we can sleep (we are in attach context only). 624 * 625 * We do this delay even if already powerd up, just to make 626 * sure we aren't seeing something that *just* transitioned 627 * into D0 state. 628 */ 629 delay(drv_usectohz(TS_20MS)); 630 631 /* clear PME# flag */ 632 pmcsr = pci_config_get16(pcih, ptr); 633 pci_config_put16(pcih, ptr, pmcsr | PCI_PMCSR_PME_STAT); 634} 635 636/* 637 * audiots_chip_init() 638 * 639 * Description: 640 * Initialize the audio core. 641 * 642 * Arguments: 643 * audiots_state_t *state The device's state structure 644 */ 645static void 646audiots_chip_init(audiots_state_t *state) 647{ 648 ddi_acc_handle_t handle = state->ts_acch; 649 audiots_regs_t *regs = state->ts_regs; 650 int str; 651 652 /* start with all interrupts & dma channels disabled */ 653 ddi_put32(handle, ®s->aud_regs.ap_stop, TS_ALL_DMA_ENGINES); 654 ddi_put32(handle, ®s->aud_regs.ap_ainten, TS_ALL_DMA_OFF); 655 656 /* set global music and wave volume to 0dB */ 657 ddi_put32(handle, ®s->aud_regs.ap_volume, 0x0); 658 659 /* enable end interrupts for all channels. */ 660 ddi_put32(handle, ®s->aud_regs.ap_cir_gc, AP_CIR_GC_ENDLP_IE); 661 662 /* for each stream, set gain and vol settings */ 663 for (str = 0; str < TS_MAX_HW_CHANNELS; str++) { 664 /* 665 * Set volume to all off, 1st left and then right. 666 * These are never changed, so we don't have to save them. 667 */ 668 ddi_put16(handle, 669 ®s->aud_ram[str].eram.eram_gvsel_pan_vol, 670 (ERAM_WAVE_VOL|ERAM_PAN_LEFT|ERAM_PAN_0dB| 671 ERAM_VOL_MAX_ATTEN)); 672 ddi_put16(handle, 673 ®s->aud_ram[str].eram.eram_gvsel_pan_vol, 674 (ERAM_WAVE_VOL|ERAM_PAN_RIGHT|ERAM_PAN_0dB| 675 ERAM_VOL_MAX_ATTEN)); 676 677 /* 678 * The envelope engine *MUST* remain in still mode (off). 679 * Otherwise bad things like gain randomly disappearing might 680 * happen. See bug #4332773. 681 */ 682 683 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf1, 684 ERAM_EBUF_STILL); 685 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf2, 686 ERAM_EBUF_STILL); 687 688 /* program the initial eram and aram rate */ 689 ddi_put16(handle, ®s->aud_ram[str].aram.aram_delta, 690 1 << TS_SRC_SHIFT); 691 ddi_put16(handle, ®s->aud_ram[str].eram.eram_ctrl_ec, 692 ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE | 693 ERAM_SIGNED_PCM); 694 } 695 696 /* program channel 31 for record */ 697 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_global_control, 698 (AP_CLOGAL_CTRL_E_PCMIN_CH31|AP_CLOGAL_CTRL_PCM_OUT_AC97| 699 AP_CLOGAL_CTRL_MMC_FROM_MIXER|AP_CLOGAL_CTRL_PCM_OUT_TO_AC97)); 700 701 /* do a warm reset, which powers up the Codec */ 702 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl, 703 AP_SCTRL_WRST_CODEC); 704 drv_usecwait(2); 705 AND_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl, 706 ~AP_SCTRL_WRST_CODEC); 707 708 /* do a warm reset via the Codec, yes, I'm being paranoid! */ 709 audiots_set_ac97(state, AC97_RESET_REGISTER, 0); 710 711 /* Make sure the Codec is powered up. */ 712 int i = TS_WAIT_CNT; 713 while ((audiots_get_ac97(state, AC97_POWERDOWN_CTRL_STAT_REGISTER) & 714 PCSR_POWERD_UP) != PCSR_POWERD_UP && i--) { 715 drv_usecwait(1); 716 } 717 718} 719 720/* 721 * audiots_get_ac97() 722 * 723 * Description: 724 * Get the value in the specified AC-97 Codec register. There is a 725 * bug in silicon which forces us to do multiple reads of the Codec's 726 * register. This algorithm was provided by T2 and is heuristic in 727 * nature. Unfortunately we have no guarantees that the real answer 728 * isn't 0x0000, which is what we get when a read fails. So we loop 729 * TS_LOOP_CNT times before we give up. We just have to hope this is 730 * sufficient to give us the correct value. 731 * 732 * Arguments: 733 * audiots_state_t *state The device's state structure 734 * int reg AC-97 register number 735 * 736 * Returns: 737 * unsigned short The value in the specified register 738 */ 739static uint16_t 740audiots_get_ac97(void *arg, uint8_t reg) 741{ 742 audiots_state_t *state = arg; 743 ddi_acc_handle_t handle = state->ts_acch; 744 uint16_t *data; 745 int count; 746 int delay; 747 uint16_t first; 748 uint16_t next; 749 750 if (state->ts_revid == AC_REV_ID1) { 751 data = &state->ts_regs->aud_regs.ap_acrd_35D_data; 752 } else { 753 data = &state->ts_regs->aud_regs.ap_acrdwr_data; 754 } 755 756 /* make sure the register is good */ 757 reg &= AP_ACRD_INDEX_MASK; 758 for (count = TS_LOOP_CNT; count--; ) { 759 if ((first = audiots_read_ac97(state, reg)) != 0) { 760 next = first; 761 break; 762 } 763 764 delay = TS_DELAY_CNT; 765 while (delay--) { 766 (void) ddi_get16(handle, data); 767 } 768 769 if ((next = audiots_read_ac97(state, reg)) != 0) { 770 break; 771 } 772 } 773 774 /* 775 * Arggg, if you let the next read happen too soon then it fails. 776 * 12 usec fails, 13 usec succeeds. So set it to 20 for safety. 777 */ 778 drv_usecwait(TS_20US); 779 780 return (next); 781 782} 783 784/* 785 * audiots_init_state() 786 * 787 * Description: 788 * This routine initializes the audio driver's state structure. 789 * This includes reading the properties. 790 * 791 * CAUTION: This routine cannot allocate resources, unless it frees 792 * them before returning for an error. Also, error_destroy: 793 * in audiots_attach() would need to be fixed as well. 794 * 795 * NOTE: birdsnest supports CD ROM input. We check for the cdrom 796 * property. If there we turn it on. 797 * 798 * Arguments: 799 * audiots_state_t *state The device's state structure 800 * dev_info_t *dip Pointer to the device's dev_info struct 801 * 802 * Returns: 803 * DDI_SUCCESS State structure initialized 804 * DDI_FAILURE State structure not initialized 805 */ 806static int 807audiots_init_state(audiots_state_t *state, dev_info_t *dip) 808{ 809 state->ts_ac97 = ac97_alloc(dip, audiots_get_ac97, 810 audiots_set_ac97, state); 811 812 if (state->ts_ac97 == NULL) { 813 return (DDI_FAILURE); 814 } 815 816 /* save the device info pointer */ 817 state->ts_dip = dip; 818 819 for (int i = 0; i < TS_NUM_PORTS; i++) { 820 if (audiots_alloc_port(state, i) != DDI_SUCCESS) { 821 return (DDI_FAILURE); 822 } 823 } 824 825 return (DDI_SUCCESS); 826 827} 828 829/* 830 * audiots_map_regs() 831 * 832 * Description: 833 * This routine maps the registers in. 834 * 835 * Once the config space registers are mapped in we determine if the 836 * audio core may be power managed. It should, but if it doesn't, 837 * then trying to may cause the core to hang. 838 * 839 * CAUTION: Make sure all errors call audio_dev_warn(). 840 * 841 * Arguments: 842 * dev_info_t *dip Pointer to the device's devinfo 843 * audiots_state_t *state The device's state structure 844 * Returns: 845 * DDI_SUCCESS Registers successfully mapped 846 * DDI_FAILURE Registers not successfully mapped 847 */ 848static int 849audiots_map_regs(dev_info_t *dip, audiots_state_t *state) 850{ 851 char rev[16]; 852 char *name; 853 854 /* map in the registers, the config and memory mapped registers */ 855 if (pci_config_setup(dip, &state->ts_pcih) != DDI_SUCCESS) { 856 audio_dev_warn(state->ts_adev, 857 "unable to map PCI configuration space"); 858 return (DDI_FAILURE); 859 } 860 861 /* Read the Audio Controller's vendor, device, and revision IDs */ 862 state->ts_devid = 863 (pci_config_get16(state->ts_pcih, PCI_CONF_VENID) << 16) | 864 pci_config_get16(state->ts_pcih, PCI_CONF_DEVID); 865 state->ts_revid = pci_config_get8(state->ts_pcih, PCI_CONF_REVID); 866 867 if (ddi_regs_map_setup(dip, TS_MEM_MAPPED_REGS, 868 (caddr_t *)&state->ts_regs, 0, 0, &ts_regs_attr, &state->ts_acch) != 869 DDI_SUCCESS) { 870 audio_dev_warn(state->ts_adev, 871 "unable to map PCI device registers"); 872 return (DDI_FAILURE); 873 } 874 875 switch (state->ts_devid) { 876 case 0x10b95451: 877 name = "ALI M5451"; 878 break; 879 default: 880 name = "audiots"; 881 break; 882 } 883 (void) snprintf(rev, sizeof (rev), "Rev %x", state->ts_revid); 884 audio_dev_set_description(state->ts_adev, name); 885 audio_dev_set_version(state->ts_adev, rev); 886 887 return (DDI_SUCCESS); 888} 889 890/* 891 * audiots_alloc_port() 892 * 893 * Description: 894 * This routine allocates the DMA handles and the memory for the 895 * DMA engines to use. It then binds each of the buffers to its 896 * respective handle, getting a DMA cookie. 897 * 898 * NOTE: All of the ddi_dma_... routines sleep if they cannot get 899 * memory. This means these calls should always succeed. 900 * 901 * NOTE: ddi_dma_alloc_handle() attempts to use the full 4 GB DMA address 902 * range. This is to work around Southbridge rev E/G OBP issues. 903 * (See Grover OBP note above) 904 * 905 * CAUTION: Make sure all errors call audio_dev_warn(). 906 * 907 * Arguments: 908 * audiots_port_t *state The port structure for a device stream 909 * int num The port number 910 * 911 * Returns: 912 * DDI_SUCCESS DMA resources mapped 913 * DDI_FAILURE DMA resources not successfully mapped 914 */ 915int 916audiots_alloc_port(audiots_state_t *state, int num) 917{ 918 audiots_port_t *port; 919 dev_info_t *dip = state->ts_dip; 920 audio_dev_t *adev = state->ts_adev; 921 int dir; 922 unsigned caps; 923 ddi_dma_cookie_t cookie; 924 unsigned count; 925 int rc; 926 ddi_acc_handle_t regsh = state->ts_acch; 927 uint32_t *gcptr = &state->ts_regs->aud_regs.ap_cir_gc; 928 929 port = kmem_zalloc(sizeof (*port), KM_SLEEP); 930 state->ts_ports[num] = port; 931 port->tp_num = num; 932 port->tp_state = state; 933 port->tp_rate = TS_RATE; 934 935 if (num == TS_INPUT_PORT) { 936 dir = DDI_DMA_READ; 937 caps = ENGINE_INPUT_CAP; 938 port->tp_dma_stream = 31; 939 port->tp_sync_dir = DDI_DMA_SYNC_FORKERNEL; 940 } else { 941 dir = DDI_DMA_WRITE; 942 caps = ENGINE_OUTPUT_CAP; 943 port->tp_dma_stream = 0; 944 port->tp_sync_dir = DDI_DMA_SYNC_FORDEV; 945 } 946 947 port->tp_dma_mask = (1U << port->tp_dma_stream); 948 port->tp_nframes = 4096; 949 port->tp_size = port->tp_nframes * TS_FRAMESZ; 950 951 /* allocate dma handle */ 952 rc = ddi_dma_alloc_handle(dip, &audiots_attr, DDI_DMA_SLEEP, 953 NULL, &port->tp_dmah); 954 if (rc != DDI_SUCCESS) { 955 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc); 956 return (DDI_FAILURE); 957 } 958 /* allocate DMA buffer */ 959 rc = ddi_dma_mem_alloc(port->tp_dmah, port->tp_size, &ts_acc_attr, 960 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->tp_kaddr, 961 &port->tp_size, &port->tp_acch); 962 if (rc == DDI_FAILURE) { 963 audio_dev_warn(adev, "dma_mem_alloc failed"); 964 return (DDI_FAILURE); 965 } 966 967 /* bind DMA buffer */ 968 rc = ddi_dma_addr_bind_handle(port->tp_dmah, NULL, 969 port->tp_kaddr, port->tp_size, dir|DDI_DMA_CONSISTENT, 970 DDI_DMA_SLEEP, NULL, &cookie, &count); 971 if (rc != DDI_DMA_MAPPED) { 972 audio_dev_warn(adev, 973 "ddi_dma_addr_bind_handle failed: %d", rc); 974 return (DDI_FAILURE); 975 } 976 ASSERT(count == 1); 977 978 port->tp_paddr = cookie.dmac_address; 979 if ((unsigned)port->tp_paddr & 0x80000000U) { 980 ddi_put32(regsh, gcptr, 981 ddi_get32(regsh, gcptr) | AP_CIR_GC_SYS_MEM_4G_ENABLE); 982 } else { 983 ddi_put32(regsh, gcptr, 984 ddi_get32(regsh, gcptr) & ~(AP_CIR_GC_SYS_MEM_4G_ENABLE)); 985 } 986 port->tp_engine = audio_engine_alloc(&audiots_engine_ops, caps); 987 if (port->tp_engine == NULL) { 988 audio_dev_warn(adev, "audio_engine_alloc failed"); 989 return (DDI_FAILURE); 990 } 991 992 audio_engine_set_private(port->tp_engine, port); 993 audio_dev_add_engine(adev, port->tp_engine); 994 995 return (DDI_SUCCESS); 996} 997 998/* 999 * audiots_read_ac97() 1000 * 1001 * Description: 1002 * This routine actually reads the AC-97 Codec's register. It may 1003 * be called several times to succeed. 1004 * 1005 * NOTE: 1006 * Revision M1535D B1-C of the ALI SouthBridge includes a workaround for 1007 * the broken busy flag. Resetting the busy flag requires a software tweak 1008 * to go with the worked around hardware. When we detect failure, we make 1009 * 10 attempts to reset the chip before we fail. This should reset the new 1010 * SB systems. On all SB systems, this will increse the read delay 1011 * slightly, but shouldn't bother it otherwise. 1012 * 1013 * Arguments: 1014 * audiots_state_t *state The device's state structure 1015 * int reg AC-97 register number 1016 * 1017 * Returns: 1018 * unsigned short The value in the specified register 1019 */ 1020static uint16_t 1021audiots_read_ac97(audiots_state_t *state, int reg) 1022{ 1023 ddi_acc_handle_t acch = state->ts_acch; 1024 uint16_t *addr; 1025 uint16_t *data; 1026 uint32_t *stimer = &state->ts_regs->aud_regs.ap_stimer; 1027 uint32_t chk1; 1028 uint32_t chk2; 1029 int resets = 0; 1030 int i; 1031 1032 if (state->ts_revid == AC_REV_ID1) { 1033 addr = &state->ts_regs->aud_regs.ap_acrd_35D_reg; 1034 data = &state->ts_regs->aud_regs.ap_acrd_35D_data; 1035 } else { 1036 addr = &state->ts_regs->aud_regs.ap_acrdwr_reg; 1037 data = &state->ts_regs->aud_regs.ap_acrdwr_data; 1038 } 1039 1040first_read: 1041 /* wait for ready to send read request */ 1042 for (i = 0; i < TS_READ_TRIES; i++) { 1043 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) { 1044 break; 1045 } 1046 /* don't beat on the bus */ 1047 drv_usecwait(1); 1048 } 1049 if (i >= TS_READ_TRIES) { 1050 if (resets < TS_RESET_TRIES) { 1051 /* Attempt to reset */ 1052 drv_usecwait(TS_20US); 1053 ddi_put16(acch, addr, TS_SB_RESET); 1054 resets++; 1055 goto first_read; 1056 } else { 1057 state->ts_flags |= TS_AUDIO_READ_FAILED; 1058 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) { 1059 ddi_dev_report_fault(state->ts_dip, 1060 DDI_SERVICE_LOST, DDI_DEVICE_FAULT, 1061 "Unable to communicate with AC97 CODEC"); 1062 audio_dev_warn(state->ts_adev, 1063 "The audio AC97 register has timed out."); 1064 audio_dev_warn(state->ts_adev, 1065 "Audio is now disabled."); 1066 audio_dev_warn(state->ts_adev, 1067 "Please reboot to restore audio."); 1068 1069 /* Don't flood the console */ 1070 state->ts_flags |= TS_READ_FAILURE_PRINTED; 1071 } 1072 } 1073 return (0); 1074 } 1075 1076 /* program the register to read */ 1077 ddi_put16(acch, addr, (reg|AP_ACRD_W_PRIMARY_CODEC| 1078 AP_ACRD_W_READ_MIXER_REG|AP_ACRD_W_AUDIO_READ_REQ& 1079 (~AP_ACWR_W_SELECT_WRITE))); 1080 1081 /* hardware bug work around */ 1082 chk1 = ddi_get32(acch, stimer); 1083 chk2 = ddi_get32(acch, stimer); 1084 i = TS_WAIT_CNT; 1085 while (chk1 == chk2 && i) { 1086 chk2 = ddi_get32(acch, stimer); 1087 i--; 1088 } 1089 OR_SET_SHORT(acch, addr, AP_ACRD_W_READ_MIXER_REG); 1090 resets = 0; 1091 1092second_read: 1093 /* wait again for read to send read request */ 1094 for (i = 0; i < TS_READ_TRIES; i++) { 1095 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) { 1096 break; 1097 } 1098 /* don't beat on the bus */ 1099 drv_usecwait(1); 1100 } 1101 if (i >= TS_READ_TRIES) { 1102 if (resets < TS_RESET_TRIES) { 1103 /* Attempt to reset */ 1104 drv_usecwait(TS_20US); 1105 ddi_put16(acch, addr, TS_SB_RESET); 1106 resets++; 1107 goto second_read; 1108 } else { 1109 state->ts_flags |= TS_AUDIO_READ_FAILED; 1110 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) { 1111 ddi_dev_report_fault(state->ts_dip, 1112 DDI_SERVICE_LOST, DDI_DEVICE_FAULT, 1113 "Unable to communicate with AC97 CODEC"); 1114 audio_dev_warn(state->ts_adev, 1115 "The audio AC97 register has timed out."); 1116 audio_dev_warn(state->ts_adev, 1117 "Audio is now disabled."); 1118 audio_dev_warn(state->ts_adev, 1119 "Please reboot to restore audio."); 1120 1121 /* Don't flood the console */ 1122 state->ts_flags |= TS_READ_FAILURE_PRINTED; 1123 } 1124 } 1125 return (0); 1126 } 1127 1128 return (ddi_get16(acch, data)); 1129 1130} /* audiots_read_ac97() */ 1131 1132/* 1133 * audiots_set_ac97() 1134 * 1135 * Description: 1136 * Set the value in the specified AC-97 Codec register. Just like 1137 * reading the AC-97 Codec, it is possible there is a problem writing 1138 * it as well. So we loop. 1139 * 1140 * Arguments: 1141 * audiots_state_t *state The device's state structure 1142 * int reg AC-97 register number 1143 * uint16_t value The value to write 1144 */ 1145static void 1146audiots_set_ac97(void *arg, uint8_t reg8, uint16_t data) 1147{ 1148 audiots_state_t *state = arg; 1149 ddi_acc_handle_t handle = state->ts_acch; 1150 uint16_t *data_addr = &state->ts_regs->aud_regs.ap_acrdwr_data; 1151 uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg; 1152 int count; 1153 int i; 1154 uint16_t tmp_short; 1155 uint16_t reg = reg8; 1156 1157 reg &= AP_ACWR_INDEX_MASK; 1158 1159 /* Don't touch the reserved bits on the pre 35D+ SouthBridge */ 1160 if (state->ts_revid == AC_REV_ID1) { 1161 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG; 1162 } else { 1163 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG| 1164 AP_ACWR_W_SELECT_WRITE; 1165 } 1166 1167 for (count = TS_LOOP_CNT; count--; ) { 1168 /* wait for ready to write */ 1169 for (i = 0; i < TS_WAIT_CNT; i++) { 1170 if (!(ddi_get16(handle, reg_addr) & 1171 AP_ACWR_R_WRITE_BUSY)) { 1172 /* ready to write */ 1173 ddi_put16(handle, reg_addr, reg); 1174 1175 /* Write the data */ 1176 ddi_put16(handle, data_addr, data); 1177 break; 1178 } 1179 } 1180 if (i >= TS_WAIT_CNT) { 1181 /* try again */ 1182 continue; 1183 } 1184 1185 /* wait for write to complete */ 1186 for (i = 0; i < TS_WAIT_CNT; i++) { 1187 if (!(ddi_get16(handle, reg_addr) & 1188 AP_ACWR_R_WRITE_BUSY)) { 1189 /* done writing */ 1190 break; 1191 } 1192 } 1193 1194 /* verify the value written */ 1195 tmp_short = audiots_get_ac97(state, reg8); 1196 if (data == tmp_short) { 1197 /* successfully loaded, so we can return */ 1198 return; 1199 } 1200 } 1201 1202} /* audiots_set_ac97() */ 1203 1204/* 1205 * audiots_open() 1206 * 1207 * Description: 1208 * Opens a DMA engine for use. Will also ensure the device is powered 1209 * up if not already done so. 1210 * 1211 * Arguments: 1212 * void *arg The DMA engine to set up 1213 * int flag Open flags 1214 * unsigned *nframesp Receives number of frames 1215 * caddr_t *bufp Receives kernel data buffer 1216 * 1217 * Returns: 1218 * 0 on success 1219 * errno on failure 1220 */ 1221static int 1222audiots_open(void *arg, int flag, unsigned *nframesp, caddr_t *bufp) 1223{ 1224 audiots_port_t *port = arg; 1225 1226 _NOTE(ARGUNUSED(flag)); 1227 1228 port->tp_count = 0; 1229 port->tp_cso = 0; 1230 *nframesp = port->tp_nframes; 1231 *bufp = port->tp_kaddr; 1232 1233 return (0); 1234} 1235 1236/* 1237 * audiots_close() 1238 * 1239 * Description: 1240 * Closes an audio DMA engine that was previously opened. Since 1241 * nobody is using it, we could take this opportunity to possibly power 1242 * down the entire device, or at least the DMA engine. 1243 * 1244 * Arguments: 1245 * void *arg The DMA engine to shut down 1246 */ 1247static void 1248audiots_close(void *arg) 1249{ 1250 _NOTE(ARGUNUSED(arg)); 1251} 1252 1253/* 1254 * audiots_stop() 1255 * 1256 * Description: 1257 * This is called by the framework to stop a port that is 1258 * transferring data. 1259 * 1260 * Arguments: 1261 * void *arg The DMA engine to stop 1262 */ 1263static void 1264audiots_stop(void *arg) 1265{ 1266 audiots_port_t *port = arg; 1267 audiots_state_t *state = port->tp_state; 1268 1269 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop, 1270 port->tp_dma_mask); 1271} 1272 1273/* 1274 * audiots_start() 1275 * 1276 * Description: 1277 * This is called by the framework to start a port transferring data. 1278 * 1279 * Arguments: 1280 * void *arg The DMA engine to start 1281 * 1282 * Returns: 1283 * 0 on success (never fails, errno if it did) 1284 */ 1285static int 1286audiots_start(void *arg) 1287{ 1288 audiots_port_t *port = arg; 1289 audiots_state_t *state = port->tp_state; 1290 ddi_acc_handle_t handle = state->ts_acch; 1291 audiots_regs_t *regs = state->ts_regs; 1292 audiots_aram_t *aram; 1293 audiots_eram_t *eram; 1294 unsigned delta; 1295 uint16_t ctrl; 1296 uint16_t gvsel; 1297 uint16_t eso; 1298 1299 aram = ®s->aud_ram[port->tp_dma_stream].aram; 1300 eram = ®s->aud_ram[port->tp_dma_stream].eram; 1301 1302 port->tp_cso = 0; 1303 1304 gvsel = ERAM_WAVE_VOL | ERAM_PAN_0dB | ERAM_VOL_DEFAULT; 1305 ctrl = ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE | ERAM_SIGNED_PCM; 1306 1307 delta = (port->tp_rate << TS_SRC_SHIFT) / TS_RATE; 1308 1309 if (port->tp_num == TS_INPUT_PORT) { 1310 delta = (TS_RATE << TS_SRC_SHIFT) / port->tp_rate; 1311 } 1312 eso = port->tp_nframes - 1; 1313 1314 /* program the sample rate */ 1315 ddi_put16(handle, &aram->aram_delta, (uint16_t)delta); 1316 1317 /* program the precision, number of channels and loop mode */ 1318 ddi_put16(handle, &eram->eram_ctrl_ec, ctrl); 1319 1320 /* program the volume settings */ 1321 ddi_put16(handle, &eram->eram_gvsel_pan_vol, gvsel); 1322 1323 /* set ALPHA and FMS to 0 */ 1324 ddi_put16(handle, &aram->aram_alpha_fms, 0x0); 1325 1326 /* set CSO to 0 */ 1327 ddi_put16(handle, &aram->aram_cso, 0x0); 1328 1329 /* set LBA */ 1330 ddi_put32(handle, &aram->aram_cptr_lba, 1331 port->tp_paddr & ARAM_LBA_MASK); 1332 1333 /* set ESO */ 1334 ddi_put16(handle, &aram->aram_eso, eso); 1335 1336 /* stop the DMA engines */ 1337 ddi_put32(handle, ®s->aud_regs.ap_stop, port->tp_dma_mask); 1338 1339 /* now make sure it starts playing */ 1340 ddi_put32(handle, ®s->aud_regs.ap_start, port->tp_dma_mask); 1341 1342 return (0); 1343} 1344 1345/* 1346 * audiots_chinfo() 1347 * 1348 * Description: 1349 * This is called by the framework to query the channel offsets 1350 * and ordering. 1351 * 1352 * Arguments: 1353 * void *arg The DMA engine to query 1354 * int chan Channel number. 1355 * unsigned *offset Starting offset of channel. 1356 * unsigned *incr Increment (in samples) between frames. 1357 * 1358 * Returns: 1359 * 0 indicating rate array is range instead of enumeration 1360 */ 1361 1362static void 1363audiots_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 1364{ 1365 _NOTE(ARGUNUSED(arg)); 1366 *offset = chan; 1367 *incr = 2; 1368} 1369 1370/* 1371 * audiots_format() 1372 * 1373 * Description: 1374 * Called by the framework to query the format for the device. 1375 * 1376 * Arguments: 1377 * void *arg The DMA engine to query 1378 * 1379 * Returns: 1380 * AUDIO_FORMAT_S16_LE. 1381 */ 1382static int 1383audiots_format(void *arg) 1384{ 1385 _NOTE(ARGUNUSED(arg)); 1386 1387 return (AUDIO_FORMAT_S16_LE); 1388} 1389 1390 1391/* 1392 * audiots_channels() 1393 * 1394 * Description: 1395 * Called by the framework to query the channnels for the device. 1396 * 1397 * Arguments: 1398 * void *arg The DMA engine to query 1399 * 1400 * Returns: 1401 * 2 (Stereo). 1402 */ 1403static int 1404audiots_channels(void *arg) 1405{ 1406 _NOTE(ARGUNUSED(arg)); 1407 1408 return (2); 1409} 1410 1411/* 1412 * audiots_rate() 1413 * 1414 * Description: 1415 * Called by the framework to query the sample rates for the device. 1416 * 1417 * Arguments: 1418 * void *arg The DMA engine to query 1419 * 1420 * Returns: 1421 * Sample rate in HZ (always 48000). 1422 */ 1423static int 1424audiots_rate(void *arg) 1425{ 1426 audiots_port_t *port = arg; 1427 1428 return (port->tp_rate); 1429} 1430 1431/* 1432 * audiots_count() 1433 * 1434 * Description: 1435 * This is called by the framework to get the engine's frame counter 1436 * 1437 * Arguments: 1438 * void *arg The DMA engine to query 1439 * 1440 * Returns: 1441 * frame count for current engine 1442 */ 1443static uint64_t 1444audiots_count(void *arg) 1445{ 1446 audiots_port_t *port = arg; 1447 audiots_state_t *state = port->tp_state; 1448 uint64_t val; 1449 uint16_t cso; 1450 unsigned n; 1451 1452 cso = ddi_get16(state->ts_acch, 1453 &state->ts_regs->aud_ram[port->tp_dma_stream].aram.aram_cso); 1454 1455 n = (cso >= port->tp_cso) ? 1456 cso - port->tp_cso : 1457 cso + port->tp_nframes - port->tp_cso; 1458 1459 port->tp_cso = cso; 1460 port->tp_count += n; 1461 val = port->tp_count; 1462 1463 return (val); 1464} 1465 1466/* 1467 * audiots_sync() 1468 * 1469 * Description: 1470 * This is called by the framework to synchronize DMA caches. 1471 * 1472 * Arguments: 1473 * void *arg The DMA engine to sync 1474 */ 1475static void 1476audiots_sync(void *arg, unsigned nframes) 1477{ 1478 audiots_port_t *port = arg; 1479 _NOTE(ARGUNUSED(nframes)); 1480 1481 (void) ddi_dma_sync(port->tp_dmah, 0, 0, port->tp_sync_dir); 1482} 1483 1484/* 1485 * audiots_stop_everything() 1486 * 1487 * Description: 1488 * This routine disables the address engine interrupt for all 32 DMA 1489 * engines. Just to be sure, it then explicitly issues a stop command to 1490 * the address engine and envelope engines for all 32 channels. 1491 * 1492 * NOTE: 1493 * 1494 * There is a hardware bug that generates a spurious interrupt 1495 * when the DMA engines are stopped. It's not consistent - it 1496 * happens every 1 out of 6 stops or so. It will show up as a 1497 * record interrupt. The problem is that once the driver is 1498 * detached or if the system goes into low power mode, nobody 1499 * will service that interrupt. The system will eventually become 1500 * unusable. 1501 * 1502 * Arguments: 1503 * audiots_state_t *state The device's state structure 1504 */ 1505static void 1506audiots_stop_everything(audiots_state_t *state) 1507{ 1508 if (state->ts_acch == NULL) 1509 return; 1510 1511 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten, 1512 TS_ALL_DMA_OFF); 1513 1514 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop, 1515 TS_ALL_DMA_ENGINES); 1516 1517 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_aint, 1518 TS_ALL_DMA_ENGINES); 1519} 1520 1521/* 1522 * audiots_free_port() 1523 * 1524 * Description: 1525 * This routine unbinds the DMA cookies, frees the DMA buffers, 1526 * deallocates the DMA handles. 1527 * 1528 * Arguments: 1529 * audiots_port_t *port The port structure for a device stream. 1530 */ 1531void 1532audiots_free_port(audiots_port_t *port) 1533{ 1534 if (port == NULL) 1535 return; 1536 1537 if (port->tp_engine) { 1538 audio_dev_remove_engine(port->tp_state->ts_adev, 1539 port->tp_engine); 1540 audio_engine_free(port->tp_engine); 1541 } 1542 if (port->tp_paddr) { 1543 (void) ddi_dma_unbind_handle(port->tp_dmah); 1544 } 1545 if (port->tp_acch) { 1546 ddi_dma_mem_free(&port->tp_acch); 1547 } 1548 if (port->tp_dmah) { 1549 ddi_dma_free_handle(&port->tp_dmah); 1550 } 1551 kmem_free(port, sizeof (*port)); 1552} 1553 1554/* 1555 * audiots_destroy() 1556 * 1557 * Description: 1558 * This routine releases all resources held by the device instance, 1559 * as part of either detach or a failure in attach. 1560 * 1561 * Arguments: 1562 * audiots_state_t *state The device soft state. 1563 */ 1564void 1565audiots_destroy(audiots_state_t *state) 1566{ 1567 audiots_stop_everything(state); 1568 1569 for (int i = 0; i < TS_NUM_PORTS; i++) 1570 audiots_free_port(state->ts_ports[i]); 1571 1572 if (state->ts_acch) 1573 ddi_regs_map_free(&state->ts_acch); 1574 1575 if (state->ts_pcih) 1576 pci_config_teardown(&state->ts_pcih); 1577 1578 if (state->ts_ac97) 1579 ac97_free(state->ts_ac97); 1580 1581 if (state->ts_adev) 1582 audio_dev_free(state->ts_adev); 1583 1584 ddi_soft_state_free(audiots_statep, ddi_get_instance(state->ts_dip)); 1585} 1586