/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
H A D | process_pptables_v1_0.h | 31 struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
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H A D | vega10_processpptables.h | 60 struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
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H A D | vega12_processpptables.c | 352 uint32_t entry_index, struct pp_power_state *power_state, 364 power_state->classification.bios_index = entry_index; 384 result = call_back_func(hwmgr, (void *)state_entry, power_state, 391 if (!result && (power_state->classification.flags & 393 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
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H A D | vega10_processpptables.c | 1295 uint32_t entry_index, struct pp_power_state *power_state, 1307 power_state->classification.bios_index = entry_index; 1327 result = call_back_func(hwmgr, (void *)state_entry, power_state, 1334 if (!result && (power_state->classification.flags & 1336 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); 1294 vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index, struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *, struct pp_power_state *, void *, uint32_t)) argument
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H A D | process_pptables_v1_0.c | 1364 * @power_state: The address of the PowerState instance being created. 1369 uint32_t entry_index, struct pp_power_state *power_state, 1381 power_state->classification.bios_index = entry_index; 1399 result = call_back_func(hwmgr, (void *)state_entry, power_state, 1406 if (!result && (power_state->classification.flags & 1408 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); 1368 get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t entry_index, struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *, struct pp_power_state *, void *, uint32_t)) argument
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H A D | vega10_hwmgr.c | 3116 void *state, struct pp_power_state *power_state, 3121 cast_phw_vega10_power_state(&(power_state->hardware)); 3143 power_state->classification.ui_label = 3147 power_state->classification.flags = classification_flag; 3151 power_state->classification.temporary_state = false; 3152 power_state->classification.to_be_deleted = false; 3154 power_state->validation.disallowOnDC = 3158 power_state->display.disableFrameModulation = false; 3159 power_state->display.limitRefreshrate = false; 3160 power_state 3115 vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, void *state, struct pp_power_state *power_state, void *pp_table, uint32_t classification_flag) argument [all...] |
H A D | smu7_hwmgr.c | 3591 void *state, struct pp_power_state *power_state, 3596 (struct smu7_power_state *)(&(power_state->hardware)); 3612 power_state->classification.ui_label = 3616 power_state->classification.flags = classification_flag; 3619 power_state->classification.temporary_state = false; 3620 power_state->classification.to_be_deleted = false; 3622 power_state->validation.disallowOnDC = 3626 power_state->pcie.lanes = 0; 3628 power_state->display.disableFrameModulation = false; 3629 power_state 3590 smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, void *state, struct pp_power_state *power_state, void *pp_table, uint32_t classification_flag) argument 3790 smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *power_state, unsigned int index, const void *clock_info) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | atombios_dp.h | 38 u8 power_state);
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H A D | amdgpu_atombios_dp.c | 470 u8 power_state) 483 DP_SET_POWER, power_state); 469 amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector, u8 power_state) argument
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/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | radeon_atombios.c | 2050 rdev->pm.power_state[state_index].misc = misc; 2051 rdev->pm.power_state[state_index].misc2 = misc2; 2054 rdev->pm.power_state[state_index].type = 2057 rdev->pm.power_state[state_index].type = 2060 rdev->pm.power_state[state_index].type = 2063 rdev->pm.power_state[state_index].type = 2066 rdev->pm.power_state[state_index].type = 2068 rdev->pm.power_state[state_index].flags &= 2072 rdev->pm.power_state[state_index].type = 2075 rdev->pm.power_state[state_inde 2585 union pplib_power_state *power_state; local 2675 union pplib_power_state *power_state; local [all...] |
H A D | radeon_combios.c | 2657 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state), 2659 if (rdev->pm.power_state) { 2661 rdev->pm.power_state[0].clock_info = 2664 rdev->pm.power_state[1].clock_info = 2667 if (!rdev->pm.power_state[0].clock_info || 2668 !rdev->pm.power_state[1].clock_info) 2748 rdev->pm.power_state[state_index].num_clock_modes = 1; 2749 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2750 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2751 if ((rdev->pm.power_state[state_inde [all...] |
H A D | radeon_pm.c | 64 if (rdev->pm.power_state[i].type == ps_type) { 182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 324 struct radeon_power_state *power_state; local 329 power_state = &rdev->pm.power_state[i]; 331 radeon_pm_state_type_name[power_state->type]); 335 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 336 if (power_state [all...] |
H A D | rs780_dpm.c | 793 union pplib_power_state *power_state; local 814 power_state = (union pplib_power_state *) 821 (power_state->v1.ucNonClockStateIndex * 827 (power_state->v1.ucClockStateIndices[0] *
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H A D | trinity_dpm.c | 1689 union pplib_power_state *power_state; local 1725 power_state = (union pplib_power_state *)power_state_offset; 1726 non_clock_array_index = power_state->v2.nonClockInfoIndex; 1729 if (!rdev->pm.power_state[i].clock_info) { 1740 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 1741 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 1758 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
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H A D | sumo_dpm.c | 1456 union pplib_power_state *power_state; local 1492 power_state = (union pplib_power_state *)power_state_offset; 1493 non_clock_array_index = power_state->v2.nonClockInfoIndex; 1496 if (!rdev->pm.power_state[i].clock_info) { 1507 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 1508 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 1524 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
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H A D | r600.c | 389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 412 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 493 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 527 rdev->pm.power_state[rde [all...] |
H A D | rs600.c | 232 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 316 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
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H A D | atombios_dp.c | 518 u8 power_state) 531 DP_SET_POWER, power_state); 517 radeon_dp_set_rx_power_state(struct drm_connector *connector, u8 power_state) argument
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H A D | r100.c | 241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 269 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 297 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 299 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 301 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 364 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 445 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
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H A D | kv_dpm.c | 2433 union pplib_power_state *power_state; local 2469 power_state = (union pplib_power_state *)power_state_offset; 2470 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2473 if (!rdev->pm.power_state[i].clock_info) 2482 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 2483 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2500 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
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H A D | rv6xx_dpm.c | 1876 union pplib_power_state *power_state; local 1897 power_state = (union pplib_power_state *) 1904 (power_state->v1.ucNonClockStateIndex * 1916 idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
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H A D | rv770_dpm.c | 2272 union pplib_power_state *power_state; local 2293 power_state = (union pplib_power_state *) 2300 (power_state->v1.ucNonClockStateIndex * 2313 idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/ |
H A D | smu_v11_0.h | 135 enum smu_11_0_power_state power_state; member in struct:smu_11_0_power_context 141 enum smu_11_0_power_state power_state; member in struct:smu_11_5_power_context
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H A D | smu_v13_0.h | 123 enum smu_13_0_power_state power_state; member in struct:smu_13_0_power_context
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/openbsd-current/sys/dev/fdt/ |
H A D | psci.c | 354 psci_cpu_suspend(register_t power_state, register_t entry_point_address, argument 360 return (*sc->sc_callfn)(sc->sc_cpu_suspend, power_state,
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