1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27#include <linux/pci.h> 28 29#include <drm/drm_device.h> 30#include <drm/radeon_drm.h> 31 32#include "radeon.h" 33 34#include "atom.h" 35#include "atom-bits.h" 36#include "radeon_asic.h" 37#include "radeon_atombios.h" 38#include "radeon_legacy_encoders.h" 39 40union atom_supported_devices { 41 struct _ATOM_SUPPORTED_DEVICES_INFO info; 42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 44}; 45 46static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 47 ATOM_GPIO_I2C_ASSIGMENT *gpio, 48 u8 index) 49{ 50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 51 if ((rdev->family == CHIP_R420) || 52 (rdev->family == CHIP_R423) || 53 (rdev->family == CHIP_RV410)) { 54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 57 gpio->ucClkMaskShift = 0x19; 58 gpio->ucDataMaskShift = 0x18; 59 } 60 } 61 62 /* some evergreen boards have bad data for this entry */ 63 if (ASIC_IS_DCE4(rdev)) { 64 if ((index == 7) && 65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 66 (gpio->sucI2cId.ucAccess == 0)) { 67 gpio->sucI2cId.ucAccess = 0x97; 68 gpio->ucDataMaskShift = 8; 69 gpio->ucDataEnShift = 8; 70 gpio->ucDataY_Shift = 8; 71 gpio->ucDataA_Shift = 8; 72 } 73 } 74 75 /* some DCE3 boards have bad data for this entry */ 76 if (ASIC_IS_DCE3(rdev)) { 77 if ((index == 4) && 78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 79 (gpio->sucI2cId.ucAccess == 0x94)) 80 gpio->sucI2cId.ucAccess = 0x14; 81 } 82} 83 84static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 85{ 86 struct radeon_i2c_bus_rec i2c; 87 88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 89 90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 101 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 106 107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 108 i2c.hw_capable = true; 109 else 110 i2c.hw_capable = false; 111 112 if (gpio->sucI2cId.ucAccess == 0xa0) 113 i2c.mm_i2c = true; 114 else 115 i2c.mm_i2c = false; 116 117 i2c.i2c_id = gpio->sucI2cId.ucAccess; 118 119 if (i2c.mask_clk_reg) 120 i2c.valid = true; 121 else 122 i2c.valid = false; 123 124 return i2c; 125} 126 127static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 128 uint8_t id) 129{ 130 struct atom_context *ctx = rdev->mode_info.atom_context; 131 ATOM_GPIO_I2C_ASSIGMENT *gpio; 132 struct radeon_i2c_bus_rec i2c; 133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 134 struct _ATOM_GPIO_I2C_INFO *i2c_info; 135 uint16_t data_offset, size; 136 int i, num_indices; 137 138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 139 i2c.valid = false; 140 141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 143 144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 145 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 146 147 gpio = &i2c_info->asGPIO_Info[0]; 148 for (i = 0; i < num_indices; i++) { 149 150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 151 152 if (gpio->sucI2cId.ucAccess == id) { 153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 154 break; 155 } 156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 158 } 159 } 160 161 return i2c; 162} 163 164void radeon_atombios_i2c_init(struct radeon_device *rdev) 165{ 166 struct atom_context *ctx = rdev->mode_info.atom_context; 167 ATOM_GPIO_I2C_ASSIGMENT *gpio; 168 struct radeon_i2c_bus_rec i2c; 169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 170 struct _ATOM_GPIO_I2C_INFO *i2c_info; 171 uint16_t data_offset, size; 172 int i, num_indices; 173 char stmp[32]; 174 175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 177 178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 179 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 180 181 gpio = &i2c_info->asGPIO_Info[0]; 182 for (i = 0; i < num_indices; i++) { 183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 184 185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 186 187 if (i2c.valid) { 188 snprintf(stmp, sizeof(stmp), "0x%x", i2c.i2c_id); 189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 190 } 191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 193 } 194 } 195} 196 197struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 198 u8 id) 199{ 200 struct atom_context *ctx = rdev->mode_info.atom_context; 201 struct radeon_gpio_rec gpio; 202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 203 struct _ATOM_GPIO_PIN_LUT *gpio_info; 204 ATOM_GPIO_PIN_ASSIGNMENT *pin; 205 u16 data_offset, size; 206 int i, num_indices; 207 208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 209 gpio.valid = false; 210 211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 213 214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 216 217 pin = gpio_info->asGPIO_Pin; 218 for (i = 0; i < num_indices; i++) { 219 if (id == pin->ucGPIO_ID) { 220 gpio.id = pin->ucGPIO_ID; 221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 222 gpio.shift = pin->ucGpioPinBitShift; 223 gpio.mask = (1 << pin->ucGpioPinBitShift); 224 gpio.valid = true; 225 break; 226 } 227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 229 } 230 } 231 232 return gpio; 233} 234 235static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 236 struct radeon_gpio_rec *gpio) 237{ 238 struct radeon_hpd hpd; 239 u32 reg; 240 241 memset(&hpd, 0, sizeof(struct radeon_hpd)); 242 243 if (ASIC_IS_DCE6(rdev)) 244 reg = SI_DC_GPIO_HPD_A; 245 else if (ASIC_IS_DCE4(rdev)) 246 reg = EVERGREEN_DC_GPIO_HPD_A; 247 else 248 reg = AVIVO_DC_GPIO_HPD_A; 249 250 hpd.gpio = *gpio; 251 if (gpio->reg == reg) { 252 switch(gpio->mask) { 253 case (1 << 0): 254 hpd.hpd = RADEON_HPD_1; 255 break; 256 case (1 << 8): 257 hpd.hpd = RADEON_HPD_2; 258 break; 259 case (1 << 16): 260 hpd.hpd = RADEON_HPD_3; 261 break; 262 case (1 << 24): 263 hpd.hpd = RADEON_HPD_4; 264 break; 265 case (1 << 26): 266 hpd.hpd = RADEON_HPD_5; 267 break; 268 case (1 << 28): 269 hpd.hpd = RADEON_HPD_6; 270 break; 271 default: 272 hpd.hpd = RADEON_HPD_NONE; 273 break; 274 } 275 } else 276 hpd.hpd = RADEON_HPD_NONE; 277 return hpd; 278} 279 280static bool radeon_atom_apply_quirks(struct drm_device *dev, 281 uint32_t supported_device, 282 int *connector_type, 283 struct radeon_i2c_bus_rec *i2c_bus, 284 uint16_t *line_mux, 285 struct radeon_hpd *hpd) 286{ 287#ifdef __linux__ 288 struct pci_dev *pdev = to_pci_dev(dev->dev); 289#else 290 struct pci_dev *pdev = dev->pdev; 291#endif 292 293 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 294 if ((pdev->device == 0x791e) && 295 (pdev->subsystem_vendor == 0x1043) && 296 (pdev->subsystem_device == 0x826d)) { 297 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 298 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 299 *connector_type = DRM_MODE_CONNECTOR_DVID; 300 } 301 302 /* Asrock RS600 board lists the DVI port as HDMI */ 303 if ((pdev->device == 0x7941) && 304 (pdev->subsystem_vendor == 0x1849) && 305 (pdev->subsystem_device == 0x7941)) { 306 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 308 *connector_type = DRM_MODE_CONNECTOR_DVID; 309 } 310 311 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 312 if ((pdev->device == 0x796e) && 313 (pdev->subsystem_vendor == 0x1462) && 314 (pdev->subsystem_device == 0x7302)) { 315 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 316 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 317 return false; 318 } 319 320 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 321 if ((pdev->device == 0x7941) && 322 (pdev->subsystem_vendor == 0x147b) && 323 (pdev->subsystem_device == 0x2412)) { 324 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 325 return false; 326 } 327 328 /* Falcon NW laptop lists vga ddc line for LVDS */ 329 if ((pdev->device == 0x5653) && 330 (pdev->subsystem_vendor == 0x1462) && 331 (pdev->subsystem_device == 0x0291)) { 332 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 333 i2c_bus->valid = false; 334 *line_mux = 53; 335 } 336 } 337 338 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 339 if ((pdev->device == 0x7146) && 340 (pdev->subsystem_vendor == 0x17af) && 341 (pdev->subsystem_device == 0x2058)) { 342 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 343 return false; 344 } 345 346 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 347 if ((pdev->device == 0x7142) && 348 (pdev->subsystem_vendor == 0x1458) && 349 (pdev->subsystem_device == 0x2134)) { 350 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 351 return false; 352 } 353 354 355 /* Funky macbooks */ 356 if ((pdev->device == 0x71C5) && 357 (pdev->subsystem_vendor == 0x106b) && 358 (pdev->subsystem_device == 0x0080)) { 359 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 360 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 361 return false; 362 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 363 *line_mux = 0x90; 364 } 365 366 /* mac rv630, rv730, others */ 367 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 368 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 369 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 370 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 371 } 372 373 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 374 if ((pdev->device == 0x9598) && 375 (pdev->subsystem_vendor == 0x1043) && 376 (pdev->subsystem_device == 0x01da)) { 377 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 378 *connector_type = DRM_MODE_CONNECTOR_DVII; 379 } 380 } 381 382 /* ASUS HD 3600 board lists the DVI port as HDMI */ 383 if ((pdev->device == 0x9598) && 384 (pdev->subsystem_vendor == 0x1043) && 385 (pdev->subsystem_device == 0x01e4)) { 386 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 387 *connector_type = DRM_MODE_CONNECTOR_DVII; 388 } 389 } 390 391 /* ASUS HD 3450 board lists the DVI port as HDMI */ 392 if ((pdev->device == 0x95C5) && 393 (pdev->subsystem_vendor == 0x1043) && 394 (pdev->subsystem_device == 0x01e2)) { 395 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 396 *connector_type = DRM_MODE_CONNECTOR_DVII; 397 } 398 } 399 400 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 401 * HDMI + VGA reporting as HDMI 402 */ 403 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 404 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 405 *connector_type = DRM_MODE_CONNECTOR_VGA; 406 *line_mux = 0; 407 } 408 } 409 410 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 411 * on the laptop and a DVI port on the docking station and 412 * both share the same encoder, hpd pin, and ddc line. 413 * So while the bios table is technically correct, 414 * we drop the DVI port here since xrandr has no concept of 415 * encoders and will try and drive both connectors 416 * with different crtcs which isn't possible on the hardware 417 * side and leaves no crtcs for LVDS or VGA. 418 */ 419 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) && 420 (pdev->subsystem_vendor == 0x1025) && 421 (pdev->subsystem_device == 0x013c)) { 422 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 423 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 424 /* actually it's a DVI-D port not DVI-I */ 425 *connector_type = DRM_MODE_CONNECTOR_DVID; 426 return false; 427 } 428 } 429 430 /* XFX Pine Group device rv730 reports no VGA DDC lines 431 * even though they are wired up to record 0x93 432 */ 433 if ((pdev->device == 0x9498) && 434 (pdev->subsystem_vendor == 0x1682) && 435 (pdev->subsystem_device == 0x2452) && 436 (i2c_bus->valid == false) && 437 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 438 struct radeon_device *rdev = dev->dev_private; 439 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 440 } 441 442 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 443 if (((pdev->device == 0x9802) || 444 (pdev->device == 0x9805) || 445 (pdev->device == 0x9806)) && 446 (pdev->subsystem_vendor == 0x1734) && 447 (pdev->subsystem_device == 0x11bd)) { 448 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 449 *connector_type = DRM_MODE_CONNECTOR_DVII; 450 *line_mux = 0x3103; 451 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 452 *connector_type = DRM_MODE_CONNECTOR_DVII; 453 } 454 } 455 456 return true; 457} 458 459static const int supported_devices_connector_convert[] = { 460 DRM_MODE_CONNECTOR_Unknown, 461 DRM_MODE_CONNECTOR_VGA, 462 DRM_MODE_CONNECTOR_DVII, 463 DRM_MODE_CONNECTOR_DVID, 464 DRM_MODE_CONNECTOR_DVIA, 465 DRM_MODE_CONNECTOR_SVIDEO, 466 DRM_MODE_CONNECTOR_Composite, 467 DRM_MODE_CONNECTOR_LVDS, 468 DRM_MODE_CONNECTOR_Unknown, 469 DRM_MODE_CONNECTOR_Unknown, 470 DRM_MODE_CONNECTOR_HDMIA, 471 DRM_MODE_CONNECTOR_HDMIB, 472 DRM_MODE_CONNECTOR_Unknown, 473 DRM_MODE_CONNECTOR_Unknown, 474 DRM_MODE_CONNECTOR_9PinDIN, 475 DRM_MODE_CONNECTOR_DisplayPort 476}; 477 478static const uint16_t supported_devices_connector_object_id_convert[] = { 479 CONNECTOR_OBJECT_ID_NONE, 480 CONNECTOR_OBJECT_ID_VGA, 481 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 482 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 483 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 484 CONNECTOR_OBJECT_ID_COMPOSITE, 485 CONNECTOR_OBJECT_ID_SVIDEO, 486 CONNECTOR_OBJECT_ID_LVDS, 487 CONNECTOR_OBJECT_ID_9PIN_DIN, 488 CONNECTOR_OBJECT_ID_9PIN_DIN, 489 CONNECTOR_OBJECT_ID_DISPLAYPORT, 490 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 491 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 492 CONNECTOR_OBJECT_ID_SVIDEO 493}; 494 495static const int object_connector_convert[] = { 496 DRM_MODE_CONNECTOR_Unknown, 497 DRM_MODE_CONNECTOR_DVII, 498 DRM_MODE_CONNECTOR_DVII, 499 DRM_MODE_CONNECTOR_DVID, 500 DRM_MODE_CONNECTOR_DVID, 501 DRM_MODE_CONNECTOR_VGA, 502 DRM_MODE_CONNECTOR_Composite, 503 DRM_MODE_CONNECTOR_SVIDEO, 504 DRM_MODE_CONNECTOR_Unknown, 505 DRM_MODE_CONNECTOR_Unknown, 506 DRM_MODE_CONNECTOR_9PinDIN, 507 DRM_MODE_CONNECTOR_Unknown, 508 DRM_MODE_CONNECTOR_HDMIA, 509 DRM_MODE_CONNECTOR_HDMIB, 510 DRM_MODE_CONNECTOR_LVDS, 511 DRM_MODE_CONNECTOR_9PinDIN, 512 DRM_MODE_CONNECTOR_Unknown, 513 DRM_MODE_CONNECTOR_Unknown, 514 DRM_MODE_CONNECTOR_Unknown, 515 DRM_MODE_CONNECTOR_DisplayPort, 516 DRM_MODE_CONNECTOR_eDP, 517 DRM_MODE_CONNECTOR_Unknown 518}; 519 520bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 521{ 522 struct radeon_device *rdev = dev->dev_private; 523 struct radeon_mode_info *mode_info = &rdev->mode_info; 524 struct atom_context *ctx = mode_info->atom_context; 525 int index = GetIndexIntoMasterTable(DATA, Object_Header); 526 u16 size, data_offset; 527 u8 frev, crev; 528 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 529 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 530 ATOM_OBJECT_TABLE *router_obj; 531 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 532 ATOM_OBJECT_HEADER *obj_header; 533 int i, j, k, path_size, device_support; 534 int connector_type; 535 u16 igp_lane_info, conn_id, connector_object_id; 536 struct radeon_i2c_bus_rec ddc_bus; 537 struct radeon_router router; 538 struct radeon_gpio_rec gpio; 539 struct radeon_hpd hpd; 540 541 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 542 return false; 543 544 if (crev < 2) 545 return false; 546 547 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 548 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 549 (ctx->bios + data_offset + 550 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 551 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 552 (ctx->bios + data_offset + 553 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 554 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 555 (ctx->bios + data_offset + 556 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 557 router_obj = (ATOM_OBJECT_TABLE *) 558 (ctx->bios + data_offset + 559 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 560 device_support = le16_to_cpu(obj_header->usDeviceSupport); 561 562 path_size = 0; 563 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 564 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 565 ATOM_DISPLAY_OBJECT_PATH *path; 566 addr += path_size; 567 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 568 path_size += le16_to_cpu(path->usSize); 569 570 if (device_support & le16_to_cpu(path->usDeviceTag)) { 571 uint8_t con_obj_id, con_obj_num; 572 573 con_obj_id = 574 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 575 >> OBJECT_ID_SHIFT; 576 con_obj_num = 577 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 578 >> ENUM_ID_SHIFT; 579 580 /* TODO CV support */ 581 if (le16_to_cpu(path->usDeviceTag) == 582 ATOM_DEVICE_CV_SUPPORT) 583 continue; 584 585 /* IGP chips */ 586 if ((rdev->flags & RADEON_IS_IGP) && 587 (con_obj_id == 588 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 589 uint16_t igp_offset = 0; 590 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 591 592 index = 593 GetIndexIntoMasterTable(DATA, 594 IntegratedSystemInfo); 595 596 if (atom_parse_data_header(ctx, index, &size, &frev, 597 &crev, &igp_offset)) { 598 599 if (crev >= 2) { 600 igp_obj = 601 (ATOM_INTEGRATED_SYSTEM_INFO_V2 602 *) (ctx->bios + igp_offset); 603 604 if (igp_obj) { 605 uint32_t slot_config, ct; 606 607 if (con_obj_num == 1) 608 slot_config = 609 igp_obj-> 610 ulDDISlot1Config; 611 else 612 slot_config = 613 igp_obj-> 614 ulDDISlot2Config; 615 616 ct = (slot_config >> 16) & 0xff; 617 connector_type = 618 object_connector_convert 619 [ct]; 620 connector_object_id = ct; 621 igp_lane_info = 622 slot_config & 0xffff; 623 } else 624 continue; 625 } else 626 continue; 627 } else { 628 igp_lane_info = 0; 629 connector_type = 630 object_connector_convert[con_obj_id]; 631 connector_object_id = con_obj_id; 632 } 633 } else { 634 igp_lane_info = 0; 635 connector_type = 636 object_connector_convert[con_obj_id]; 637 connector_object_id = con_obj_id; 638 } 639 640 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 641 continue; 642 643 router.ddc_valid = false; 644 router.cd_valid = false; 645 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 646 uint8_t grph_obj_type = 647 (le16_to_cpu(path->usGraphicObjIds[j]) & 648 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 649 650 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 651 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 652 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 653 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 654 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 655 (ctx->bios + data_offset + 656 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 657 ATOM_ENCODER_CAP_RECORD *cap_record; 658 u16 caps = 0; 659 660 while (record->ucRecordSize > 0 && 661 record->ucRecordType > 0 && 662 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 663 switch (record->ucRecordType) { 664 case ATOM_ENCODER_CAP_RECORD_TYPE: 665 cap_record =(ATOM_ENCODER_CAP_RECORD *) 666 record; 667 caps = le16_to_cpu(cap_record->usEncoderCap); 668 break; 669 } 670 record = (ATOM_COMMON_RECORD_HEADER *) 671 ((char *)record + record->ucRecordSize); 672 } 673 radeon_add_atom_encoder(dev, 674 encoder_obj, 675 le16_to_cpu 676 (path-> 677 usDeviceTag), 678 caps); 679 } 680 } 681 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 682 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 683 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 684 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 685 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 686 (ctx->bios + data_offset + 687 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 688 ATOM_I2C_RECORD *i2c_record; 689 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 690 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 691 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 692 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 693 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 694 (ctx->bios + data_offset + 695 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 696 u8 *num_dst_objs = (u8 *) 697 ((u8 *)router_src_dst_table + 1 + 698 (router_src_dst_table->ucNumberOfSrc * 2)); 699 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 700 int enum_id; 701 702 router.router_id = router_obj_id; 703 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 704 if (le16_to_cpu(path->usConnObjectId) == 705 le16_to_cpu(dst_objs[enum_id])) 706 break; 707 } 708 709 while (record->ucRecordSize > 0 && 710 record->ucRecordType > 0 && 711 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 712 switch (record->ucRecordType) { 713 case ATOM_I2C_RECORD_TYPE: 714 i2c_record = 715 (ATOM_I2C_RECORD *) 716 record; 717 i2c_config = 718 (ATOM_I2C_ID_CONFIG_ACCESS *) 719 &i2c_record->sucI2cId; 720 router.i2c_info = 721 radeon_lookup_i2c_gpio(rdev, 722 i2c_config-> 723 ucAccess); 724 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 725 break; 726 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 727 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 728 record; 729 router.ddc_valid = true; 730 router.ddc_mux_type = ddc_path->ucMuxType; 731 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 732 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 733 break; 734 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 735 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 736 record; 737 router.cd_valid = true; 738 router.cd_mux_type = cd_path->ucMuxType; 739 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 740 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 741 break; 742 } 743 record = (ATOM_COMMON_RECORD_HEADER *) 744 ((char *)record + record->ucRecordSize); 745 } 746 } 747 } 748 } 749 } 750 751 /* look up gpio for ddc, hpd */ 752 ddc_bus.valid = false; 753 hpd.hpd = RADEON_HPD_NONE; 754 if ((le16_to_cpu(path->usDeviceTag) & 755 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 756 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 757 if (le16_to_cpu(path->usConnObjectId) == 758 le16_to_cpu(con_obj->asObjects[j]. 759 usObjectID)) { 760 ATOM_COMMON_RECORD_HEADER 761 *record = 762 (ATOM_COMMON_RECORD_HEADER 763 *) 764 (ctx->bios + data_offset + 765 le16_to_cpu(con_obj-> 766 asObjects[j]. 767 usRecordOffset)); 768 ATOM_I2C_RECORD *i2c_record; 769 ATOM_HPD_INT_RECORD *hpd_record; 770 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 771 772 while (record->ucRecordSize > 0 && 773 record->ucRecordType > 0 && 774 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 775 switch (record->ucRecordType) { 776 case ATOM_I2C_RECORD_TYPE: 777 i2c_record = 778 (ATOM_I2C_RECORD *) 779 record; 780 i2c_config = 781 (ATOM_I2C_ID_CONFIG_ACCESS *) 782 &i2c_record->sucI2cId; 783 ddc_bus = radeon_lookup_i2c_gpio(rdev, 784 i2c_config-> 785 ucAccess); 786 break; 787 case ATOM_HPD_INT_RECORD_TYPE: 788 hpd_record = 789 (ATOM_HPD_INT_RECORD *) 790 record; 791 gpio = radeon_atombios_lookup_gpio(rdev, 792 hpd_record->ucHPDIntGPIOID); 793 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 794 hpd.plugged_state = hpd_record->ucPlugged_PinState; 795 break; 796 } 797 record = 798 (ATOM_COMMON_RECORD_HEADER 799 *) ((char *)record 800 + 801 record-> 802 ucRecordSize); 803 } 804 break; 805 } 806 } 807 } 808 809 /* needed for aux chan transactions */ 810 ddc_bus.hpd = hpd.hpd; 811 812 conn_id = le16_to_cpu(path->usConnObjectId); 813 814 if (!radeon_atom_apply_quirks 815 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 816 &ddc_bus, &conn_id, &hpd)) 817 continue; 818 819 radeon_add_atom_connector(dev, 820 conn_id, 821 le16_to_cpu(path-> 822 usDeviceTag), 823 connector_type, &ddc_bus, 824 igp_lane_info, 825 connector_object_id, 826 &hpd, 827 &router); 828 829 } 830 } 831 832 radeon_link_encoder_connector(dev); 833 return true; 834} 835 836static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 837 int connector_type, 838 uint16_t devices) 839{ 840 struct radeon_device *rdev = dev->dev_private; 841 842 if (rdev->flags & RADEON_IS_IGP) { 843 return supported_devices_connector_object_id_convert 844 [connector_type]; 845 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 846 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 847 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 848 struct radeon_mode_info *mode_info = &rdev->mode_info; 849 struct atom_context *ctx = mode_info->atom_context; 850 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 851 uint16_t size, data_offset; 852 uint8_t frev, crev; 853 ATOM_XTMDS_INFO *xtmds; 854 855 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 856 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 857 858 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 859 if (connector_type == DRM_MODE_CONNECTOR_DVII) 860 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 861 else 862 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 863 } else { 864 if (connector_type == DRM_MODE_CONNECTOR_DVII) 865 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 866 else 867 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 868 } 869 } else 870 return supported_devices_connector_object_id_convert 871 [connector_type]; 872 } else { 873 return supported_devices_connector_object_id_convert 874 [connector_type]; 875 } 876} 877 878struct bios_connector { 879 bool valid; 880 uint16_t line_mux; 881 uint16_t devices; 882 int connector_type; 883 struct radeon_i2c_bus_rec ddc_bus; 884 struct radeon_hpd hpd; 885}; 886 887bool radeon_get_atom_connector_info_from_supported_devices_table(struct 888 drm_device 889 *dev) 890{ 891 struct radeon_device *rdev = dev->dev_private; 892 struct radeon_mode_info *mode_info = &rdev->mode_info; 893 struct atom_context *ctx = mode_info->atom_context; 894 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 895 uint16_t size, data_offset; 896 uint8_t frev, crev; 897 uint16_t device_support; 898 uint8_t dac; 899 union atom_supported_devices *supported_devices; 900 int i, j, max_device; 901 struct bios_connector *bios_connectors; 902 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 903 struct radeon_router router; 904 905 router.ddc_valid = false; 906 router.cd_valid = false; 907 908 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 909 if (!bios_connectors) 910 return false; 911 912 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 913 &data_offset)) { 914 kfree(bios_connectors); 915 return false; 916 } 917 918 supported_devices = 919 (union atom_supported_devices *)(ctx->bios + data_offset); 920 921 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 922 923 if (frev > 1) 924 max_device = ATOM_MAX_SUPPORTED_DEVICE; 925 else 926 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 927 928 for (i = 0; i < max_device; i++) { 929 ATOM_CONNECTOR_INFO_I2C ci; 930 931 if (frev > 1) 932 ci = supported_devices->info_2d1.asConnInfo[i]; 933 else 934 ci = supported_devices->info.asConnInfo[i]; 935 936 bios_connectors[i].valid = false; 937 938 if (!(device_support & (1 << i))) { 939 continue; 940 } 941 942 if (i == ATOM_DEVICE_CV_INDEX) { 943 DRM_DEBUG_KMS("Skipping Component Video\n"); 944 continue; 945 } 946 947 bios_connectors[i].connector_type = 948 supported_devices_connector_convert[ci.sucConnectorInfo. 949 sbfAccess. 950 bfConnectorType]; 951 952 if (bios_connectors[i].connector_type == 953 DRM_MODE_CONNECTOR_Unknown) 954 continue; 955 956 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 957 958 bios_connectors[i].line_mux = 959 ci.sucI2cId.ucAccess; 960 961 /* give tv unique connector ids */ 962 if (i == ATOM_DEVICE_TV1_INDEX) { 963 bios_connectors[i].ddc_bus.valid = false; 964 bios_connectors[i].line_mux = 50; 965 } else if (i == ATOM_DEVICE_TV2_INDEX) { 966 bios_connectors[i].ddc_bus.valid = false; 967 bios_connectors[i].line_mux = 51; 968 } else if (i == ATOM_DEVICE_CV_INDEX) { 969 bios_connectors[i].ddc_bus.valid = false; 970 bios_connectors[i].line_mux = 52; 971 } else 972 bios_connectors[i].ddc_bus = 973 radeon_lookup_i2c_gpio(rdev, 974 bios_connectors[i].line_mux); 975 976 if ((crev > 1) && (frev > 1)) { 977 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 978 switch (isb) { 979 case 0x4: 980 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 981 break; 982 case 0xa: 983 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 984 break; 985 default: 986 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 987 break; 988 } 989 } else { 990 if (i == ATOM_DEVICE_DFP1_INDEX) 991 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 992 else if (i == ATOM_DEVICE_DFP2_INDEX) 993 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 994 else 995 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 996 } 997 998 /* Always set the connector type to VGA for CRT1/CRT2. if they are 999 * shared with a DVI port, we'll pick up the DVI connector when we 1000 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 1001 */ 1002 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1003 bios_connectors[i].connector_type = 1004 DRM_MODE_CONNECTOR_VGA; 1005 1006 if (!radeon_atom_apply_quirks 1007 (dev, (1 << i), &bios_connectors[i].connector_type, 1008 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1009 &bios_connectors[i].hpd)) 1010 continue; 1011 1012 bios_connectors[i].valid = true; 1013 bios_connectors[i].devices = (1 << i); 1014 1015 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1016 radeon_add_atom_encoder(dev, 1017 radeon_get_encoder_enum(dev, 1018 (1 << i), 1019 dac), 1020 (1 << i), 1021 0); 1022 else 1023 radeon_add_legacy_encoder(dev, 1024 radeon_get_encoder_enum(dev, 1025 (1 << i), 1026 dac), 1027 (1 << i)); 1028 } 1029 1030 /* combine shared connectors */ 1031 for (i = 0; i < max_device; i++) { 1032 if (bios_connectors[i].valid) { 1033 for (j = 0; j < max_device; j++) { 1034 if (bios_connectors[j].valid && (i != j)) { 1035 if (bios_connectors[i].line_mux == 1036 bios_connectors[j].line_mux) { 1037 /* make sure not to combine LVDS */ 1038 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1039 bios_connectors[i].line_mux = 53; 1040 bios_connectors[i].ddc_bus.valid = false; 1041 continue; 1042 } 1043 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1044 bios_connectors[j].line_mux = 53; 1045 bios_connectors[j].ddc_bus.valid = false; 1046 continue; 1047 } 1048 /* combine analog and digital for DVI-I */ 1049 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1050 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1051 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1052 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1053 bios_connectors[i].devices |= 1054 bios_connectors[j].devices; 1055 bios_connectors[i].connector_type = 1056 DRM_MODE_CONNECTOR_DVII; 1057 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1058 bios_connectors[i].hpd = 1059 bios_connectors[j].hpd; 1060 bios_connectors[j].valid = false; 1061 } 1062 } 1063 } 1064 } 1065 } 1066 } 1067 1068 /* add the connectors */ 1069 for (i = 0; i < max_device; i++) { 1070 if (bios_connectors[i].valid) { 1071 uint16_t connector_object_id = 1072 atombios_get_connector_object_id(dev, 1073 bios_connectors[i].connector_type, 1074 bios_connectors[i].devices); 1075 radeon_add_atom_connector(dev, 1076 bios_connectors[i].line_mux, 1077 bios_connectors[i].devices, 1078 bios_connectors[i]. 1079 connector_type, 1080 &bios_connectors[i].ddc_bus, 1081 0, 1082 connector_object_id, 1083 &bios_connectors[i].hpd, 1084 &router); 1085 } 1086 } 1087 1088 radeon_link_encoder_connector(dev); 1089 1090 kfree(bios_connectors); 1091 return true; 1092} 1093 1094union firmware_info { 1095 ATOM_FIRMWARE_INFO info; 1096 ATOM_FIRMWARE_INFO_V1_2 info_12; 1097 ATOM_FIRMWARE_INFO_V1_3 info_13; 1098 ATOM_FIRMWARE_INFO_V1_4 info_14; 1099 ATOM_FIRMWARE_INFO_V2_1 info_21; 1100 ATOM_FIRMWARE_INFO_V2_2 info_22; 1101}; 1102 1103union igp_info { 1104 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1106 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1107 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1108 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1109}; 1110 1111static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) 1112{ 1113 struct radeon_mode_info *mode_info = &rdev->mode_info; 1114 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1115 union igp_info *igp_info; 1116 u8 frev, crev; 1117 u16 data_offset; 1118 1119 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1120 &frev, &crev, &data_offset)) { 1121 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1122 data_offset); 1123 rdev->clock.vco_freq = 1124 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); 1125 } 1126} 1127 1128bool radeon_atom_get_clock_info(struct drm_device *dev) 1129{ 1130 struct radeon_device *rdev = dev->dev_private; 1131 struct radeon_mode_info *mode_info = &rdev->mode_info; 1132 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1133 union firmware_info *firmware_info; 1134 uint8_t frev, crev; 1135 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1136 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1137 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1138 struct radeon_pll *spll = &rdev->clock.spll; 1139 struct radeon_pll *mpll = &rdev->clock.mpll; 1140 uint16_t data_offset; 1141 1142 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1143 &frev, &crev, &data_offset)) { 1144 firmware_info = 1145 (union firmware_info *)(mode_info->atom_context->bios + 1146 data_offset); 1147 /* pixel clocks */ 1148 p1pll->reference_freq = 1149 le16_to_cpu(firmware_info->info.usReferenceClock); 1150 p1pll->reference_div = 0; 1151 1152 if ((frev < 2) && (crev < 2)) 1153 p1pll->pll_out_min = 1154 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1155 else 1156 p1pll->pll_out_min = 1157 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1158 p1pll->pll_out_max = 1159 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1160 1161 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { 1162 p1pll->lcd_pll_out_min = 1163 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1164 if (p1pll->lcd_pll_out_min == 0) 1165 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1166 p1pll->lcd_pll_out_max = 1167 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1168 if (p1pll->lcd_pll_out_max == 0) 1169 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1170 } else { 1171 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1172 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1173 } 1174 1175 if (p1pll->pll_out_min == 0) { 1176 if (ASIC_IS_AVIVO(rdev)) 1177 p1pll->pll_out_min = 64800; 1178 else 1179 p1pll->pll_out_min = 20000; 1180 } 1181 1182 p1pll->pll_in_min = 1183 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1184 p1pll->pll_in_max = 1185 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1186 1187 *p2pll = *p1pll; 1188 1189 /* system clock */ 1190 if (ASIC_IS_DCE4(rdev)) 1191 spll->reference_freq = 1192 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1193 else 1194 spll->reference_freq = 1195 le16_to_cpu(firmware_info->info.usReferenceClock); 1196 spll->reference_div = 0; 1197 1198 spll->pll_out_min = 1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1200 spll->pll_out_max = 1201 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1202 1203 /* ??? */ 1204 if (spll->pll_out_min == 0) { 1205 if (ASIC_IS_AVIVO(rdev)) 1206 spll->pll_out_min = 64800; 1207 else 1208 spll->pll_out_min = 20000; 1209 } 1210 1211 spll->pll_in_min = 1212 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1213 spll->pll_in_max = 1214 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1215 1216 /* memory clock */ 1217 if (ASIC_IS_DCE4(rdev)) 1218 mpll->reference_freq = 1219 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1220 else 1221 mpll->reference_freq = 1222 le16_to_cpu(firmware_info->info.usReferenceClock); 1223 mpll->reference_div = 0; 1224 1225 mpll->pll_out_min = 1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1227 mpll->pll_out_max = 1228 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1229 1230 /* ??? */ 1231 if (mpll->pll_out_min == 0) { 1232 if (ASIC_IS_AVIVO(rdev)) 1233 mpll->pll_out_min = 64800; 1234 else 1235 mpll->pll_out_min = 20000; 1236 } 1237 1238 mpll->pll_in_min = 1239 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1240 mpll->pll_in_max = 1241 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1242 1243 rdev->clock.default_sclk = 1244 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1245 rdev->clock.default_mclk = 1246 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1247 1248 if (ASIC_IS_DCE4(rdev)) { 1249 rdev->clock.default_dispclk = 1250 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1251 if (rdev->clock.default_dispclk == 0) { 1252 if (ASIC_IS_DCE6(rdev)) 1253 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1254 else if (ASIC_IS_DCE5(rdev)) 1255 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1256 else 1257 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1258 } 1259 /* set a reasonable default for DP */ 1260 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1261 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1262 rdev->clock.default_dispclk / 100); 1263 rdev->clock.default_dispclk = 60000; 1264 } 1265 rdev->clock.dp_extclk = 1266 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1267 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1268 } 1269 *dcpll = *p1pll; 1270 1271 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1272 if (rdev->clock.max_pixel_clock == 0) 1273 rdev->clock.max_pixel_clock = 40000; 1274 1275 /* not technically a clock, but... */ 1276 rdev->mode_info.firmware_flags = 1277 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1278 1279 if (ASIC_IS_DCE8(rdev)) 1280 rdev->clock.vco_freq = 1281 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); 1282 else if (ASIC_IS_DCE5(rdev)) 1283 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1284 else if (ASIC_IS_DCE41(rdev)) 1285 radeon_atombios_get_dentist_vco_freq(rdev); 1286 else 1287 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1288 1289 if (rdev->clock.vco_freq == 0) 1290 rdev->clock.vco_freq = 360000; /* 3.6 GHz */ 1291 1292 return true; 1293 } 1294 1295 return false; 1296} 1297 1298bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1299{ 1300 struct radeon_mode_info *mode_info = &rdev->mode_info; 1301 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1302 union igp_info *igp_info; 1303 u8 frev, crev; 1304 u16 data_offset; 1305 1306 /* sideport is AMD only */ 1307 if (rdev->family == CHIP_RS600) 1308 return false; 1309 1310 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1311 &frev, &crev, &data_offset)) { 1312 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1313 data_offset); 1314 switch (crev) { 1315 case 1: 1316 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1317 return true; 1318 break; 1319 case 2: 1320 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1321 return true; 1322 break; 1323 default: 1324 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1325 break; 1326 } 1327 } 1328 return false; 1329} 1330 1331bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1332 struct radeon_encoder_int_tmds *tmds) 1333{ 1334 struct drm_device *dev = encoder->base.dev; 1335 struct radeon_device *rdev = dev->dev_private; 1336 struct radeon_mode_info *mode_info = &rdev->mode_info; 1337 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1338 uint16_t data_offset; 1339 struct _ATOM_TMDS_INFO *tmds_info; 1340 uint8_t frev, crev; 1341 uint16_t maxfreq; 1342 int i; 1343 1344 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1345 &frev, &crev, &data_offset)) { 1346 tmds_info = 1347 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1348 data_offset); 1349 1350 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1351 for (i = 0; i < 4; i++) { 1352 tmds->tmds_pll[i].freq = 1353 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1354 tmds->tmds_pll[i].value = 1355 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1356 tmds->tmds_pll[i].value |= 1357 (tmds_info->asMiscInfo[i]. 1358 ucPLL_VCO_Gain & 0x3f) << 6; 1359 tmds->tmds_pll[i].value |= 1360 (tmds_info->asMiscInfo[i]. 1361 ucPLL_DutyCycle & 0xf) << 12; 1362 tmds->tmds_pll[i].value |= 1363 (tmds_info->asMiscInfo[i]. 1364 ucPLL_VoltageSwing & 0xf) << 16; 1365 1366 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1367 tmds->tmds_pll[i].freq, 1368 tmds->tmds_pll[i].value); 1369 1370 if (maxfreq == tmds->tmds_pll[i].freq) { 1371 tmds->tmds_pll[i].freq = 0xffffffff; 1372 break; 1373 } 1374 } 1375 return true; 1376 } 1377 return false; 1378} 1379 1380bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1381 struct radeon_atom_ss *ss, 1382 int id) 1383{ 1384 struct radeon_mode_info *mode_info = &rdev->mode_info; 1385 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1386 uint16_t data_offset, size; 1387 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1388 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1389 uint8_t frev, crev; 1390 int i, num_indices; 1391 1392 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1393 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1394 &frev, &crev, &data_offset)) { 1395 ss_info = 1396 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1397 1398 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1399 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1400 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1401 ((u8 *)&ss_info->asSS_Info[0]); 1402 for (i = 0; i < num_indices; i++) { 1403 if (ss_assign->ucSS_Id == id) { 1404 ss->percentage = 1405 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1406 ss->type = ss_assign->ucSpreadSpectrumType; 1407 ss->step = ss_assign->ucSS_Step; 1408 ss->delay = ss_assign->ucSS_Delay; 1409 ss->range = ss_assign->ucSS_Range; 1410 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1411 return true; 1412 } 1413 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1414 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1415 } 1416 } 1417 return false; 1418} 1419 1420static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1421 struct radeon_atom_ss *ss, 1422 int id) 1423{ 1424 struct radeon_mode_info *mode_info = &rdev->mode_info; 1425 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1426 u16 data_offset, size; 1427 union igp_info *igp_info; 1428 u8 frev, crev; 1429 u16 percentage = 0, rate = 0; 1430 1431 /* get any igp specific overrides */ 1432 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1433 &frev, &crev, &data_offset)) { 1434 igp_info = (union igp_info *) 1435 (mode_info->atom_context->bios + data_offset); 1436 switch (crev) { 1437 case 6: 1438 switch (id) { 1439 case ASIC_INTERNAL_SS_ON_TMDS: 1440 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1441 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1442 break; 1443 case ASIC_INTERNAL_SS_ON_HDMI: 1444 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1445 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1446 break; 1447 case ASIC_INTERNAL_SS_ON_LVDS: 1448 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1449 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1450 break; 1451 } 1452 break; 1453 case 7: 1454 switch (id) { 1455 case ASIC_INTERNAL_SS_ON_TMDS: 1456 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1457 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1458 break; 1459 case ASIC_INTERNAL_SS_ON_HDMI: 1460 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1461 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1462 break; 1463 case ASIC_INTERNAL_SS_ON_LVDS: 1464 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1465 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1466 break; 1467 } 1468 break; 1469 case 8: 1470 switch (id) { 1471 case ASIC_INTERNAL_SS_ON_TMDS: 1472 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1473 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1474 break; 1475 case ASIC_INTERNAL_SS_ON_HDMI: 1476 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1477 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1478 break; 1479 case ASIC_INTERNAL_SS_ON_LVDS: 1480 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1481 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1482 break; 1483 } 1484 break; 1485 default: 1486 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1487 break; 1488 } 1489 if (percentage) 1490 ss->percentage = percentage; 1491 if (rate) 1492 ss->rate = rate; 1493 } 1494} 1495 1496union asic_ss_info { 1497 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1498 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1499 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1500}; 1501 1502union asic_ss_assignment { 1503 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1504 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1505 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1506}; 1507 1508bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1509 struct radeon_atom_ss *ss, 1510 int id, u32 clock) 1511{ 1512 struct radeon_mode_info *mode_info = &rdev->mode_info; 1513 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1514 uint16_t data_offset, size; 1515 union asic_ss_info *ss_info; 1516 union asic_ss_assignment *ss_assign; 1517 uint8_t frev, crev; 1518 int i, num_indices; 1519 1520 if (id == ASIC_INTERNAL_MEMORY_SS) { 1521 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1522 return false; 1523 } 1524 if (id == ASIC_INTERNAL_ENGINE_SS) { 1525 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1526 return false; 1527 } 1528 1529 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1530 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1531 &frev, &crev, &data_offset)) { 1532 1533 ss_info = 1534 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1535 1536 switch (frev) { 1537 case 1: 1538 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1539 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1540 1541 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1542 for (i = 0; i < num_indices; i++) { 1543 if ((ss_assign->v1.ucClockIndication == id) && 1544 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1545 ss->percentage = 1546 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1547 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1548 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1549 ss->percentage_divider = 100; 1550 return true; 1551 } 1552 ss_assign = (union asic_ss_assignment *) 1553 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1554 } 1555 break; 1556 case 2: 1557 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1558 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1559 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1560 for (i = 0; i < num_indices; i++) { 1561 if ((ss_assign->v2.ucClockIndication == id) && 1562 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1563 ss->percentage = 1564 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1565 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1566 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1567 ss->percentage_divider = 100; 1568 if ((crev == 2) && 1569 ((id == ASIC_INTERNAL_ENGINE_SS) || 1570 (id == ASIC_INTERNAL_MEMORY_SS))) 1571 ss->rate /= 100; 1572 return true; 1573 } 1574 ss_assign = (union asic_ss_assignment *) 1575 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1576 } 1577 break; 1578 case 3: 1579 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1580 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1581 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1582 for (i = 0; i < num_indices; i++) { 1583 if ((ss_assign->v3.ucClockIndication == id) && 1584 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1585 ss->percentage = 1586 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1587 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1588 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1589 if (ss_assign->v3.ucSpreadSpectrumMode & 1590 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1591 ss->percentage_divider = 1000; 1592 else 1593 ss->percentage_divider = 100; 1594 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1595 (id == ASIC_INTERNAL_MEMORY_SS)) 1596 ss->rate /= 100; 1597 if (rdev->flags & RADEON_IS_IGP) 1598 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1599 return true; 1600 } 1601 ss_assign = (union asic_ss_assignment *) 1602 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1603 } 1604 break; 1605 default: 1606 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1607 break; 1608 } 1609 1610 } 1611 return false; 1612} 1613 1614union lvds_info { 1615 struct _ATOM_LVDS_INFO info; 1616 struct _ATOM_LVDS_INFO_V12 info_12; 1617}; 1618 1619struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1620 radeon_encoder 1621 *encoder) 1622{ 1623 struct drm_device *dev = encoder->base.dev; 1624 struct radeon_device *rdev = dev->dev_private; 1625 struct radeon_mode_info *mode_info = &rdev->mode_info; 1626 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1627 uint16_t data_offset, misc; 1628 union lvds_info *lvds_info; 1629 uint8_t frev, crev; 1630 struct radeon_encoder_atom_dig *lvds = NULL; 1631 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1632 1633 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1634 &frev, &crev, &data_offset)) { 1635 lvds_info = 1636 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1637 lvds = 1638 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1639 1640 if (!lvds) 1641 return NULL; 1642 1643 lvds->native_mode.clock = 1644 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1645 lvds->native_mode.hdisplay = 1646 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1647 lvds->native_mode.vdisplay = 1648 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1649 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1650 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1651 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1652 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1653 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1654 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1655 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1656 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1657 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1658 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1659 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1660 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1661 lvds->panel_pwr_delay = 1662 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1663 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1664 1665 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1666 if (misc & ATOM_VSYNC_POLARITY) 1667 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1668 if (misc & ATOM_HSYNC_POLARITY) 1669 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1670 if (misc & ATOM_COMPOSITESYNC) 1671 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1672 if (misc & ATOM_INTERLACE) 1673 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1674 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1675 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1676 1677 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1678 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1679 1680 /* set crtc values */ 1681 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1682 1683 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1684 1685 encoder->native_mode = lvds->native_mode; 1686 1687 if (encoder_enum == 2) 1688 lvds->linkb = true; 1689 else 1690 lvds->linkb = false; 1691 1692 /* parse the lcd record table */ 1693 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1694 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1695 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1696 bool bad_record = false; 1697 u8 *record; 1698 1699 if ((frev == 1) && (crev < 2)) 1700 /* absolute */ 1701 record = (u8 *)(mode_info->atom_context->bios + 1702 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1703 else 1704 /* relative */ 1705 record = (u8 *)(mode_info->atom_context->bios + 1706 data_offset + 1707 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1708 while (*record != ATOM_RECORD_END_TYPE) { 1709 switch (*record) { 1710 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1711 record += sizeof(ATOM_PATCH_RECORD_MODE); 1712 break; 1713 case LCD_RTS_RECORD_TYPE: 1714 record += sizeof(ATOM_LCD_RTS_RECORD); 1715 break; 1716 case LCD_CAP_RECORD_TYPE: 1717 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1718 break; 1719 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1720 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1721 if (fake_edid_record->ucFakeEDIDLength) { 1722 struct edid *edid; 1723 int edid_size = 1724 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1725 edid = kmalloc(edid_size, GFP_KERNEL); 1726 if (edid) { 1727 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1728 fake_edid_record->ucFakeEDIDLength); 1729 1730 if (drm_edid_is_valid(edid)) { 1731 rdev->mode_info.bios_hardcoded_edid = edid; 1732 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1733 } else 1734 kfree(edid); 1735 } 1736 } 1737 record += fake_edid_record->ucFakeEDIDLength ? 1738 struct_size(fake_edid_record, 1739 ucFakeEDIDString, 1740 fake_edid_record->ucFakeEDIDLength) : 1741 /* empty fake edid record must be 3 bytes long */ 1742 sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1; 1743 break; 1744 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1745 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1746 lvds->native_mode.width_mm = panel_res_record->usHSize; 1747 lvds->native_mode.height_mm = panel_res_record->usVSize; 1748 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1749 break; 1750 default: 1751 DRM_ERROR("Bad LCD record %d\n", *record); 1752 bad_record = true; 1753 break; 1754 } 1755 if (bad_record) 1756 break; 1757 } 1758 } 1759 } 1760 return lvds; 1761} 1762 1763struct radeon_encoder_primary_dac * 1764radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1765{ 1766 struct drm_device *dev = encoder->base.dev; 1767 struct radeon_device *rdev = dev->dev_private; 1768 struct radeon_mode_info *mode_info = &rdev->mode_info; 1769 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1770 uint16_t data_offset; 1771 struct _COMPASSIONATE_DATA *dac_info; 1772 uint8_t frev, crev; 1773 uint8_t bg, dac; 1774 struct radeon_encoder_primary_dac *p_dac = NULL; 1775 1776 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1777 &frev, &crev, &data_offset)) { 1778 dac_info = (struct _COMPASSIONATE_DATA *) 1779 (mode_info->atom_context->bios + data_offset); 1780 1781 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1782 1783 if (!p_dac) 1784 return NULL; 1785 1786 bg = dac_info->ucDAC1_BG_Adjustment; 1787 dac = dac_info->ucDAC1_DAC_Adjustment; 1788 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1789 1790 } 1791 return p_dac; 1792} 1793 1794bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1795 struct drm_display_mode *mode) 1796{ 1797 struct radeon_mode_info *mode_info = &rdev->mode_info; 1798 ATOM_ANALOG_TV_INFO *tv_info; 1799 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1800 ATOM_DTD_FORMAT *dtd_timings; 1801 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1802 u8 frev, crev; 1803 u16 data_offset, misc; 1804 1805 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1806 &frev, &crev, &data_offset)) 1807 return false; 1808 1809 switch (crev) { 1810 case 1: 1811 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1812 if (index >= MAX_SUPPORTED_TV_TIMING) 1813 return false; 1814 1815 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1816 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1817 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1818 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1819 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1820 1821 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1822 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1823 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1824 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1825 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1826 1827 mode->flags = 0; 1828 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1829 if (misc & ATOM_VSYNC_POLARITY) 1830 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1831 if (misc & ATOM_HSYNC_POLARITY) 1832 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1833 if (misc & ATOM_COMPOSITESYNC) 1834 mode->flags |= DRM_MODE_FLAG_CSYNC; 1835 if (misc & ATOM_INTERLACE) 1836 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1837 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1838 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1839 1840 mode->crtc_clock = mode->clock = 1841 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1842 1843 if (index == 1) { 1844 /* PAL timings appear to have wrong values for totals */ 1845 mode->crtc_htotal -= 1; 1846 mode->crtc_vtotal -= 1; 1847 } 1848 break; 1849 case 2: 1850 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1851 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1852 return false; 1853 1854 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1855 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1856 le16_to_cpu(dtd_timings->usHBlanking_Time); 1857 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1858 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1859 le16_to_cpu(dtd_timings->usHSyncOffset); 1860 mode->crtc_hsync_end = mode->crtc_hsync_start + 1861 le16_to_cpu(dtd_timings->usHSyncWidth); 1862 1863 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1864 le16_to_cpu(dtd_timings->usVBlanking_Time); 1865 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1866 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1867 le16_to_cpu(dtd_timings->usVSyncOffset); 1868 mode->crtc_vsync_end = mode->crtc_vsync_start + 1869 le16_to_cpu(dtd_timings->usVSyncWidth); 1870 1871 mode->flags = 0; 1872 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1873 if (misc & ATOM_VSYNC_POLARITY) 1874 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1875 if (misc & ATOM_HSYNC_POLARITY) 1876 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1877 if (misc & ATOM_COMPOSITESYNC) 1878 mode->flags |= DRM_MODE_FLAG_CSYNC; 1879 if (misc & ATOM_INTERLACE) 1880 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1881 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1882 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1883 1884 mode->crtc_clock = mode->clock = 1885 le16_to_cpu(dtd_timings->usPixClk) * 10; 1886 break; 1887 } 1888 return true; 1889} 1890 1891enum radeon_tv_std 1892radeon_atombios_get_tv_info(struct radeon_device *rdev) 1893{ 1894 struct radeon_mode_info *mode_info = &rdev->mode_info; 1895 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1896 uint16_t data_offset; 1897 uint8_t frev, crev; 1898 struct _ATOM_ANALOG_TV_INFO *tv_info; 1899 enum radeon_tv_std tv_std = TV_STD_NTSC; 1900 1901 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1902 &frev, &crev, &data_offset)) { 1903 1904 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1905 (mode_info->atom_context->bios + data_offset); 1906 1907 switch (tv_info->ucTV_BootUpDefaultStandard) { 1908 case ATOM_TV_NTSC: 1909 tv_std = TV_STD_NTSC; 1910 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1911 break; 1912 case ATOM_TV_NTSCJ: 1913 tv_std = TV_STD_NTSC_J; 1914 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1915 break; 1916 case ATOM_TV_PAL: 1917 tv_std = TV_STD_PAL; 1918 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1919 break; 1920 case ATOM_TV_PALM: 1921 tv_std = TV_STD_PAL_M; 1922 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1923 break; 1924 case ATOM_TV_PALN: 1925 tv_std = TV_STD_PAL_N; 1926 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1927 break; 1928 case ATOM_TV_PALCN: 1929 tv_std = TV_STD_PAL_CN; 1930 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1931 break; 1932 case ATOM_TV_PAL60: 1933 tv_std = TV_STD_PAL_60; 1934 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1935 break; 1936 case ATOM_TV_SECAM: 1937 tv_std = TV_STD_SECAM; 1938 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1939 break; 1940 default: 1941 tv_std = TV_STD_NTSC; 1942 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1943 break; 1944 } 1945 } 1946 return tv_std; 1947} 1948 1949struct radeon_encoder_tv_dac * 1950radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1951{ 1952 struct drm_device *dev = encoder->base.dev; 1953 struct radeon_device *rdev = dev->dev_private; 1954 struct radeon_mode_info *mode_info = &rdev->mode_info; 1955 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1956 uint16_t data_offset; 1957 struct _COMPASSIONATE_DATA *dac_info; 1958 uint8_t frev, crev; 1959 uint8_t bg, dac; 1960 struct radeon_encoder_tv_dac *tv_dac = NULL; 1961 1962 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1963 &frev, &crev, &data_offset)) { 1964 1965 dac_info = (struct _COMPASSIONATE_DATA *) 1966 (mode_info->atom_context->bios + data_offset); 1967 1968 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1969 1970 if (!tv_dac) 1971 return NULL; 1972 1973 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1974 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1975 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1976 1977 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1978 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1979 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1980 1981 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1982 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1983 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1984 1985 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1986 } 1987 return tv_dac; 1988} 1989 1990static const char *thermal_controller_names[] = { 1991 "NONE", 1992 "lm63", 1993 "adm1032", 1994 "adm1030", 1995 "max6649", 1996 "lm63", /* lm64 */ 1997 "f75375", 1998 "asc7xxx", 1999}; 2000 2001static const char *pp_lib_thermal_controller_names[] = { 2002 "NONE", 2003 "lm63", 2004 "adm1032", 2005 "adm1030", 2006 "max6649", 2007 "lm63", /* lm64 */ 2008 "f75375", 2009 "RV6xx", 2010 "RV770", 2011 "adt7473", 2012 "NONE", 2013 "External GPIO", 2014 "Evergreen", 2015 "emc2103", 2016 "Sumo", 2017 "Northern Islands", 2018 "Southern Islands", 2019 "lm96163", 2020 "Sea Islands", 2021}; 2022 2023union power_info { 2024 struct _ATOM_POWERPLAY_INFO info; 2025 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2026 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2027 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2028 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2029 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2030}; 2031 2032union pplib_clock_info { 2033 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2034 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2035 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2036 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2037 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2038 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2039}; 2040 2041union pplib_power_state { 2042 struct _ATOM_PPLIB_STATE v1; 2043 struct _ATOM_PPLIB_STATE_V2 v2; 2044}; 2045 2046static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2047 int state_index, 2048 u32 misc, u32 misc2) 2049{ 2050 rdev->pm.power_state[state_index].misc = misc; 2051 rdev->pm.power_state[state_index].misc2 = misc2; 2052 /* order matters! */ 2053 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2054 rdev->pm.power_state[state_index].type = 2055 POWER_STATE_TYPE_POWERSAVE; 2056 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2057 rdev->pm.power_state[state_index].type = 2058 POWER_STATE_TYPE_BATTERY; 2059 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2060 rdev->pm.power_state[state_index].type = 2061 POWER_STATE_TYPE_BATTERY; 2062 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2063 rdev->pm.power_state[state_index].type = 2064 POWER_STATE_TYPE_BALANCED; 2065 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2066 rdev->pm.power_state[state_index].type = 2067 POWER_STATE_TYPE_PERFORMANCE; 2068 rdev->pm.power_state[state_index].flags &= 2069 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2070 } 2071 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2072 rdev->pm.power_state[state_index].type = 2073 POWER_STATE_TYPE_BALANCED; 2074 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2075 rdev->pm.power_state[state_index].type = 2076 POWER_STATE_TYPE_DEFAULT; 2077 rdev->pm.default_power_state_index = state_index; 2078 rdev->pm.power_state[state_index].default_clock_mode = 2079 &rdev->pm.power_state[state_index].clock_info[0]; 2080 } else if (state_index == 0) { 2081 rdev->pm.power_state[state_index].clock_info[0].flags |= 2082 RADEON_PM_MODE_NO_DISPLAY; 2083 } 2084} 2085 2086static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2087{ 2088 struct radeon_mode_info *mode_info = &rdev->mode_info; 2089 u32 misc, misc2 = 0; 2090 int num_modes = 0, i; 2091 int state_index = 0; 2092 struct radeon_i2c_bus_rec i2c_bus; 2093 union power_info *power_info; 2094 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2095 u16 data_offset; 2096 u8 frev, crev; 2097 2098 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2099 &frev, &crev, &data_offset)) 2100 return state_index; 2101 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2102 2103 /* add the i2c bus for thermal/fan chip */ 2104 if ((power_info->info.ucOverdriveThermalController > 0) && 2105 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2106 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2107 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2108 power_info->info.ucOverdriveControllerAddress >> 1); 2109 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2110 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2111#ifdef notyet 2112 if (rdev->pm.i2c_bus) { 2113 struct i2c_board_info info = { }; 2114 const char *name = thermal_controller_names[power_info->info. 2115 ucOverdriveThermalController]; 2116 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2117 strscpy(info.type, name, sizeof(info.type)); 2118 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2119 } 2120#endif 2121 } 2122 num_modes = power_info->info.ucNumOfPowerModeEntries; 2123 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2124 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2125 if (num_modes == 0) 2126 return state_index; 2127 rdev->pm.power_state = kcalloc(num_modes, 2128 sizeof(struct radeon_power_state), 2129 GFP_KERNEL); 2130 if (!rdev->pm.power_state) 2131 return state_index; 2132 /* last mode is usually default, array is low to high */ 2133 for (i = 0; i < num_modes; i++) { 2134 /* avoid memory leaks from invalid modes or unknown frev. */ 2135 if (!rdev->pm.power_state[state_index].clock_info) { 2136 rdev->pm.power_state[state_index].clock_info = 2137 kzalloc(sizeof(struct radeon_pm_clock_info), 2138 GFP_KERNEL); 2139 } 2140 if (!rdev->pm.power_state[state_index].clock_info) 2141 goto out; 2142 rdev->pm.power_state[state_index].num_clock_modes = 1; 2143 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2144 switch (frev) { 2145 case 1: 2146 rdev->pm.power_state[state_index].clock_info[0].mclk = 2147 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2148 rdev->pm.power_state[state_index].clock_info[0].sclk = 2149 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2150 /* skip invalid modes */ 2151 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2152 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2153 continue; 2154 rdev->pm.power_state[state_index].pcie_lanes = 2155 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2156 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2157 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2158 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2159 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2160 VOLTAGE_GPIO; 2161 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2162 radeon_atombios_lookup_gpio(rdev, 2163 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2164 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2165 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2166 true; 2167 else 2168 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2169 false; 2170 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2171 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2172 VOLTAGE_VDDC; 2173 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2174 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2175 } 2176 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2177 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2178 state_index++; 2179 break; 2180 case 2: 2181 rdev->pm.power_state[state_index].clock_info[0].mclk = 2182 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2183 rdev->pm.power_state[state_index].clock_info[0].sclk = 2184 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2185 /* skip invalid modes */ 2186 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2187 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2188 continue; 2189 rdev->pm.power_state[state_index].pcie_lanes = 2190 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2191 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2192 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2193 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2194 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2195 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2196 VOLTAGE_GPIO; 2197 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2198 radeon_atombios_lookup_gpio(rdev, 2199 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2200 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2201 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2202 true; 2203 else 2204 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2205 false; 2206 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2207 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2208 VOLTAGE_VDDC; 2209 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2210 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2211 } 2212 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2213 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2214 state_index++; 2215 break; 2216 case 3: 2217 rdev->pm.power_state[state_index].clock_info[0].mclk = 2218 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2219 rdev->pm.power_state[state_index].clock_info[0].sclk = 2220 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2221 /* skip invalid modes */ 2222 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2223 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2224 continue; 2225 rdev->pm.power_state[state_index].pcie_lanes = 2226 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2227 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2228 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2229 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2230 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2231 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2232 VOLTAGE_GPIO; 2233 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2234 radeon_atombios_lookup_gpio(rdev, 2235 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2236 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2237 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2238 true; 2239 else 2240 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2241 false; 2242 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2243 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2244 VOLTAGE_VDDC; 2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2246 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2247 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2248 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2249 true; 2250 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2251 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2252 } 2253 } 2254 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2255 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2256 state_index++; 2257 break; 2258 } 2259 } 2260out: 2261 /* free any unused clock_info allocation. */ 2262 if (state_index && state_index < num_modes) { 2263 kfree(rdev->pm.power_state[state_index].clock_info); 2264 rdev->pm.power_state[state_index].clock_info = NULL; 2265 } 2266 2267 /* last mode is usually default */ 2268 if (state_index && rdev->pm.default_power_state_index == -1) { 2269 rdev->pm.power_state[state_index - 1].type = 2270 POWER_STATE_TYPE_DEFAULT; 2271 rdev->pm.default_power_state_index = state_index - 1; 2272 rdev->pm.power_state[state_index - 1].default_clock_mode = 2273 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2274 rdev->pm.power_state[state_index - 1].flags &= 2275 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2276 rdev->pm.power_state[state_index - 1].misc = 0; 2277 rdev->pm.power_state[state_index - 1].misc2 = 0; 2278 } 2279 return state_index; 2280} 2281 2282static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2283 ATOM_PPLIB_THERMALCONTROLLER *controller) 2284{ 2285 struct radeon_i2c_bus_rec i2c_bus; 2286 2287 /* add the i2c bus for thermal/fan chip */ 2288 if (controller->ucType > 0) { 2289 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2290 rdev->pm.no_fan = true; 2291 rdev->pm.fan_pulses_per_revolution = 2292 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2293 if (rdev->pm.fan_pulses_per_revolution) { 2294 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2295 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2296 } 2297 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2298 DRM_INFO("Internal thermal controller %s fan control\n", 2299 (controller->ucFanParameters & 2300 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2301 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2302 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2303 DRM_INFO("Internal thermal controller %s fan control\n", 2304 (controller->ucFanParameters & 2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2306 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2307 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2308 DRM_INFO("Internal thermal controller %s fan control\n", 2309 (controller->ucFanParameters & 2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2311 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2312 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2313 DRM_INFO("Internal thermal controller %s fan control\n", 2314 (controller->ucFanParameters & 2315 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2316 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2317 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2318 DRM_INFO("Internal thermal controller %s fan control\n", 2319 (controller->ucFanParameters & 2320 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2321 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2322 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2323 DRM_INFO("Internal thermal controller %s fan control\n", 2324 (controller->ucFanParameters & 2325 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2326 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2327 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2328 DRM_INFO("Internal thermal controller %s fan control\n", 2329 (controller->ucFanParameters & 2330 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2331 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2332 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2333 DRM_INFO("Internal thermal controller %s fan control\n", 2334 (controller->ucFanParameters & 2335 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2336 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2337 } else if (controller->ucType == 2338 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2339 DRM_INFO("External GPIO thermal controller %s fan control\n", 2340 (controller->ucFanParameters & 2341 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2342 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2343 } else if (controller->ucType == 2344 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2345 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2346 (controller->ucFanParameters & 2347 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2348 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2349 } else if (controller->ucType == 2350 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2351 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2352 (controller->ucFanParameters & 2353 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2354 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2355 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2356 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2357 pp_lib_thermal_controller_names[controller->ucType], 2358 controller->ucI2cAddress >> 1, 2359 (controller->ucFanParameters & 2360 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2361 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2362 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2363 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2364#ifdef notyet 2365 if (rdev->pm.i2c_bus) { 2366 struct i2c_board_info info = { }; 2367 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2368 info.addr = controller->ucI2cAddress >> 1; 2369 strscpy(info.type, name, sizeof(info.type)); 2370 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2371 } 2372#endif 2373 } else { 2374 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2375 controller->ucType, 2376 controller->ucI2cAddress >> 1, 2377 (controller->ucFanParameters & 2378 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2379 } 2380 } 2381} 2382 2383void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2384 u16 *vddc, u16 *vddci, u16 *mvdd) 2385{ 2386 struct radeon_mode_info *mode_info = &rdev->mode_info; 2387 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2388 u8 frev, crev; 2389 u16 data_offset; 2390 union firmware_info *firmware_info; 2391 2392 *vddc = 0; 2393 *vddci = 0; 2394 *mvdd = 0; 2395 2396 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2397 &frev, &crev, &data_offset)) { 2398 firmware_info = 2399 (union firmware_info *)(mode_info->atom_context->bios + 2400 data_offset); 2401 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2402 if ((frev == 2) && (crev >= 2)) { 2403 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2404 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2405 } 2406 } 2407} 2408 2409static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2410 int state_index, int mode_index, 2411 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2412{ 2413 int j; 2414 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2415 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2416 u16 vddc, vddci, mvdd; 2417 2418 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2419 2420 rdev->pm.power_state[state_index].misc = misc; 2421 rdev->pm.power_state[state_index].misc2 = misc2; 2422 rdev->pm.power_state[state_index].pcie_lanes = 2423 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2424 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2425 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2426 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2427 rdev->pm.power_state[state_index].type = 2428 POWER_STATE_TYPE_BATTERY; 2429 break; 2430 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2431 rdev->pm.power_state[state_index].type = 2432 POWER_STATE_TYPE_BALANCED; 2433 break; 2434 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2435 rdev->pm.power_state[state_index].type = 2436 POWER_STATE_TYPE_PERFORMANCE; 2437 break; 2438 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2439 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2440 rdev->pm.power_state[state_index].type = 2441 POWER_STATE_TYPE_PERFORMANCE; 2442 break; 2443 } 2444 rdev->pm.power_state[state_index].flags = 0; 2445 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2446 rdev->pm.power_state[state_index].flags |= 2447 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2448 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2449 rdev->pm.power_state[state_index].type = 2450 POWER_STATE_TYPE_DEFAULT; 2451 rdev->pm.default_power_state_index = state_index; 2452 rdev->pm.power_state[state_index].default_clock_mode = 2453 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2454 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2455 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2456 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2457 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2458 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2459 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2460 } else { 2461 u16 max_vddci = 0; 2462 2463 if (ASIC_IS_DCE4(rdev)) 2464 radeon_atom_get_max_voltage(rdev, 2465 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2466 &max_vddci); 2467 /* patch the table values with the default sclk/mclk from firmware info */ 2468 for (j = 0; j < mode_index; j++) { 2469 rdev->pm.power_state[state_index].clock_info[j].mclk = 2470 rdev->clock.default_mclk; 2471 rdev->pm.power_state[state_index].clock_info[j].sclk = 2472 rdev->clock.default_sclk; 2473 if (vddc) 2474 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2475 vddc; 2476 if (max_vddci) 2477 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2478 max_vddci; 2479 } 2480 } 2481 } 2482} 2483 2484static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2485 int state_index, int mode_index, 2486 union pplib_clock_info *clock_info) 2487{ 2488 u32 sclk, mclk; 2489 u16 vddc; 2490 2491 if (rdev->flags & RADEON_IS_IGP) { 2492 if (rdev->family >= CHIP_PALM) { 2493 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2494 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2495 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2496 } else { 2497 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2498 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2499 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2500 } 2501 } else if (rdev->family >= CHIP_BONAIRE) { 2502 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2503 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2504 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2505 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2506 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2509 VOLTAGE_NONE; 2510 } else if (rdev->family >= CHIP_TAHITI) { 2511 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2512 sclk |= clock_info->si.ucEngineClockHigh << 16; 2513 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2514 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2515 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2516 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2517 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2518 VOLTAGE_SW; 2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2520 le16_to_cpu(clock_info->si.usVDDC); 2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2522 le16_to_cpu(clock_info->si.usVDDCI); 2523 } else if (rdev->family >= CHIP_CEDAR) { 2524 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2525 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2526 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2527 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2528 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2529 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2530 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2531 VOLTAGE_SW; 2532 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2533 le16_to_cpu(clock_info->evergreen.usVDDC); 2534 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2535 le16_to_cpu(clock_info->evergreen.usVDDCI); 2536 } else { 2537 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2538 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2539 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2540 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2541 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2542 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2543 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2544 VOLTAGE_SW; 2545 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2546 le16_to_cpu(clock_info->r600.usVDDC); 2547 } 2548 2549 /* patch up vddc if necessary */ 2550 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2551 case ATOM_VIRTUAL_VOLTAGE_ID0: 2552 case ATOM_VIRTUAL_VOLTAGE_ID1: 2553 case ATOM_VIRTUAL_VOLTAGE_ID2: 2554 case ATOM_VIRTUAL_VOLTAGE_ID3: 2555 case ATOM_VIRTUAL_VOLTAGE_ID4: 2556 case ATOM_VIRTUAL_VOLTAGE_ID5: 2557 case ATOM_VIRTUAL_VOLTAGE_ID6: 2558 case ATOM_VIRTUAL_VOLTAGE_ID7: 2559 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2560 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2561 &vddc) == 0) 2562 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2563 break; 2564 default: 2565 break; 2566 } 2567 2568 if (rdev->flags & RADEON_IS_IGP) { 2569 /* skip invalid modes */ 2570 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2571 return false; 2572 } else { 2573 /* skip invalid modes */ 2574 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2575 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2576 return false; 2577 } 2578 return true; 2579} 2580 2581static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2582{ 2583 struct radeon_mode_info *mode_info = &rdev->mode_info; 2584 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2585 union pplib_power_state *power_state; 2586 int i, j; 2587 int state_index = 0, mode_index = 0; 2588 union pplib_clock_info *clock_info; 2589 bool valid; 2590 union power_info *power_info; 2591 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2592 u16 data_offset; 2593 u8 frev, crev; 2594 2595 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2596 &frev, &crev, &data_offset)) 2597 return state_index; 2598 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2599 2600 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2601 if (power_info->pplib.ucNumStates == 0) 2602 return state_index; 2603 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates, 2604 sizeof(struct radeon_power_state), 2605 GFP_KERNEL); 2606 if (!rdev->pm.power_state) 2607 return state_index; 2608 /* first mode is usually default, followed by low to high */ 2609 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2610 mode_index = 0; 2611 power_state = (union pplib_power_state *) 2612 (mode_info->atom_context->bios + data_offset + 2613 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2614 i * power_info->pplib.ucStateEntrySize); 2615 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2616 (mode_info->atom_context->bios + data_offset + 2617 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2618 (power_state->v1.ucNonClockStateIndex * 2619 power_info->pplib.ucNonClockSize)); 2620 rdev->pm.power_state[i].clock_info = 2621 kcalloc((power_info->pplib.ucStateEntrySize - 1) ? 2622 (power_info->pplib.ucStateEntrySize - 1) : 1, 2623 sizeof(struct radeon_pm_clock_info), 2624 GFP_KERNEL); 2625 if (!rdev->pm.power_state[i].clock_info) 2626 return state_index; 2627 if (power_info->pplib.ucStateEntrySize - 1) { 2628 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2629 clock_info = (union pplib_clock_info *) 2630 (mode_info->atom_context->bios + data_offset + 2631 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2632 (power_state->v1.ucClockStateIndices[j] * 2633 power_info->pplib.ucClockInfoSize)); 2634 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2635 state_index, mode_index, 2636 clock_info); 2637 if (valid) 2638 mode_index++; 2639 } 2640 } else { 2641 rdev->pm.power_state[state_index].clock_info[0].mclk = 2642 rdev->clock.default_mclk; 2643 rdev->pm.power_state[state_index].clock_info[0].sclk = 2644 rdev->clock.default_sclk; 2645 mode_index++; 2646 } 2647 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2648 if (mode_index) { 2649 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2650 non_clock_info); 2651 state_index++; 2652 } 2653 } 2654 /* if multiple clock modes, mark the lowest as no display */ 2655 for (i = 0; i < state_index; i++) { 2656 if (rdev->pm.power_state[i].num_clock_modes > 1) 2657 rdev->pm.power_state[i].clock_info[0].flags |= 2658 RADEON_PM_MODE_NO_DISPLAY; 2659 } 2660 /* first mode is usually default */ 2661 if (rdev->pm.default_power_state_index == -1) { 2662 rdev->pm.power_state[0].type = 2663 POWER_STATE_TYPE_DEFAULT; 2664 rdev->pm.default_power_state_index = 0; 2665 rdev->pm.power_state[0].default_clock_mode = 2666 &rdev->pm.power_state[0].clock_info[0]; 2667 } 2668 return state_index; 2669} 2670 2671static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2672{ 2673 struct radeon_mode_info *mode_info = &rdev->mode_info; 2674 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2675 union pplib_power_state *power_state; 2676 int i, j, non_clock_array_index, clock_array_index; 2677 int state_index = 0, mode_index = 0; 2678 union pplib_clock_info *clock_info; 2679 struct _StateArray *state_array; 2680 struct _ClockInfoArray *clock_info_array; 2681 struct _NonClockInfoArray *non_clock_info_array; 2682 bool valid; 2683 union power_info *power_info; 2684 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2685 u16 data_offset; 2686 u8 frev, crev; 2687 u8 *power_state_offset; 2688 2689 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2690 &frev, &crev, &data_offset)) 2691 return state_index; 2692 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2693 2694 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2695 state_array = (struct _StateArray *) 2696 (mode_info->atom_context->bios + data_offset + 2697 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2698 clock_info_array = (struct _ClockInfoArray *) 2699 (mode_info->atom_context->bios + data_offset + 2700 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2701 non_clock_info_array = (struct _NonClockInfoArray *) 2702 (mode_info->atom_context->bios + data_offset + 2703 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2704 if (state_array->ucNumEntries == 0) 2705 return state_index; 2706 rdev->pm.power_state = kcalloc(state_array->ucNumEntries, 2707 sizeof(struct radeon_power_state), 2708 GFP_KERNEL); 2709 if (!rdev->pm.power_state) 2710 return state_index; 2711 power_state_offset = (u8 *)state_array->states; 2712 for (i = 0; i < state_array->ucNumEntries; i++) { 2713 mode_index = 0; 2714 power_state = (union pplib_power_state *)power_state_offset; 2715 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2716 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2717 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2718 rdev->pm.power_state[i].clock_info = 2719 kcalloc(power_state->v2.ucNumDPMLevels ? 2720 power_state->v2.ucNumDPMLevels : 1, 2721 sizeof(struct radeon_pm_clock_info), 2722 GFP_KERNEL); 2723 if (!rdev->pm.power_state[i].clock_info) 2724 return state_index; 2725 if (power_state->v2.ucNumDPMLevels) { 2726 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2727 clock_array_index = power_state->v2.clockInfoIndex[j]; 2728 clock_info = (union pplib_clock_info *) 2729 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2730 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2731 state_index, mode_index, 2732 clock_info); 2733 if (valid) 2734 mode_index++; 2735 } 2736 } else { 2737 rdev->pm.power_state[state_index].clock_info[0].mclk = 2738 rdev->clock.default_mclk; 2739 rdev->pm.power_state[state_index].clock_info[0].sclk = 2740 rdev->clock.default_sclk; 2741 mode_index++; 2742 } 2743 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2744 if (mode_index) { 2745 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2746 non_clock_info); 2747 state_index++; 2748 } 2749 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2750 } 2751 /* if multiple clock modes, mark the lowest as no display */ 2752 for (i = 0; i < state_index; i++) { 2753 if (rdev->pm.power_state[i].num_clock_modes > 1) 2754 rdev->pm.power_state[i].clock_info[0].flags |= 2755 RADEON_PM_MODE_NO_DISPLAY; 2756 } 2757 /* first mode is usually default */ 2758 if (rdev->pm.default_power_state_index == -1) { 2759 rdev->pm.power_state[0].type = 2760 POWER_STATE_TYPE_DEFAULT; 2761 rdev->pm.default_power_state_index = 0; 2762 rdev->pm.power_state[0].default_clock_mode = 2763 &rdev->pm.power_state[0].clock_info[0]; 2764 } 2765 return state_index; 2766} 2767 2768void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2769{ 2770 struct radeon_mode_info *mode_info = &rdev->mode_info; 2771 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2772 u16 data_offset; 2773 u8 frev, crev; 2774 int state_index = 0; 2775 2776 rdev->pm.default_power_state_index = -1; 2777 2778 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2779 &frev, &crev, &data_offset)) { 2780 switch (frev) { 2781 case 1: 2782 case 2: 2783 case 3: 2784 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2785 break; 2786 case 4: 2787 case 5: 2788 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2789 break; 2790 case 6: 2791 state_index = radeon_atombios_parse_power_table_6(rdev); 2792 break; 2793 default: 2794 break; 2795 } 2796 } 2797 2798 if (state_index == 0) { 2799 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2800 if (rdev->pm.power_state) { 2801 rdev->pm.power_state[0].clock_info = 2802 kcalloc(1, 2803 sizeof(struct radeon_pm_clock_info), 2804 GFP_KERNEL); 2805 if (rdev->pm.power_state[0].clock_info) { 2806 /* add the default mode */ 2807 rdev->pm.power_state[state_index].type = 2808 POWER_STATE_TYPE_DEFAULT; 2809 rdev->pm.power_state[state_index].num_clock_modes = 1; 2810 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2811 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2812 rdev->pm.power_state[state_index].default_clock_mode = 2813 &rdev->pm.power_state[state_index].clock_info[0]; 2814 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2815 rdev->pm.power_state[state_index].pcie_lanes = 16; 2816 rdev->pm.default_power_state_index = state_index; 2817 rdev->pm.power_state[state_index].flags = 0; 2818 state_index++; 2819 } 2820 } 2821 } 2822 2823 rdev->pm.num_power_states = state_index; 2824 2825 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2826 rdev->pm.current_clock_mode_index = 0; 2827 if (rdev->pm.default_power_state_index >= 0) 2828 rdev->pm.current_vddc = 2829 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2830 else 2831 rdev->pm.current_vddc = 0; 2832} 2833 2834union get_clock_dividers { 2835 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2836 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2837 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2838 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2839 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2840 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2841 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2842}; 2843 2844int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2845 u8 clock_type, 2846 u32 clock, 2847 bool strobe_mode, 2848 struct atom_clock_dividers *dividers) 2849{ 2850 union get_clock_dividers args; 2851 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2852 u8 frev, crev; 2853 2854 memset(&args, 0, sizeof(args)); 2855 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2856 2857 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2858 return -EINVAL; 2859 2860 switch (crev) { 2861 case 1: 2862 /* r4xx, r5xx */ 2863 args.v1.ucAction = clock_type; 2864 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2865 2866 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2867 2868 dividers->post_div = args.v1.ucPostDiv; 2869 dividers->fb_div = args.v1.ucFbDiv; 2870 dividers->enable_post_div = true; 2871 break; 2872 case 2: 2873 case 3: 2874 case 5: 2875 /* r6xx, r7xx, evergreen, ni, si */ 2876 if (rdev->family <= CHIP_RV770) { 2877 args.v2.ucAction = clock_type; 2878 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2879 2880 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2881 2882 dividers->post_div = args.v2.ucPostDiv; 2883 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2884 dividers->ref_div = args.v2.ucAction; 2885 if (rdev->family == CHIP_RV770) { 2886 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2887 true : false; 2888 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2889 } else 2890 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2891 } else { 2892 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2893 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2894 2895 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2896 2897 dividers->post_div = args.v3.ucPostDiv; 2898 dividers->enable_post_div = (args.v3.ucCntlFlag & 2899 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2900 dividers->enable_dithen = (args.v3.ucCntlFlag & 2901 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2902 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2903 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2904 dividers->ref_div = args.v3.ucRefDiv; 2905 dividers->vco_mode = (args.v3.ucCntlFlag & 2906 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2907 } else { 2908 /* for SI we use ComputeMemoryClockParam for memory plls */ 2909 if (rdev->family >= CHIP_TAHITI) 2910 return -EINVAL; 2911 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2912 if (strobe_mode) 2913 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2914 2915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2916 2917 dividers->post_div = args.v5.ucPostDiv; 2918 dividers->enable_post_div = (args.v5.ucCntlFlag & 2919 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2920 dividers->enable_dithen = (args.v5.ucCntlFlag & 2921 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2922 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2923 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2924 dividers->ref_div = args.v5.ucRefDiv; 2925 dividers->vco_mode = (args.v5.ucCntlFlag & 2926 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2927 } 2928 } 2929 break; 2930 case 4: 2931 /* fusion */ 2932 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2933 2934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2935 2936 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2937 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2938 break; 2939 case 6: 2940 /* CI */ 2941 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2942 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2943 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2944 2945 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2946 2947 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2948 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2949 dividers->ref_div = args.v6_out.ucPllRefDiv; 2950 dividers->post_div = args.v6_out.ucPllPostDiv; 2951 dividers->flags = args.v6_out.ucPllCntlFlag; 2952 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2953 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2954 break; 2955 default: 2956 return -EINVAL; 2957 } 2958 return 0; 2959} 2960 2961int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2962 u32 clock, 2963 bool strobe_mode, 2964 struct atom_mpll_param *mpll_param) 2965{ 2966 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2967 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2968 u8 frev, crev; 2969 2970 memset(&args, 0, sizeof(args)); 2971 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2972 2973 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2974 return -EINVAL; 2975 2976 switch (frev) { 2977 case 2: 2978 switch (crev) { 2979 case 1: 2980 /* SI */ 2981 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2982 args.ucInputFlag = 0; 2983 if (strobe_mode) 2984 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2985 2986 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2987 2988 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2989 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2990 mpll_param->post_div = args.ucPostDiv; 2991 mpll_param->dll_speed = args.ucDllSpeed; 2992 mpll_param->bwcntl = args.ucBWCntl; 2993 mpll_param->vco_mode = 2994 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2995 mpll_param->yclk_sel = 2996 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2997 mpll_param->qdr = 2998 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2999 mpll_param->half_rate = 3000 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 3001 break; 3002 default: 3003 return -EINVAL; 3004 } 3005 break; 3006 default: 3007 return -EINVAL; 3008 } 3009 return 0; 3010} 3011 3012void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 3013{ 3014 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 3015 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 3016 3017 args.ucEnable = enable; 3018 3019 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3020} 3021 3022uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 3023{ 3024 GET_ENGINE_CLOCK_PS_ALLOCATION args; 3025 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 3026 3027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3028 return le32_to_cpu(args.ulReturnEngineClock); 3029} 3030 3031uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 3032{ 3033 GET_MEMORY_CLOCK_PS_ALLOCATION args; 3034 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 3035 3036 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3037 return le32_to_cpu(args.ulReturnMemoryClock); 3038} 3039 3040void radeon_atom_set_engine_clock(struct radeon_device *rdev, 3041 uint32_t eng_clock) 3042{ 3043 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3044 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3045 3046 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3047 3048 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3049} 3050 3051void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3052 uint32_t mem_clock) 3053{ 3054 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3055 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3056 3057 if (rdev->flags & RADEON_IS_IGP) 3058 return; 3059 3060 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3061 3062 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3063} 3064 3065void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3066 u32 eng_clock, u32 mem_clock) 3067{ 3068 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3069 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3070 u32 tmp; 3071 3072 memset(&args, 0, sizeof(args)); 3073 3074 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3075 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3076 3077 args.ulTargetEngineClock = cpu_to_le32(tmp); 3078 if (mem_clock) 3079 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3080 3081 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3082} 3083 3084void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3085 u32 mem_clock) 3086{ 3087 u32 args; 3088 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3089 3090 args = cpu_to_le32(mem_clock); /* 10 khz */ 3091 3092 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3093} 3094 3095void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3096 u32 mem_clock) 3097{ 3098 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3099 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3100 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3101 3102 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3103 3104 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3105} 3106 3107union set_voltage { 3108 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3109 struct _SET_VOLTAGE_PARAMETERS v1; 3110 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3111 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3112}; 3113 3114void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3115{ 3116 union set_voltage args; 3117 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3118 u8 frev, crev, volt_index = voltage_level; 3119 3120 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3121 return; 3122 3123 /* 0xff01 is a flag rather then an actual voltage */ 3124 if (voltage_level == 0xff01) 3125 return; 3126 3127 switch (crev) { 3128 case 1: 3129 args.v1.ucVoltageType = voltage_type; 3130 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3131 args.v1.ucVoltageIndex = volt_index; 3132 break; 3133 case 2: 3134 args.v2.ucVoltageType = voltage_type; 3135 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3136 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3137 break; 3138 case 3: 3139 args.v3.ucVoltageType = voltage_type; 3140 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3141 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3142 break; 3143 default: 3144 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3145 return; 3146 } 3147 3148 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3149} 3150 3151int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3152 u16 voltage_id, u16 *voltage) 3153{ 3154 union set_voltage args; 3155 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3156 u8 frev, crev; 3157 3158 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3159 return -EINVAL; 3160 3161 switch (crev) { 3162 case 1: 3163 return -EINVAL; 3164 case 2: 3165 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3166 args.v2.ucVoltageMode = 0; 3167 args.v2.usVoltageLevel = 0; 3168 3169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3170 3171 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3172 break; 3173 case 3: 3174 args.v3.ucVoltageType = voltage_type; 3175 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3176 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3177 3178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3179 3180 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3181 break; 3182 default: 3183 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3184 return -EINVAL; 3185 } 3186 3187 return 0; 3188} 3189 3190int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3191 u16 *voltage, 3192 u16 leakage_idx) 3193{ 3194 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3195} 3196 3197int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3198 u16 *leakage_id) 3199{ 3200 union set_voltage args; 3201 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3202 u8 frev, crev; 3203 3204 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3205 return -EINVAL; 3206 3207 switch (crev) { 3208 case 3: 3209 case 4: 3210 args.v3.ucVoltageType = 0; 3211 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3212 args.v3.usVoltageLevel = 0; 3213 3214 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3215 3216 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3217 break; 3218 default: 3219 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3220 return -EINVAL; 3221 } 3222 3223 return 0; 3224} 3225 3226int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3227 u16 *vddc, u16 *vddci, 3228 u16 virtual_voltage_id, 3229 u16 vbios_voltage_id) 3230{ 3231 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3232 u8 frev, crev; 3233 u16 data_offset, size; 3234 int i, j; 3235 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3236 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3237 3238 *vddc = 0; 3239 *vddci = 0; 3240 3241 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3242 &frev, &crev, &data_offset)) 3243 return -EINVAL; 3244 3245 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3246 (rdev->mode_info.atom_context->bios + data_offset); 3247 3248 switch (frev) { 3249 case 1: 3250 return -EINVAL; 3251 case 2: 3252 switch (crev) { 3253 case 1: 3254 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3255 return -EINVAL; 3256 leakage_bin = (u16 *) 3257 (rdev->mode_info.atom_context->bios + data_offset + 3258 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3259 vddc_id_buf = (u16 *) 3260 (rdev->mode_info.atom_context->bios + data_offset + 3261 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3262 vddc_buf = (u16 *) 3263 (rdev->mode_info.atom_context->bios + data_offset + 3264 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3265 vddci_id_buf = (u16 *) 3266 (rdev->mode_info.atom_context->bios + data_offset + 3267 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3268 vddci_buf = (u16 *) 3269 (rdev->mode_info.atom_context->bios + data_offset + 3270 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3271 3272 if (profile->ucElbVDDC_Num > 0) { 3273 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3274 if (vddc_id_buf[i] == virtual_voltage_id) { 3275 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3276 if (vbios_voltage_id <= leakage_bin[j]) { 3277 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3278 break; 3279 } 3280 } 3281 break; 3282 } 3283 } 3284 } 3285 if (profile->ucElbVDDCI_Num > 0) { 3286 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3287 if (vddci_id_buf[i] == virtual_voltage_id) { 3288 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3289 if (vbios_voltage_id <= leakage_bin[j]) { 3290 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3291 break; 3292 } 3293 } 3294 break; 3295 } 3296 } 3297 } 3298 break; 3299 default: 3300 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3301 return -EINVAL; 3302 } 3303 break; 3304 default: 3305 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3306 return -EINVAL; 3307 } 3308 3309 return 0; 3310} 3311 3312union get_voltage_info { 3313 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3314 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3315}; 3316 3317int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3318 u16 virtual_voltage_id, 3319 u16 *voltage) 3320{ 3321 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3322 u32 entry_id; 3323 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3324 union get_voltage_info args; 3325 3326 for (entry_id = 0; entry_id < count; entry_id++) { 3327 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3328 virtual_voltage_id) 3329 break; 3330 } 3331 3332 if (entry_id >= count) 3333 return -EINVAL; 3334 3335 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3336 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3337 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3338 args.in.ulSCLKFreq = 3339 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3340 3341 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3342 3343 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3344 3345 return 0; 3346} 3347 3348int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3349 u16 voltage_level, u8 voltage_type, 3350 u32 *gpio_value, u32 *gpio_mask) 3351{ 3352 union set_voltage args; 3353 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3354 u8 frev, crev; 3355 3356 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3357 return -EINVAL; 3358 3359 switch (crev) { 3360 case 1: 3361 return -EINVAL; 3362 case 2: 3363 args.v2.ucVoltageType = voltage_type; 3364 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3365 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3366 3367 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3368 3369 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3370 3371 args.v2.ucVoltageType = voltage_type; 3372 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3373 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3374 3375 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3376 3377 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3378 break; 3379 default: 3380 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3381 return -EINVAL; 3382 } 3383 3384 return 0; 3385} 3386 3387union voltage_object_info { 3388 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3389 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3390 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3391}; 3392 3393union voltage_object { 3394 struct _ATOM_VOLTAGE_OBJECT v1; 3395 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3396 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3397}; 3398 3399static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3400 u8 voltage_type) 3401{ 3402 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3403 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3404 u8 *start = (u8 *)v1; 3405 3406 while (offset < size) { 3407 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3408 if (vo->ucVoltageType == voltage_type) 3409 return vo; 3410 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3411 vo->asFormula.ucNumOfVoltageEntries; 3412 } 3413 return NULL; 3414} 3415 3416static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3417 u8 voltage_type) 3418{ 3419 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3420 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3421 u8 *start = (u8 *)v2; 3422 3423 while (offset < size) { 3424 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3425 if (vo->ucVoltageType == voltage_type) 3426 return vo; 3427 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3428 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3429 } 3430 return NULL; 3431} 3432 3433static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3434 u8 voltage_type, u8 voltage_mode) 3435{ 3436 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3437 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3438 u8 *start = (u8 *)v3; 3439 3440 while (offset < size) { 3441 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3442 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3443 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3444 return vo; 3445 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3446 } 3447 return NULL; 3448} 3449 3450bool 3451radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3452 u8 voltage_type, u8 voltage_mode) 3453{ 3454 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3455 u8 frev, crev; 3456 u16 data_offset, size; 3457 union voltage_object_info *voltage_info; 3458 union voltage_object *voltage_object = NULL; 3459 3460 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3461 &frev, &crev, &data_offset)) { 3462 voltage_info = (union voltage_object_info *) 3463 (rdev->mode_info.atom_context->bios + data_offset); 3464 3465 switch (frev) { 3466 case 1: 3467 case 2: 3468 switch (crev) { 3469 case 1: 3470 voltage_object = (union voltage_object *) 3471 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3472 if (voltage_object && 3473 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3474 return true; 3475 break; 3476 case 2: 3477 voltage_object = (union voltage_object *) 3478 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3479 if (voltage_object && 3480 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3481 return true; 3482 break; 3483 default: 3484 DRM_ERROR("unknown voltage object table\n"); 3485 return false; 3486 } 3487 break; 3488 case 3: 3489 switch (crev) { 3490 case 1: 3491 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3492 voltage_type, voltage_mode)) 3493 return true; 3494 break; 3495 default: 3496 DRM_ERROR("unknown voltage object table\n"); 3497 return false; 3498 } 3499 break; 3500 default: 3501 DRM_ERROR("unknown voltage object table\n"); 3502 return false; 3503 } 3504 3505 } 3506 return false; 3507} 3508 3509int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3510 u8 voltage_type, 3511 u8 *svd_gpio_id, u8 *svc_gpio_id) 3512{ 3513 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3514 u8 frev, crev; 3515 u16 data_offset, size; 3516 union voltage_object_info *voltage_info; 3517 union voltage_object *voltage_object = NULL; 3518 3519 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3520 &frev, &crev, &data_offset)) { 3521 voltage_info = (union voltage_object_info *) 3522 (rdev->mode_info.atom_context->bios + data_offset); 3523 3524 switch (frev) { 3525 case 3: 3526 switch (crev) { 3527 case 1: 3528 voltage_object = (union voltage_object *) 3529 atom_lookup_voltage_object_v3(&voltage_info->v3, 3530 voltage_type, 3531 VOLTAGE_OBJ_SVID2); 3532 if (voltage_object) { 3533 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3534 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3535 } else { 3536 return -EINVAL; 3537 } 3538 break; 3539 default: 3540 DRM_ERROR("unknown voltage object table\n"); 3541 return -EINVAL; 3542 } 3543 break; 3544 default: 3545 DRM_ERROR("unknown voltage object table\n"); 3546 return -EINVAL; 3547 } 3548 3549 } 3550 return 0; 3551} 3552 3553int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3554 u8 voltage_type, u16 *max_voltage) 3555{ 3556 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3557 u8 frev, crev; 3558 u16 data_offset, size; 3559 union voltage_object_info *voltage_info; 3560 union voltage_object *voltage_object = NULL; 3561 3562 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3563 &frev, &crev, &data_offset)) { 3564 voltage_info = (union voltage_object_info *) 3565 (rdev->mode_info.atom_context->bios + data_offset); 3566 3567 switch (crev) { 3568 case 1: 3569 voltage_object = (union voltage_object *) 3570 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3571 if (voltage_object) { 3572 ATOM_VOLTAGE_FORMULA *formula = 3573 &voltage_object->v1.asFormula; 3574 if (formula->ucFlag & 1) 3575 *max_voltage = 3576 le16_to_cpu(formula->usVoltageBaseLevel) + 3577 formula->ucNumOfVoltageEntries / 2 * 3578 le16_to_cpu(formula->usVoltageStep); 3579 else 3580 *max_voltage = 3581 le16_to_cpu(formula->usVoltageBaseLevel) + 3582 (formula->ucNumOfVoltageEntries - 1) * 3583 le16_to_cpu(formula->usVoltageStep); 3584 return 0; 3585 } 3586 break; 3587 case 2: 3588 voltage_object = (union voltage_object *) 3589 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3590 if (voltage_object) { 3591 ATOM_VOLTAGE_FORMULA_V2 *formula = 3592 &voltage_object->v2.asFormula; 3593 if (formula->ucNumOfVoltageEntries) { 3594 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3595 ((u8 *)&formula->asVIDAdjustEntries[0] + 3596 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3597 *max_voltage = 3598 le16_to_cpu(lut->usVoltageValue); 3599 return 0; 3600 } 3601 } 3602 break; 3603 default: 3604 DRM_ERROR("unknown voltage object table\n"); 3605 return -EINVAL; 3606 } 3607 3608 } 3609 return -EINVAL; 3610} 3611 3612int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3613 u8 voltage_type, u16 *min_voltage) 3614{ 3615 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3616 u8 frev, crev; 3617 u16 data_offset, size; 3618 union voltage_object_info *voltage_info; 3619 union voltage_object *voltage_object = NULL; 3620 3621 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3622 &frev, &crev, &data_offset)) { 3623 voltage_info = (union voltage_object_info *) 3624 (rdev->mode_info.atom_context->bios + data_offset); 3625 3626 switch (crev) { 3627 case 1: 3628 voltage_object = (union voltage_object *) 3629 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3630 if (voltage_object) { 3631 ATOM_VOLTAGE_FORMULA *formula = 3632 &voltage_object->v1.asFormula; 3633 *min_voltage = 3634 le16_to_cpu(formula->usVoltageBaseLevel); 3635 return 0; 3636 } 3637 break; 3638 case 2: 3639 voltage_object = (union voltage_object *) 3640 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3641 if (voltage_object) { 3642 ATOM_VOLTAGE_FORMULA_V2 *formula = 3643 &voltage_object->v2.asFormula; 3644 if (formula->ucNumOfVoltageEntries) { 3645 *min_voltage = 3646 le16_to_cpu(formula->asVIDAdjustEntries[ 3647 0 3648 ].usVoltageValue); 3649 return 0; 3650 } 3651 } 3652 break; 3653 default: 3654 DRM_ERROR("unknown voltage object table\n"); 3655 return -EINVAL; 3656 } 3657 3658 } 3659 return -EINVAL; 3660} 3661 3662int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3663 u8 voltage_type, u16 *voltage_step) 3664{ 3665 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3666 u8 frev, crev; 3667 u16 data_offset, size; 3668 union voltage_object_info *voltage_info; 3669 union voltage_object *voltage_object = NULL; 3670 3671 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3672 &frev, &crev, &data_offset)) { 3673 voltage_info = (union voltage_object_info *) 3674 (rdev->mode_info.atom_context->bios + data_offset); 3675 3676 switch (crev) { 3677 case 1: 3678 voltage_object = (union voltage_object *) 3679 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3680 if (voltage_object) { 3681 ATOM_VOLTAGE_FORMULA *formula = 3682 &voltage_object->v1.asFormula; 3683 if (formula->ucFlag & 1) 3684 *voltage_step = 3685 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3686 else 3687 *voltage_step = 3688 le16_to_cpu(formula->usVoltageStep); 3689 return 0; 3690 } 3691 break; 3692 case 2: 3693 return -EINVAL; 3694 default: 3695 DRM_ERROR("unknown voltage object table\n"); 3696 return -EINVAL; 3697 } 3698 3699 } 3700 return -EINVAL; 3701} 3702 3703int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3704 u8 voltage_type, 3705 u16 nominal_voltage, 3706 u16 *true_voltage) 3707{ 3708 u16 min_voltage, max_voltage, voltage_step; 3709 3710 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3711 return -EINVAL; 3712 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3713 return -EINVAL; 3714 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3715 return -EINVAL; 3716 3717 if (nominal_voltage <= min_voltage) 3718 *true_voltage = min_voltage; 3719 else if (nominal_voltage >= max_voltage) 3720 *true_voltage = max_voltage; 3721 else 3722 *true_voltage = min_voltage + 3723 ((nominal_voltage - min_voltage) / voltage_step) * 3724 voltage_step; 3725 3726 return 0; 3727} 3728 3729int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3730 u8 voltage_type, u8 voltage_mode, 3731 struct atom_voltage_table *voltage_table) 3732{ 3733 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3734 u8 frev, crev; 3735 u16 data_offset, size; 3736 int i, ret; 3737 union voltage_object_info *voltage_info; 3738 union voltage_object *voltage_object = NULL; 3739 3740 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3741 &frev, &crev, &data_offset)) { 3742 voltage_info = (union voltage_object_info *) 3743 (rdev->mode_info.atom_context->bios + data_offset); 3744 3745 switch (frev) { 3746 case 1: 3747 case 2: 3748 switch (crev) { 3749 case 1: 3750 DRM_ERROR("old table version %d, %d\n", frev, crev); 3751 return -EINVAL; 3752 case 2: 3753 voltage_object = (union voltage_object *) 3754 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3755 if (voltage_object) { 3756 ATOM_VOLTAGE_FORMULA_V2 *formula = 3757 &voltage_object->v2.asFormula; 3758 VOLTAGE_LUT_ENTRY *lut; 3759 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3760 return -EINVAL; 3761 lut = &formula->asVIDAdjustEntries[0]; 3762 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3763 voltage_table->entries[i].value = 3764 le16_to_cpu(lut->usVoltageValue); 3765 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3766 voltage_table->entries[i].value, 3767 voltage_type, 3768 &voltage_table->entries[i].smio_low, 3769 &voltage_table->mask_low); 3770 if (ret) 3771 return ret; 3772 lut = (VOLTAGE_LUT_ENTRY *) 3773 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3774 } 3775 voltage_table->count = formula->ucNumOfVoltageEntries; 3776 return 0; 3777 } 3778 break; 3779 default: 3780 DRM_ERROR("unknown voltage object table\n"); 3781 return -EINVAL; 3782 } 3783 break; 3784 case 3: 3785 switch (crev) { 3786 case 1: 3787 voltage_object = (union voltage_object *) 3788 atom_lookup_voltage_object_v3(&voltage_info->v3, 3789 voltage_type, voltage_mode); 3790 if (voltage_object) { 3791 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3792 &voltage_object->v3.asGpioVoltageObj; 3793 VOLTAGE_LUT_ENTRY_V2 *lut; 3794 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3795 return -EINVAL; 3796 lut = &gpio->asVolGpioLut[0]; 3797 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3798 voltage_table->entries[i].value = 3799 le16_to_cpu(lut->usVoltageValue); 3800 voltage_table->entries[i].smio_low = 3801 le32_to_cpu(lut->ulVoltageId); 3802 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3803 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3804 } 3805 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3806 voltage_table->count = gpio->ucGpioEntryNum; 3807 voltage_table->phase_delay = gpio->ucPhaseDelay; 3808 return 0; 3809 } 3810 break; 3811 default: 3812 DRM_ERROR("unknown voltage object table\n"); 3813 return -EINVAL; 3814 } 3815 break; 3816 default: 3817 DRM_ERROR("unknown voltage object table\n"); 3818 return -EINVAL; 3819 } 3820 } 3821 return -EINVAL; 3822} 3823 3824union vram_info { 3825 struct _ATOM_VRAM_INFO_V3 v1_3; 3826 struct _ATOM_VRAM_INFO_V4 v1_4; 3827 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3828}; 3829 3830int radeon_atom_get_memory_info(struct radeon_device *rdev, 3831 u8 module_index, struct atom_memory_info *mem_info) 3832{ 3833 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3834 u8 frev, crev, i; 3835 u16 data_offset, size; 3836 union vram_info *vram_info; 3837 3838 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3839 3840 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3841 &frev, &crev, &data_offset)) { 3842 vram_info = (union vram_info *) 3843 (rdev->mode_info.atom_context->bios + data_offset); 3844 switch (frev) { 3845 case 1: 3846 switch (crev) { 3847 case 3: 3848 /* r6xx */ 3849 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3850 ATOM_VRAM_MODULE_V3 *vram_module = 3851 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3852 3853 for (i = 0; i < module_index; i++) { 3854 if (le16_to_cpu(vram_module->usSize) == 0) 3855 return -EINVAL; 3856 vram_module = (ATOM_VRAM_MODULE_V3 *) 3857 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3858 } 3859 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3860 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3861 } else 3862 return -EINVAL; 3863 break; 3864 case 4: 3865 /* r7xx, evergreen */ 3866 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3867 ATOM_VRAM_MODULE_V4 *vram_module = 3868 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3869 3870 for (i = 0; i < module_index; i++) { 3871 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3872 return -EINVAL; 3873 vram_module = (ATOM_VRAM_MODULE_V4 *) 3874 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3875 } 3876 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3877 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3878 } else 3879 return -EINVAL; 3880 break; 3881 default: 3882 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3883 return -EINVAL; 3884 } 3885 break; 3886 case 2: 3887 switch (crev) { 3888 case 1: 3889 /* ni */ 3890 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3891 ATOM_VRAM_MODULE_V7 *vram_module = 3892 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3893 3894 for (i = 0; i < module_index; i++) { 3895 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3896 return -EINVAL; 3897 vram_module = (ATOM_VRAM_MODULE_V7 *) 3898 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3899 } 3900 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3901 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3902 } else 3903 return -EINVAL; 3904 break; 3905 default: 3906 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3907 return -EINVAL; 3908 } 3909 break; 3910 default: 3911 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3912 return -EINVAL; 3913 } 3914 return 0; 3915 } 3916 return -EINVAL; 3917} 3918 3919int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3920 bool gddr5, u8 module_index, 3921 struct atom_memory_clock_range_table *mclk_range_table) 3922{ 3923 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3924 u8 frev, crev, i; 3925 u16 data_offset, size; 3926 union vram_info *vram_info; 3927 u32 mem_timing_size = gddr5 ? 3928 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3929 3930 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3931 3932 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3933 &frev, &crev, &data_offset)) { 3934 vram_info = (union vram_info *) 3935 (rdev->mode_info.atom_context->bios + data_offset); 3936 switch (frev) { 3937 case 1: 3938 switch (crev) { 3939 case 3: 3940 DRM_ERROR("old table version %d, %d\n", frev, crev); 3941 return -EINVAL; 3942 case 4: 3943 /* r7xx, evergreen */ 3944 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3945 ATOM_VRAM_MODULE_V4 *vram_module = 3946 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3947 ATOM_MEMORY_TIMING_FORMAT *format; 3948 3949 for (i = 0; i < module_index; i++) { 3950 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3951 return -EINVAL; 3952 vram_module = (ATOM_VRAM_MODULE_V4 *) 3953 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3954 } 3955 mclk_range_table->num_entries = (u8) 3956 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3957 mem_timing_size); 3958 format = &vram_module->asMemTiming[0]; 3959 for (i = 0; i < mclk_range_table->num_entries; i++) { 3960 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3961 format = (ATOM_MEMORY_TIMING_FORMAT *) 3962 ((u8 *)format + mem_timing_size); 3963 } 3964 } else 3965 return -EINVAL; 3966 break; 3967 default: 3968 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3969 return -EINVAL; 3970 } 3971 break; 3972 case 2: 3973 DRM_ERROR("new table version %d, %d\n", frev, crev); 3974 return -EINVAL; 3975 default: 3976 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3977 return -EINVAL; 3978 } 3979 return 0; 3980 } 3981 return -EINVAL; 3982} 3983 3984#define MEM_ID_MASK 0xff000000 3985#define MEM_ID_SHIFT 24 3986#define CLOCK_RANGE_MASK 0x00ffffff 3987#define CLOCK_RANGE_SHIFT 0 3988#define LOW_NIBBLE_MASK 0xf 3989#define DATA_EQU_PREV 0 3990#define DATA_FROM_TABLE 4 3991 3992int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3993 u8 module_index, 3994 struct atom_mc_reg_table *reg_table) 3995{ 3996 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3997 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3998 u32 i = 0, j; 3999 u16 data_offset, size; 4000 union vram_info *vram_info; 4001 4002 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 4003 4004 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 4005 &frev, &crev, &data_offset)) { 4006 vram_info = (union vram_info *) 4007 (rdev->mode_info.atom_context->bios + data_offset); 4008 switch (frev) { 4009 case 1: 4010 DRM_ERROR("old table version %d, %d\n", frev, crev); 4011 return -EINVAL; 4012 case 2: 4013 switch (crev) { 4014 case 1: 4015 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 4016 ATOM_INIT_REG_BLOCK *reg_block = 4017 (ATOM_INIT_REG_BLOCK *) 4018 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 4019 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 4020 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4021 ((u8 *)reg_block + (2 * sizeof(u16)) + 4022 le16_to_cpu(reg_block->usRegIndexTblSize)); 4023 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 4024 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 4025 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 4026 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 4027 return -EINVAL; 4028 while (i < num_entries) { 4029 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 4030 break; 4031 reg_table->mc_reg_address[i].s1 = 4032 (u16)(le16_to_cpu(format->usRegIndex)); 4033 reg_table->mc_reg_address[i].pre_reg_data = 4034 (u8)(format->ucPreRegDataLength); 4035 i++; 4036 format = (ATOM_INIT_REG_INDEX_FORMAT *) 4037 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 4038 } 4039 reg_table->last = i; 4040 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4041 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 4042 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4043 >> MEM_ID_SHIFT); 4044 if (module_index == t_mem_id) { 4045 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4046 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4047 >> CLOCK_RANGE_SHIFT); 4048 for (i = 0, j = 1; i < reg_table->last; i++) { 4049 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4050 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4051 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4052 j++; 4053 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4054 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4055 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4056 } 4057 } 4058 num_ranges++; 4059 } 4060 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4061 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4062 } 4063 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4064 return -EINVAL; 4065 reg_table->num_entries = num_ranges; 4066 } else 4067 return -EINVAL; 4068 break; 4069 default: 4070 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4071 return -EINVAL; 4072 } 4073 break; 4074 default: 4075 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4076 return -EINVAL; 4077 } 4078 return 0; 4079 } 4080 return -EINVAL; 4081} 4082 4083void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4084{ 4085 struct radeon_device *rdev = dev->dev_private; 4086 uint32_t bios_2_scratch, bios_6_scratch; 4087 4088 if (rdev->family >= CHIP_R600) { 4089 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4090 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4091 } else { 4092 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4093 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4094 } 4095 4096 /* let the bios control the backlight */ 4097 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4098 4099 /* tell the bios not to handle mode switching */ 4100 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4101 4102 /* clear the vbios dpms state */ 4103 if (ASIC_IS_DCE4(rdev)) 4104 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4105 4106 if (rdev->family >= CHIP_R600) { 4107 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4108 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4109 } else { 4110 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4111 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4112 } 4113 4114} 4115 4116void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4117{ 4118 uint32_t scratch_reg; 4119 int i; 4120 4121 if (rdev->family >= CHIP_R600) 4122 scratch_reg = R600_BIOS_0_SCRATCH; 4123 else 4124 scratch_reg = RADEON_BIOS_0_SCRATCH; 4125 4126 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4127 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4128} 4129 4130void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4131{ 4132 uint32_t scratch_reg; 4133 int i; 4134 4135 if (rdev->family >= CHIP_R600) 4136 scratch_reg = R600_BIOS_0_SCRATCH; 4137 else 4138 scratch_reg = RADEON_BIOS_0_SCRATCH; 4139 4140 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4141 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4142} 4143 4144void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4145{ 4146 struct drm_device *dev = encoder->dev; 4147 struct radeon_device *rdev = dev->dev_private; 4148 uint32_t bios_6_scratch; 4149 4150 if (rdev->family >= CHIP_R600) 4151 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4152 else 4153 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4154 4155 if (lock) { 4156 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4157 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4158 } else { 4159 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4160 bios_6_scratch |= ATOM_S6_ACC_MODE; 4161 } 4162 4163 if (rdev->family >= CHIP_R600) 4164 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4165 else 4166 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4167} 4168 4169/* at some point we may want to break this out into individual functions */ 4170void 4171radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4172 struct drm_encoder *encoder, 4173 bool connected) 4174{ 4175 struct drm_device *dev = connector->dev; 4176 struct radeon_device *rdev = dev->dev_private; 4177 struct radeon_connector *radeon_connector = 4178 to_radeon_connector(connector); 4179 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4180 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4181 4182 if (rdev->family >= CHIP_R600) { 4183 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4184 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4185 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4186 } else { 4187 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4188 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4189 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4190 } 4191 4192 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4193 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4194 if (connected) { 4195 DRM_DEBUG_KMS("TV1 connected\n"); 4196 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4197 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4198 } else { 4199 DRM_DEBUG_KMS("TV1 disconnected\n"); 4200 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4201 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4202 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4203 } 4204 } 4205 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4206 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4207 if (connected) { 4208 DRM_DEBUG_KMS("CV connected\n"); 4209 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4210 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4211 } else { 4212 DRM_DEBUG_KMS("CV disconnected\n"); 4213 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4214 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4215 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4216 } 4217 } 4218 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4219 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4220 if (connected) { 4221 DRM_DEBUG_KMS("LCD1 connected\n"); 4222 bios_0_scratch |= ATOM_S0_LCD1; 4223 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4224 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4225 } else { 4226 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4227 bios_0_scratch &= ~ATOM_S0_LCD1; 4228 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4229 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4230 } 4231 } 4232 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4233 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4234 if (connected) { 4235 DRM_DEBUG_KMS("CRT1 connected\n"); 4236 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4237 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4238 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4239 } else { 4240 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4241 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4242 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4243 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4244 } 4245 } 4246 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4247 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4248 if (connected) { 4249 DRM_DEBUG_KMS("CRT2 connected\n"); 4250 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4251 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4252 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4253 } else { 4254 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4255 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4256 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4257 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4258 } 4259 } 4260 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4261 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4262 if (connected) { 4263 DRM_DEBUG_KMS("DFP1 connected\n"); 4264 bios_0_scratch |= ATOM_S0_DFP1; 4265 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4266 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4267 } else { 4268 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4269 bios_0_scratch &= ~ATOM_S0_DFP1; 4270 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4271 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4272 } 4273 } 4274 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4275 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4276 if (connected) { 4277 DRM_DEBUG_KMS("DFP2 connected\n"); 4278 bios_0_scratch |= ATOM_S0_DFP2; 4279 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4280 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4281 } else { 4282 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4283 bios_0_scratch &= ~ATOM_S0_DFP2; 4284 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4285 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4286 } 4287 } 4288 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4289 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4290 if (connected) { 4291 DRM_DEBUG_KMS("DFP3 connected\n"); 4292 bios_0_scratch |= ATOM_S0_DFP3; 4293 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4294 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4295 } else { 4296 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4297 bios_0_scratch &= ~ATOM_S0_DFP3; 4298 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4299 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4300 } 4301 } 4302 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4303 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4304 if (connected) { 4305 DRM_DEBUG_KMS("DFP4 connected\n"); 4306 bios_0_scratch |= ATOM_S0_DFP4; 4307 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4308 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4309 } else { 4310 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4311 bios_0_scratch &= ~ATOM_S0_DFP4; 4312 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4313 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4314 } 4315 } 4316 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4317 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4318 if (connected) { 4319 DRM_DEBUG_KMS("DFP5 connected\n"); 4320 bios_0_scratch |= ATOM_S0_DFP5; 4321 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4322 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4323 } else { 4324 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4325 bios_0_scratch &= ~ATOM_S0_DFP5; 4326 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4327 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4328 } 4329 } 4330 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4331 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4332 if (connected) { 4333 DRM_DEBUG_KMS("DFP6 connected\n"); 4334 bios_0_scratch |= ATOM_S0_DFP6; 4335 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4336 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4337 } else { 4338 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4339 bios_0_scratch &= ~ATOM_S0_DFP6; 4340 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4341 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4342 } 4343 } 4344 4345 if (rdev->family >= CHIP_R600) { 4346 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4347 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4348 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4349 } else { 4350 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4351 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4352 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4353 } 4354} 4355 4356void 4357radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4358{ 4359 struct drm_device *dev = encoder->dev; 4360 struct radeon_device *rdev = dev->dev_private; 4361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4362 uint32_t bios_3_scratch; 4363 4364 if (ASIC_IS_DCE4(rdev)) 4365 return; 4366 4367 if (rdev->family >= CHIP_R600) 4368 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4369 else 4370 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4371 4372 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4373 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4374 bios_3_scratch |= (crtc << 18); 4375 } 4376 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4377 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4378 bios_3_scratch |= (crtc << 24); 4379 } 4380 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4381 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4382 bios_3_scratch |= (crtc << 16); 4383 } 4384 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4385 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4386 bios_3_scratch |= (crtc << 20); 4387 } 4388 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4389 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4390 bios_3_scratch |= (crtc << 17); 4391 } 4392 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4393 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4394 bios_3_scratch |= (crtc << 19); 4395 } 4396 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4397 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4398 bios_3_scratch |= (crtc << 23); 4399 } 4400 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4401 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4402 bios_3_scratch |= (crtc << 25); 4403 } 4404 4405 if (rdev->family >= CHIP_R600) 4406 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4407 else 4408 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4409} 4410 4411void 4412radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4413{ 4414 struct drm_device *dev = encoder->dev; 4415 struct radeon_device *rdev = dev->dev_private; 4416 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4417 uint32_t bios_2_scratch; 4418 4419 if (ASIC_IS_DCE4(rdev)) 4420 return; 4421 4422 if (rdev->family >= CHIP_R600) 4423 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4424 else 4425 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4426 4427 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4428 if (on) 4429 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4430 else 4431 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4432 } 4433 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4434 if (on) 4435 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4436 else 4437 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4438 } 4439 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4440 if (on) 4441 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4442 else 4443 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4444 } 4445 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4446 if (on) 4447 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4448 else 4449 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4450 } 4451 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4452 if (on) 4453 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4454 else 4455 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4456 } 4457 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4458 if (on) 4459 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4460 else 4461 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4462 } 4463 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4464 if (on) 4465 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4466 else 4467 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4468 } 4469 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4470 if (on) 4471 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4472 else 4473 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4474 } 4475 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4476 if (on) 4477 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4478 else 4479 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4480 } 4481 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4482 if (on) 4483 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4484 else 4485 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4486 } 4487 4488 if (rdev->family >= CHIP_R600) 4489 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4490 else 4491 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4492} 4493