1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __SMU_V13_0_H__
24#define __SMU_V13_0_H__
25
26#include "amdgpu_smu.h"
27
28#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
29
30/* MP Apertures */
31#define MP0_Public			0x03800000
32#define MP0_SRAM			0x03900000
33#define MP1_Public			0x03b00000
34#define MP1_SRAM			0x03c00004
35
36/* address block */
37#define smnMP1_FIRMWARE_FLAGS		0x3010024
38#define smnMP1_V13_0_4_FIRMWARE_FLAGS	0x3010028
39#define smnMP0_FW_INTF			0x30101c0
40#define smnMP1_PUB_CTRL			0x3010b14
41
42#define TEMP_RANGE_MIN			(0)
43#define TEMP_RANGE_MAX			(80 * 1000)
44
45#define SMU13_TOOL_SIZE			0x19000
46
47#define MAX_DPM_LEVELS 16
48#define MAX_PCIE_CONF 3
49
50#define CTF_OFFSET_EDGE			5
51#define CTF_OFFSET_HOTSPOT		5
52#define CTF_OFFSET_MEM			5
53
54#define SMU_13_VCLK_SHIFT		16
55
56extern const int pmfw_decoded_link_speed[5];
57extern const int pmfw_decoded_link_width[7];
58
59#define DECODE_GEN_SPEED(gen_speed_idx)		(pmfw_decoded_link_speed[gen_speed_idx])
60#define DECODE_LANE_WIDTH(lane_width_idx)	(pmfw_decoded_link_width[lane_width_idx])
61
62struct smu_13_0_max_sustainable_clocks {
63	uint32_t display_clock;
64	uint32_t phy_clock;
65	uint32_t pixel_clock;
66	uint32_t uclock;
67	uint32_t dcef_clock;
68	uint32_t soc_clock;
69};
70
71struct smu_13_0_dpm_clk_level {
72	bool				enabled;
73	uint32_t			value;
74};
75
76struct smu_13_0_dpm_table {
77	uint32_t			min;        /* MHz */
78	uint32_t			max;        /* MHz */
79	uint32_t			count;
80	bool				is_fine_grained;
81	struct smu_13_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
82};
83
84struct smu_13_0_pcie_table {
85	uint8_t  pcie_gen[MAX_PCIE_CONF];
86	uint8_t  pcie_lane[MAX_PCIE_CONF];
87	uint16_t clk_freq[MAX_PCIE_CONF];
88	uint32_t num_of_link_levels;
89};
90
91struct smu_13_0_dpm_tables {
92	struct smu_13_0_dpm_table        soc_table;
93	struct smu_13_0_dpm_table        gfx_table;
94	struct smu_13_0_dpm_table        uclk_table;
95	struct smu_13_0_dpm_table        eclk_table;
96	struct smu_13_0_dpm_table        vclk_table;
97	struct smu_13_0_dpm_table        dclk_table;
98	struct smu_13_0_dpm_table        dcef_table;
99	struct smu_13_0_dpm_table        pixel_table;
100	struct smu_13_0_dpm_table        display_table;
101	struct smu_13_0_dpm_table        phy_table;
102	struct smu_13_0_dpm_table        fclk_table;
103	struct smu_13_0_pcie_table       pcie_table;
104};
105
106struct smu_13_0_dpm_context {
107	struct smu_13_0_dpm_tables  dpm_tables;
108	uint32_t                    workload_policy_mask;
109	uint32_t                    dcef_min_ds_clk;
110};
111
112enum smu_13_0_power_state {
113	SMU_13_0_POWER_STATE__D0 = 0,
114	SMU_13_0_POWER_STATE__D1,
115	SMU_13_0_POWER_STATE__D3, /* Sleep*/
116	SMU_13_0_POWER_STATE__D4, /* Hibernate*/
117	SMU_13_0_POWER_STATE__D5, /* Power off*/
118};
119
120struct smu_13_0_power_context {
121	uint32_t	power_source;
122	uint8_t		in_power_limit_boost_mode;
123	enum smu_13_0_power_state power_state;
124	atomic_t	throttle_status;
125};
126
127#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
128
129int smu_v13_0_init_microcode(struct smu_context *smu);
130
131void smu_v13_0_fini_microcode(struct smu_context *smu);
132
133int smu_v13_0_load_microcode(struct smu_context *smu);
134
135int smu_v13_0_init_smc_tables(struct smu_context *smu);
136
137int smu_v13_0_fini_smc_tables(struct smu_context *smu);
138
139int smu_v13_0_init_power(struct smu_context *smu);
140
141int smu_v13_0_fini_power(struct smu_context *smu);
142
143int smu_v13_0_check_fw_status(struct smu_context *smu);
144
145int smu_v13_0_setup_pptable(struct smu_context *smu);
146
147int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
148
149int smu_v13_0_check_fw_version(struct smu_context *smu);
150
151int smu_v13_0_set_driver_table_location(struct smu_context *smu);
152
153int smu_v13_0_set_tool_table_location(struct smu_context *smu);
154
155int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
156
157int smu_v13_0_system_features_control(struct smu_context *smu,
158				      bool en);
159
160int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
161
162int smu_v13_0_set_allowed_mask(struct smu_context *smu);
163
164int smu_v13_0_notify_display_change(struct smu_context *smu);
165
166int smu_v13_0_get_current_power_limit(struct smu_context *smu,
167				      uint32_t *power_limit);
168
169int smu_v13_0_set_power_limit(struct smu_context *smu,
170			      enum smu_ppt_limit_type limit_type,
171			      uint32_t limit);
172
173int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
174
175int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
176
177int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
178
179int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
180
181int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
182
183int
184smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
185					struct pp_display_clock_request
186					*clock_req);
187
188uint32_t
189smu_v13_0_get_fan_control_mode(struct smu_context *smu);
190
191int
192smu_v13_0_set_fan_control_mode(struct smu_context *smu,
193			       uint32_t mode);
194
195int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
196				uint32_t speed);
197
198int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
199				uint32_t speed);
200
201int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
202			      uint32_t pstate);
203
204int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
205
206int smu_v13_0_register_irq_handler(struct smu_context *smu);
207
208int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
209
210int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
211					       struct pp_smu_nv_clock_table *max_clocks);
212
213int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
214				      enum smu_baco_seq baco_seq);
215
216bool smu_v13_0_baco_is_support(struct smu_context *smu);
217
218enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
219
220int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
221
222int smu_v13_0_baco_enter(struct smu_context *smu);
223int smu_v13_0_baco_exit(struct smu_context *smu);
224
225int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
226				    uint32_t *min, uint32_t *max);
227
228int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
229					  uint32_t min, uint32_t max);
230
231int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
232					  enum smu_clk_type clk_type,
233					  uint32_t min,
234					  uint32_t max);
235
236int smu_v13_0_set_performance_level(struct smu_context *smu,
237				    enum amd_dpm_forced_level level);
238
239int smu_v13_0_set_power_source(struct smu_context *smu,
240			       enum smu_power_src_type power_src);
241
242int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
243				   enum smu_clk_type clk_type,
244				   struct smu_13_0_dpm_table *single_dpm_table);
245
246int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
247				    enum smu_clk_type clk_type, uint16_t level,
248				    uint32_t *value);
249
250int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
251
252int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
253
254int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
255
256int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
257
258int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
259			      bool enablement);
260
261int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
262			     uint64_t event_arg);
263
264int smu_v13_0_set_vcn_enable(struct smu_context *smu,
265			     bool enable);
266
267int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
268			      bool enable);
269
270int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
271
272int smu_v13_0_run_btc(struct smu_context *smu);
273
274int smu_v13_0_gpo_control(struct smu_context *smu,
275			  bool enablement);
276
277int smu_v13_0_deep_sleep_control(struct smu_context *smu,
278				 bool enablement);
279
280int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
281
282int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
283				enum PP_OD_DPM_TABLE_COMMAND type,
284				long input[],
285				uint32_t size);
286
287int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
288
289void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
290
291int smu_v13_0_mode1_reset(struct smu_context *smu);
292
293int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
294					void **table,
295					uint32_t *size,
296					uint32_t pptable_id);
297
298int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
299				     uint8_t pcie_gen_cap,
300				     uint8_t pcie_width_cap);
301
302#endif
303#endif
304