/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.h | 37 int pipe_cnt); 47 unsigned int pipe_cnt, 59 int pipe_cnt, 67 int pipe_cnt, 73 int pipe_cnt);
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H A D | dcn32_fpu.c | 265 int pipe_cnt, 280 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 314 * @pipe_cnt: [in] DML pipe count 323 int pipe_cnt) 337 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 339 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 341 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 343 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 522 * @pipe_cnt: number of DML pipes 542 unsigned int pipe_cnt, 262 dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 320 dcn32_helper_populate_phantom_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 537 dcn32_set_phantom_stream_timing(struct dc *dc, struct dc_state *context, struct pipe_ctx *ref_pipe, struct dc_stream_state *phantom_stream, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument 1147 dcn32_full_validate_bw_helper(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *vlevel, int *split, bool *merge, int *pipe_cnt) argument 1346 dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 1650 int pipe_cnt, i, pipe_idx; local 1959 dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 2938 dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 991 int pipe_cnt, i; local 995 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1002 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1003 pipes[pipe_cnt].dout.num_active_wb++; 1004 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1005 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1006 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1007 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1008 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1009 pipes[pipe_cnt] 1027 dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int i) argument 1134 dcn20_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 1313 int pipe_cnt, i; local 1729 int pipe_cnt, i, pipe_idx; local 2029 int pipe_cnt = 0; local 2154 uint32_t pipe_cnt; local 2200 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 2237 int pipe_cnt, i, pipe_idx; local 2324 int pipe_cnt = 0; local 2476 int pipe_cnt, i, j; local [all...] |
H A D | dcn20_fpu.h | 38 int pipe_cnt, int i); 42 int pipe_cnt,
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.h | 41 int pipe_cnt, 49 int pipe_cnt, 69 int pipe_cnt,
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H A D | dcn30_fpu.c | 260 int pipe_cnt, i, j; local 267 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 275 pipes[pipe_cnt].dout.wb_enable = 0; 276 pipes[pipe_cnt].dout.num_active_wb = 0; 282 pipes[pipe_cnt].dout.wb_enable = 1; 283 pipes[pipe_cnt].dout.num_active_wb++; 326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 333 pipes[pipe_cnt].pipe.dest.htotal, 338 pipes[pipe_cnt].dout.wb = dout_wb; 343 pipe_cnt 347 dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt, int cur_pipe) argument 379 dcn30_fpu_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 691 dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.h | 40 int pipe_cnt,
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H A D | dcn301_fpu.c | 297 int pipe_cnt) 311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 312 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 317 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 318 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 415 int pipe_cnt, 292 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 412 dcn301_calculate_wm_and_dlg_fp(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel_req) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.c | 311 int i, pipe_cnt; local 321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; 340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 346 pipes[pipe_cnt].pipe.dest.vblank_nom = 347 max(pipes[pipe_cnt] [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.h | 35 int pipe_cnt); 43 int pipe_cnt,
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H A D | dcn31_fpu.c | 446 int pipe_cnt) 450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 485 int pipe_cnt, 500 if (pipe_cnt == 0) { 515 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 516 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 517 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 518 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 519 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 100 445 dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 482 dcn31_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/ |
H A D | dcn30_resource.h | 52 int pipe_cnt); 72 int pipe_cnt, 106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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H A D | dcn30_resource.c | 1322 int i, pipe_cnt; local 1329 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1333 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = 1337 return pipe_cnt; 1375 int pipe_cnt) 1405 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); 1639 int pipe_cnt, i, pipe_idx, vlevel; local 1650 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1652 if (!pipe_cnt) { 1657 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1371 dcn30_set_mcif_arb_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 2022 dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 2042 int pipe_cnt = 0; local [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn31/ |
H A D | dcn31_resource.h | 46 int pipe_cnt, 60 int pipe_cnt);
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H A D | dcn31_resource.c | 1618 uint32_t pipe_cnt; local 1623 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1625 for (i = 0; i < pipe_cnt; i++) { 1628 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1635 return pipe_cnt; 1643 int i, pipe_cnt; local 1652 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1669 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1670 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1671 pipes[pipe_cnt] 1720 dcn31_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 1742 dcn31_set_mcif_arb_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 1761 int pipe_cnt = 0; local [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn315/ |
H A D | dcn315_resource.c | 1661 int i, pipe_cnt, crb_idx, crb_pipes; local 1672 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { 1685 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1687 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1688 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1689 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1690 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1692 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1694 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); 1709 pipes[pipe_cnt] [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/ |
H A D | display_mode_lib.h | 106 int pipe_cnt);
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H A D | display_mode_lib.c | 163 int pipe_cnt) 173 for (i = 0; i < pipe_cnt; i++) { 160 dml_log_pipe_params( struct display_mode_lib *mode_lib, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/ |
H A D | dcn32_resource.c | 1677 unsigned int pipe_cnt, 1696 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); 1779 unsigned int pipe_cnt, 1788 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); 1817 int pipe_cnt = 0; local 1846 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 1852 if (pipe_cnt == 0) 1865 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1893 int i, pipe_cnt; local 1909 for (i = 0, pipe_cnt 1674 dcn32_enable_phantom_stream(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument 1777 dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int index) argument 2016 dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
H A D | dcn32_resource_helpers.c | 289 uint8_t pipe_cnt = 0; local 339 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 342 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; 343 pipe_cnt++; 354 int i, pipe_cnt; local 359 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 365 pipe_cnt++; 372 if (pipe_cnt == 1) {
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn316/ |
H A D | dcn316_resource.c | 1614 int i, pipe_cnt; local 1623 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1636 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1638 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1639 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1640 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1641 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1643 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1646 if (pipes[pipe_cnt].dout.dsc_enable) { 1649 pipes[pipe_cnt] [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/ |
H A D | core_types.h | 87 int pipe_cnt, 164 int pipe_cnt); 189 unsigned int pipe_cnt,
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/ |
H A D | dcn20_resource.h | 119 int pipe_cnt);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn314/ |
H A D | dcn314_resource.c | 1685 int pipe_cnt; local 1688 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate); 1691 return pipe_cnt; 1738 int pipe_cnt = 0; local 1749 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); 1753 if (pipe_cnt == 0) 1766 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn21/ |
H A D | dcn21_resource.c | 803 int pipe_cnt, i, pipe_idx, vlevel; local 812 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 815 *pipe_cnt_out = pipe_cnt; 817 if (!pipe_cnt) { 828 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 840 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
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