1/* 2* Copyright 2018 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27#include <linux/slab.h> 28 29#include "dm_services.h" 30#include "dc.h" 31 32#include "dcn21_init.h" 33 34#include "resource.h" 35#include "include/irq_service_interface.h" 36#include "dcn20/dcn20_resource.h" 37#include "dcn21/dcn21_resource.h" 38 39#include "dml/dcn20/dcn20_fpu.h" 40 41#include "clk_mgr.h" 42#include "dcn10/dcn10_hubp.h" 43#include "dcn10/dcn10_ipp.h" 44#include "dcn20/dcn20_hubbub.h" 45#include "dcn20/dcn20_mpc.h" 46#include "dcn20/dcn20_hubp.h" 47#include "dcn21_hubp.h" 48#include "irq/dcn21/irq_service_dcn21.h" 49#include "dcn20/dcn20_dpp.h" 50#include "dcn20/dcn20_optc.h" 51#include "dcn21/dcn21_hwseq.h" 52#include "dce110/dce110_hw_sequencer.h" 53#include "dcn20/dcn20_opp.h" 54#include "dcn20/dcn20_dsc.h" 55#include "dcn21/dcn21_link_encoder.h" 56#include "dcn20/dcn20_stream_encoder.h" 57#include "dce/dce_clock_source.h" 58#include "dce/dce_audio.h" 59#include "dce/dce_hwseq.h" 60#include "virtual/virtual_stream_encoder.h" 61#include "dml/display_mode_vba.h" 62#include "dcn20/dcn20_dccg.h" 63#include "dcn21/dcn21_dccg.h" 64#include "dcn21_hubbub.h" 65#include "dcn10/dcn10_resource.h" 66#include "dce/dce_panel_cntl.h" 67 68#include "dcn20/dcn20_dwb.h" 69#include "dcn20/dcn20_mmhubbub.h" 70#include "dpcs/dpcs_2_1_0_offset.h" 71#include "dpcs/dpcs_2_1_0_sh_mask.h" 72 73#include "renoir_ip_offset.h" 74#include "dcn/dcn_2_1_0_offset.h" 75#include "dcn/dcn_2_1_0_sh_mask.h" 76 77#include "nbio/nbio_7_0_offset.h" 78 79#include "mmhub/mmhub_2_0_0_offset.h" 80#include "mmhub/mmhub_2_0_0_sh_mask.h" 81 82#include "reg_helper.h" 83#include "dce/dce_abm.h" 84#include "dce/dce_dmcu.h" 85#include "dce/dce_aux.h" 86#include "dce/dce_i2c.h" 87#include "dcn21_resource.h" 88#include "vm_helper.h" 89#include "dcn20/dcn20_vmid.h" 90#include "dce/dmub_psr.h" 91#include "dce/dmub_abm.h" 92 93/* begin ********************* 94 * macros to expend register list macro defined in HW object header file */ 95 96/* DCN */ 97#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 98 99#define BASE(seg) BASE_INNER(seg) 100 101#define SR(reg_name)\ 102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 103 mm ## reg_name 104 105#define SRI(reg_name, block, id)\ 106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 107 mm ## block ## id ## _ ## reg_name 108 109#define SRIR(var_name, reg_name, block, id)\ 110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 111 mm ## block ## id ## _ ## reg_name 112 113#define SRII(reg_name, block, id)\ 114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 115 mm ## block ## id ## _ ## reg_name 116 117#define DCCG_SRII(reg_name, block, id)\ 118 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 119 mm ## block ## id ## _ ## reg_name 120 121#define VUPDATE_SRII(reg_name, block, id)\ 122 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 123 mm ## reg_name ## _ ## block ## id 124 125/* NBIO */ 126#define NBIO_BASE_INNER(seg) \ 127 NBIF0_BASE__INST0_SEG ## seg 128 129#define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132#define NBIO_SR(reg_name)\ 133 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 134 mm ## reg_name 135 136/* MMHUB */ 137#define MMHUB_BASE_INNER(seg) \ 138 MMHUB_BASE__INST0_SEG ## seg 139 140#define MMHUB_BASE(seg) \ 141 MMHUB_BASE_INNER(seg) 142 143#define MMHUB_SR(reg_name)\ 144 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 145 mmMM ## reg_name 146 147#define clk_src_regs(index, pllid)\ 148[index] = {\ 149 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\ 150} 151 152static const struct dce110_clk_src_regs clk_src_regs[] = { 153 clk_src_regs(0, A), 154 clk_src_regs(1, B), 155 clk_src_regs(2, C), 156 clk_src_regs(3, D), 157 clk_src_regs(4, E), 158}; 159 160static const struct dce110_clk_src_shift cs_shift = { 161 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 162}; 163 164static const struct dce110_clk_src_mask cs_mask = { 165 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 166}; 167 168static const struct bios_registers bios_regs = { 169 NBIO_SR(BIOS_SCRATCH_3), 170 NBIO_SR(BIOS_SCRATCH_6) 171}; 172 173static const struct dce_dmcu_registers dmcu_regs = { 174 DMCU_DCN20_REG_LIST() 175}; 176 177static const struct dce_dmcu_shift dmcu_shift = { 178 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 179}; 180 181static const struct dce_dmcu_mask dmcu_mask = { 182 DMCU_MASK_SH_LIST_DCN10(_MASK) 183}; 184 185static const struct dce_abm_registers abm_regs = { 186 ABM_DCN20_REG_LIST() 187}; 188 189static const struct dce_abm_shift abm_shift = { 190 ABM_MASK_SH_LIST_DCN20(__SHIFT) 191}; 192 193static const struct dce_abm_mask abm_mask = { 194 ABM_MASK_SH_LIST_DCN20(_MASK) 195}; 196 197#define audio_regs(id)\ 198[id] = {\ 199 AUD_COMMON_REG_LIST(id)\ 200} 201 202static const struct dce_audio_registers audio_regs[] = { 203 audio_regs(0), 204 audio_regs(1), 205 audio_regs(2), 206 audio_regs(3), 207 audio_regs(4), 208 audio_regs(5), 209}; 210 211#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 212 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 213 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 214 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 215 216static const struct dce_audio_shift audio_shift = { 217 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 218}; 219 220static const struct dce_audio_mask audio_mask = { 221 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 222}; 223 224static const struct dccg_registers dccg_regs = { 225 DCCG_COMMON_REG_LIST_DCN_BASE() 226}; 227 228static const struct dccg_shift dccg_shift = { 229 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT) 230}; 231 232static const struct dccg_mask dccg_mask = { 233 DCCG_MASK_SH_LIST_DCN2_1(_MASK) 234}; 235 236#define opp_regs(id)\ 237[id] = {\ 238 OPP_REG_LIST_DCN20(id),\ 239} 240 241static const struct dcn20_opp_registers opp_regs[] = { 242 opp_regs(0), 243 opp_regs(1), 244 opp_regs(2), 245 opp_regs(3), 246 opp_regs(4), 247 opp_regs(5), 248}; 249 250static const struct dcn20_opp_shift opp_shift = { 251 OPP_MASK_SH_LIST_DCN20(__SHIFT) 252}; 253 254static const struct dcn20_opp_mask opp_mask = { 255 OPP_MASK_SH_LIST_DCN20(_MASK) 256}; 257 258#define tg_regs(id)\ 259[id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 260 261static const struct dcn_optc_registers tg_regs[] = { 262 tg_regs(0), 263 tg_regs(1), 264 tg_regs(2), 265 tg_regs(3) 266}; 267 268static const struct dcn_optc_shift tg_shift = { 269 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 270}; 271 272static const struct dcn_optc_mask tg_mask = { 273 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 274}; 275 276static const struct dcn20_mpc_registers mpc_regs = { 277 MPC_REG_LIST_DCN2_0(0), 278 MPC_REG_LIST_DCN2_0(1), 279 MPC_REG_LIST_DCN2_0(2), 280 MPC_REG_LIST_DCN2_0(3), 281 MPC_REG_LIST_DCN2_0(4), 282 MPC_REG_LIST_DCN2_0(5), 283 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 284 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 285 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 286 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 287 MPC_DBG_REG_LIST_DCN2_0() 288}; 289 290static const struct dcn20_mpc_shift mpc_shift = { 291 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 292 MPC_DEBUG_REG_LIST_SH_DCN20 293}; 294 295static const struct dcn20_mpc_mask mpc_mask = { 296 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 297 MPC_DEBUG_REG_LIST_MASK_DCN20 298}; 299 300#define hubp_regs(id)\ 301[id] = {\ 302 HUBP_REG_LIST_DCN21(id)\ 303} 304 305static const struct dcn_hubp2_registers hubp_regs[] = { 306 hubp_regs(0), 307 hubp_regs(1), 308 hubp_regs(2), 309 hubp_regs(3) 310}; 311 312static const struct dcn_hubp2_shift hubp_shift = { 313 HUBP_MASK_SH_LIST_DCN21(__SHIFT) 314}; 315 316static const struct dcn_hubp2_mask hubp_mask = { 317 HUBP_MASK_SH_LIST_DCN21(_MASK) 318}; 319 320static const struct dcn_hubbub_registers hubbub_reg = { 321 HUBBUB_REG_LIST_DCN21() 322}; 323 324static const struct dcn_hubbub_shift hubbub_shift = { 325 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) 326}; 327 328static const struct dcn_hubbub_mask hubbub_mask = { 329 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 330}; 331 332 333#define vmid_regs(id)\ 334[id] = {\ 335 DCN20_VMID_REG_LIST(id)\ 336} 337 338static const struct dcn_vmid_registers vmid_regs[] = { 339 vmid_regs(0), 340 vmid_regs(1), 341 vmid_regs(2), 342 vmid_regs(3), 343 vmid_regs(4), 344 vmid_regs(5), 345 vmid_regs(6), 346 vmid_regs(7), 347 vmid_regs(8), 348 vmid_regs(9), 349 vmid_regs(10), 350 vmid_regs(11), 351 vmid_regs(12), 352 vmid_regs(13), 353 vmid_regs(14), 354 vmid_regs(15) 355}; 356 357static const struct dcn20_vmid_shift vmid_shifts = { 358 DCN20_VMID_MASK_SH_LIST(__SHIFT) 359}; 360 361static const struct dcn20_vmid_mask vmid_masks = { 362 DCN20_VMID_MASK_SH_LIST(_MASK) 363}; 364 365#define dsc_regsDCN20(id)\ 366[id] = {\ 367 DSC_REG_LIST_DCN20(id)\ 368} 369 370static const struct dcn20_dsc_registers dsc_regs[] = { 371 dsc_regsDCN20(0), 372 dsc_regsDCN20(1), 373 dsc_regsDCN20(2), 374 dsc_regsDCN20(3), 375 dsc_regsDCN20(4), 376 dsc_regsDCN20(5) 377}; 378 379static const struct dcn20_dsc_shift dsc_shift = { 380 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 381}; 382 383static const struct dcn20_dsc_mask dsc_mask = { 384 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 385}; 386 387#define ipp_regs(id)\ 388[id] = {\ 389 IPP_REG_LIST_DCN20(id),\ 390} 391 392static const struct dcn10_ipp_registers ipp_regs[] = { 393 ipp_regs(0), 394 ipp_regs(1), 395 ipp_regs(2), 396 ipp_regs(3), 397}; 398 399static const struct dcn10_ipp_shift ipp_shift = { 400 IPP_MASK_SH_LIST_DCN20(__SHIFT) 401}; 402 403static const struct dcn10_ipp_mask ipp_mask = { 404 IPP_MASK_SH_LIST_DCN20(_MASK), 405}; 406 407#define opp_regs(id)\ 408[id] = {\ 409 OPP_REG_LIST_DCN20(id),\ 410} 411 412 413#define aux_engine_regs(id)\ 414[id] = {\ 415 AUX_COMMON_REG_LIST0(id), \ 416 .AUXN_IMPCAL = 0, \ 417 .AUXP_IMPCAL = 0, \ 418 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 419} 420 421static const struct dce110_aux_registers aux_engine_regs[] = { 422 aux_engine_regs(0), 423 aux_engine_regs(1), 424 aux_engine_regs(2), 425 aux_engine_regs(3), 426 aux_engine_regs(4), 427}; 428 429#define tf_regs(id)\ 430[id] = {\ 431 TF_REG_LIST_DCN20(id),\ 432 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 433} 434 435static const struct dcn2_dpp_registers tf_regs[] = { 436 tf_regs(0), 437 tf_regs(1), 438 tf_regs(2), 439 tf_regs(3), 440}; 441 442static const struct dcn2_dpp_shift tf_shift = { 443 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 444 TF_DEBUG_REG_LIST_SH_DCN20 445}; 446 447static const struct dcn2_dpp_mask tf_mask = { 448 TF_REG_LIST_SH_MASK_DCN20(_MASK), 449 TF_DEBUG_REG_LIST_MASK_DCN20 450}; 451 452#define stream_enc_regs(id)\ 453[id] = {\ 454 SE_DCN2_REG_LIST(id)\ 455} 456 457static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 458 stream_enc_regs(0), 459 stream_enc_regs(1), 460 stream_enc_regs(2), 461 stream_enc_regs(3), 462 stream_enc_regs(4), 463}; 464 465static const struct dce110_aux_registers_shift aux_shift = { 466 DCN_AUX_MASK_SH_LIST(__SHIFT) 467}; 468 469static const struct dce110_aux_registers_mask aux_mask = { 470 DCN_AUX_MASK_SH_LIST(_MASK) 471}; 472 473static const struct dcn10_stream_encoder_shift se_shift = { 474 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 475}; 476 477static const struct dcn10_stream_encoder_mask se_mask = { 478 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 479}; 480 481static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 482 483static struct input_pixel_processor *dcn21_ipp_create( 484 struct dc_context *ctx, uint32_t inst) 485{ 486 struct dcn10_ipp *ipp = 487 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 488 489 if (!ipp) { 490 BREAK_TO_DEBUGGER(); 491 return NULL; 492 } 493 494 dcn20_ipp_construct(ipp, ctx, inst, 495 &ipp_regs[inst], &ipp_shift, &ipp_mask); 496 return &ipp->base; 497} 498 499static struct dpp *dcn21_dpp_create( 500 struct dc_context *ctx, 501 uint32_t inst) 502{ 503 struct dcn20_dpp *dpp = 504 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); 505 506 if (!dpp) 507 return NULL; 508 509 if (dpp2_construct(dpp, ctx, inst, 510 &tf_regs[inst], &tf_shift, &tf_mask)) 511 return &dpp->base; 512 513 BREAK_TO_DEBUGGER(); 514 kfree(dpp); 515 return NULL; 516} 517 518static struct dce_aux *dcn21_aux_engine_create( 519 struct dc_context *ctx, 520 uint32_t inst) 521{ 522 struct aux_engine_dce110 *aux_engine = 523 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 524 525 if (!aux_engine) 526 return NULL; 527 528 dce110_aux_engine_construct(aux_engine, ctx, inst, 529 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 530 &aux_engine_regs[inst], 531 &aux_mask, 532 &aux_shift, 533 ctx->dc->caps.extended_aux_timeout_support); 534 535 return &aux_engine->base; 536} 537 538#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 539 540static const struct dce_i2c_registers i2c_hw_regs[] = { 541 i2c_inst_regs(1), 542 i2c_inst_regs(2), 543 i2c_inst_regs(3), 544 i2c_inst_regs(4), 545 i2c_inst_regs(5), 546}; 547 548static const struct dce_i2c_shift i2c_shifts = { 549 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 550}; 551 552static const struct dce_i2c_mask i2c_masks = { 553 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 554}; 555 556static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx, 557 uint32_t inst) 558{ 559 struct dce_i2c_hw *dce_i2c_hw = 560 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 561 562 if (!dce_i2c_hw) 563 return NULL; 564 565 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 566 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 567 568 return dce_i2c_hw; 569} 570 571static const struct resource_caps res_cap_rn = { 572 .num_timing_generator = 4, 573 .num_opp = 4, 574 .num_video_plane = 4, 575 .num_audio = 4, // 4 audio endpoints. 4 audio streams 576 .num_stream_encoder = 5, 577 .num_pll = 5, // maybe 3 because the last two used for USB-c 578 .num_dwb = 1, 579 .num_ddc = 5, 580 .num_vmid = 16, 581 .num_dsc = 3, 582}; 583 584#ifdef DIAGS_BUILD 585static const struct resource_caps res_cap_rn_FPGA_4pipe = { 586 .num_timing_generator = 4, 587 .num_opp = 4, 588 .num_video_plane = 4, 589 .num_audio = 7, 590 .num_stream_encoder = 4, 591 .num_pll = 4, 592 .num_dwb = 1, 593 .num_ddc = 4, 594 .num_dsc = 0, 595}; 596 597static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = { 598 .num_timing_generator = 2, 599 .num_opp = 2, 600 .num_video_plane = 2, 601 .num_audio = 7, 602 .num_stream_encoder = 2, 603 .num_pll = 4, 604 .num_dwb = 1, 605 .num_ddc = 4, 606 .num_dsc = 2, 607}; 608#endif 609 610static const struct dc_plane_cap plane_cap = { 611 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 612 .per_pixel_alpha = true, 613 614 .pixel_format_support = { 615 .argb8888 = true, 616 .nv12 = true, 617 .fp16 = true, 618 .p010 = true 619 }, 620 621 .max_upscale_factor = { 622 .argb8888 = 16000, 623 .nv12 = 16000, 624 .fp16 = 16000 625 }, 626 627 .max_downscale_factor = { 628 .argb8888 = 250, 629 .nv12 = 250, 630 .fp16 = 250 631 }, 632 64, 633 64 634}; 635 636static const struct dc_debug_options debug_defaults_drv = { 637 .disable_dmcu = false, 638 .force_abm_enable = false, 639 .timing_trace = false, 640 .clock_trace = true, 641 .disable_pplib_clock_request = true, 642 .min_disp_clk_khz = 100000, 643 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 644 .force_single_disp_pipe_split = false, 645 .disable_dcc = DCC_ENABLE, 646 .vsr_support = true, 647 .performance_trace = false, 648 .max_downscale_src_width = 4096, 649 .disable_pplib_wm_range = false, 650 .scl_reset_length10 = true, 651 .sanity_checks = true, 652 .disable_48mhz_pwrdwn = false, 653 .usbc_combo_phy_reset_wa = true, 654 .dmub_command_table = true, 655 .use_max_lb = true, 656 .enable_legacy_fast_update = true, 657}; 658 659static const struct dc_panel_config panel_config_defaults = { 660 .psr = { 661 .disable_psr = false, 662 .disallow_psrsu = false, 663 .disallow_replay = false, 664 }, 665 .ilr = { 666 .optimize_edp_link_rate = true, 667 }, 668}; 669 670enum dcn20_clk_src_array_id { 671 DCN20_CLK_SRC_PLL0, 672 DCN20_CLK_SRC_PLL1, 673 DCN20_CLK_SRC_PLL2, 674 DCN20_CLK_SRC_PLL3, 675 DCN20_CLK_SRC_PLL4, 676 DCN20_CLK_SRC_TOTAL_DCN21 677}; 678 679static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) 680{ 681 unsigned int i; 682 683 for (i = 0; i < pool->base.stream_enc_count; i++) { 684 if (pool->base.stream_enc[i] != NULL) { 685 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 686 pool->base.stream_enc[i] = NULL; 687 } 688 } 689 690 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 691 if (pool->base.dscs[i] != NULL) 692 dcn20_dsc_destroy(&pool->base.dscs[i]); 693 } 694 695 if (pool->base.mpc != NULL) { 696 kfree(TO_DCN20_MPC(pool->base.mpc)); 697 pool->base.mpc = NULL; 698 } 699 if (pool->base.hubbub != NULL) { 700 kfree(pool->base.hubbub); 701 pool->base.hubbub = NULL; 702 } 703 for (i = 0; i < pool->base.pipe_count; i++) { 704 if (pool->base.dpps[i] != NULL) 705 dcn20_dpp_destroy(&pool->base.dpps[i]); 706 707 if (pool->base.ipps[i] != NULL) 708 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 709 710 if (pool->base.hubps[i] != NULL) { 711 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 712 pool->base.hubps[i] = NULL; 713 } 714 715 if (pool->base.irqs != NULL) { 716 dal_irq_service_destroy(&pool->base.irqs); 717 } 718 } 719 720 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 721 if (pool->base.engines[i] != NULL) 722 dce110_engine_destroy(&pool->base.engines[i]); 723 if (pool->base.hw_i2cs[i] != NULL) { 724 kfree(pool->base.hw_i2cs[i]); 725 pool->base.hw_i2cs[i] = NULL; 726 } 727 if (pool->base.sw_i2cs[i] != NULL) { 728 kfree(pool->base.sw_i2cs[i]); 729 pool->base.sw_i2cs[i] = NULL; 730 } 731 } 732 733 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 734 if (pool->base.opps[i] != NULL) 735 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 736 } 737 738 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 739 if (pool->base.timing_generators[i] != NULL) { 740 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 741 pool->base.timing_generators[i] = NULL; 742 } 743 } 744 745 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 746 if (pool->base.dwbc[i] != NULL) { 747 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 748 pool->base.dwbc[i] = NULL; 749 } 750 if (pool->base.mcif_wb[i] != NULL) { 751 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 752 pool->base.mcif_wb[i] = NULL; 753 } 754 } 755 756 for (i = 0; i < pool->base.audio_count; i++) { 757 if (pool->base.audios[i]) 758 dce_aud_destroy(&pool->base.audios[i]); 759 } 760 761 for (i = 0; i < pool->base.clk_src_count; i++) { 762 if (pool->base.clock_sources[i] != NULL) { 763 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 764 pool->base.clock_sources[i] = NULL; 765 } 766 } 767 768 if (pool->base.dp_clock_source != NULL) { 769 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 770 pool->base.dp_clock_source = NULL; 771 } 772 773 if (pool->base.abm != NULL) { 774 if (pool->base.abm->ctx->dc->config.disable_dmcu) 775 dmub_abm_destroy(&pool->base.abm); 776 else 777 dce_abm_destroy(&pool->base.abm); 778 } 779 780 if (pool->base.dmcu != NULL) 781 dce_dmcu_destroy(&pool->base.dmcu); 782 783 if (pool->base.psr != NULL) 784 dmub_psr_destroy(&pool->base.psr); 785 786 if (pool->base.dccg != NULL) 787 dcn_dccg_destroy(&pool->base.dccg); 788 789 if (pool->base.pp_smu != NULL) 790 dcn21_pp_smu_destroy(&pool->base.pp_smu); 791} 792 793bool dcn21_fast_validate_bw(struct dc *dc, 794 struct dc_state *context, 795 display_e2e_pipe_params_st *pipes, 796 int *pipe_cnt_out, 797 int *pipe_split_from, 798 int *vlevel_out, 799 bool fast_validate) 800{ 801 bool out = false; 802 int split[MAX_PIPES] = { 0 }; 803 int pipe_cnt, i, pipe_idx, vlevel; 804 805 ASSERT(pipes); 806 if (!pipes) 807 return false; 808 809 dcn20_merge_pipes_for_validate(dc, context); 810 811 DC_FP_START(); 812 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 813 DC_FP_END(); 814 815 *pipe_cnt_out = pipe_cnt; 816 817 if (!pipe_cnt) { 818 out = true; 819 goto validate_out; 820 } 821 /* 822 * DML favors voltage over p-state, but we're more interested in 823 * supporting p-state over voltage. We can't support p-state in 824 * prefetch mode > 0 so try capping the prefetch mode to start. 825 */ 826 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 827 dm_allow_self_refresh_and_mclk_switch; 828 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 829 830 if (vlevel > context->bw_ctx.dml.soc.num_states) { 831 /* 832 * If mode is unsupported or there's still no p-state support then 833 * fall back to favoring voltage. 834 * 835 * We don't actually support prefetch mode 2, so require that we 836 * at least support prefetch mode 1. 837 */ 838 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 839 dm_allow_self_refresh; 840 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 841 if (vlevel > context->bw_ctx.dml.soc.num_states) 842 goto validate_fail; 843 } 844 845 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 846 847 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 848 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 849 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 850 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 851 852 if (!pipe->stream) 853 continue; 854 855 /* We only support full screen mpo with ODM */ 856 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 857 && pipe->plane_state && mpo_pipe 858 && memcmp(&mpo_pipe->plane_state->clip_rect, 859 &pipe->stream->src, 860 sizeof(struct rect)) != 0) { 861 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 862 goto validate_fail; 863 } 864 pipe_idx++; 865 } 866 867 /*initialize pipe_just_split_from to invalid idx*/ 868 for (i = 0; i < MAX_PIPES; i++) 869 pipe_split_from[i] = -1; 870 871 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 872 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 873 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 874 875 if (!pipe->stream || pipe_split_from[i] >= 0) 876 continue; 877 878 pipe_idx++; 879 880 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 881 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 882 ASSERT(hsplit_pipe); 883 if (!dcn20_split_stream_for_odm( 884 dc, &context->res_ctx, 885 pipe, hsplit_pipe)) 886 goto validate_fail; 887 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 888 dcn20_build_mapped_resource(dc, context, pipe->stream); 889 } 890 891 if (!pipe->plane_state) 892 continue; 893 /* Skip 2nd half of already split pipe */ 894 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 895 continue; 896 897 if (split[i] == 2) { 898 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 899 /* pipe not split previously needs split */ 900 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 901 ASSERT(hsplit_pipe); 902 if (!hsplit_pipe) { 903 DC_FP_START(); 904 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); 905 DC_FP_END(); 906 continue; 907 } 908 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 909 if (!dcn20_split_stream_for_odm( 910 dc, &context->res_ctx, 911 pipe, hsplit_pipe)) 912 goto validate_fail; 913 dcn20_build_mapped_resource(dc, context, pipe->stream); 914 } else { 915 dcn20_split_stream_for_mpc( 916 &context->res_ctx, dc->res_pool, 917 pipe, hsplit_pipe); 918 resource_build_scaling_params(pipe); 919 resource_build_scaling_params(hsplit_pipe); 920 } 921 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 922 } 923 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 924 /* merge should already have been done */ 925 ASSERT(0); 926 } 927 } 928 /* Actual dsc count per stream dsc validation*/ 929 if (!dcn20_validate_dsc(dc, context)) { 930 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 931 DML_FAIL_DSC_VALIDATION_FAILURE; 932 goto validate_fail; 933 } 934 935 *vlevel_out = vlevel; 936 937 out = true; 938 goto validate_out; 939 940validate_fail: 941 out = false; 942 943validate_out: 944 return out; 945} 946 947/* 948 * Some of the functions further below use the FPU, so we need to wrap this 949 * with DC_FP_START()/DC_FP_END(). Use the same approach as for 950 * dcn20_validate_bandwidth in dcn20_resource.c. 951 */ 952static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, 953 bool fast_validate) 954{ 955 bool voltage_supported; 956 DC_FP_START(); 957 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); 958 DC_FP_END(); 959 return voltage_supported; 960} 961 962static void dcn21_destroy_resource_pool(struct resource_pool **pool) 963{ 964 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); 965 966 dcn21_resource_destruct(dcn21_pool); 967 kfree(dcn21_pool); 968 *pool = NULL; 969} 970 971static struct clock_source *dcn21_clock_source_create( 972 struct dc_context *ctx, 973 struct dc_bios *bios, 974 enum clock_source_id id, 975 const struct dce110_clk_src_regs *regs, 976 bool dp_clk_src) 977{ 978 struct dce110_clk_src *clk_src = 979 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 980 981 if (!clk_src) 982 return NULL; 983 984 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 985 regs, &cs_shift, &cs_mask)) { 986 clk_src->base.dp_clk_src = dp_clk_src; 987 return &clk_src->base; 988 } 989 990 kfree(clk_src); 991 BREAK_TO_DEBUGGER(); 992 return NULL; 993} 994 995static struct hubp *dcn21_hubp_create( 996 struct dc_context *ctx, 997 uint32_t inst) 998{ 999 struct dcn21_hubp *hubp21 = 1000 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL); 1001 1002 if (!hubp21) 1003 return NULL; 1004 1005 if (hubp21_construct(hubp21, ctx, inst, 1006 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1007 return &hubp21->base; 1008 1009 BREAK_TO_DEBUGGER(); 1010 kfree(hubp21); 1011 return NULL; 1012} 1013 1014static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) 1015{ 1016 int i; 1017 1018 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 1019 GFP_KERNEL); 1020 1021 if (!hubbub) 1022 return NULL; 1023 1024 hubbub21_construct(hubbub, ctx, 1025 &hubbub_reg, 1026 &hubbub_shift, 1027 &hubbub_mask); 1028 1029 for (i = 0; i < res_cap_rn.num_vmid; i++) { 1030 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 1031 1032 vmid->ctx = ctx; 1033 1034 vmid->regs = &vmid_regs[i]; 1035 vmid->shifts = &vmid_shifts; 1036 vmid->masks = &vmid_masks; 1037 } 1038 hubbub->num_vmid = res_cap_rn.num_vmid; 1039 1040 return &hubbub->base; 1041} 1042 1043static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx, 1044 uint32_t inst) 1045{ 1046 struct dcn20_opp *opp = 1047 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1048 1049 if (!opp) { 1050 BREAK_TO_DEBUGGER(); 1051 return NULL; 1052 } 1053 1054 dcn20_opp_construct(opp, ctx, inst, 1055 &opp_regs[inst], &opp_shift, &opp_mask); 1056 return &opp->base; 1057} 1058 1059static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx, 1060 uint32_t instance) 1061{ 1062 struct optc *tgn10 = 1063 kzalloc(sizeof(struct optc), GFP_KERNEL); 1064 1065 if (!tgn10) 1066 return NULL; 1067 1068 tgn10->base.inst = instance; 1069 tgn10->base.ctx = ctx; 1070 1071 tgn10->tg_regs = &tg_regs[instance]; 1072 tgn10->tg_shift = &tg_shift; 1073 tgn10->tg_mask = &tg_mask; 1074 1075 dcn20_timing_generator_init(tgn10); 1076 1077 return &tgn10->base; 1078} 1079 1080static struct mpc *dcn21_mpc_create(struct dc_context *ctx) 1081{ 1082 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 1083 GFP_KERNEL); 1084 1085 if (!mpc20) 1086 return NULL; 1087 1088 dcn20_mpc_construct(mpc20, ctx, 1089 &mpc_regs, 1090 &mpc_shift, 1091 &mpc_mask, 1092 6); 1093 1094 return &mpc20->base; 1095} 1096 1097static void read_dce_straps( 1098 struct dc_context *ctx, 1099 struct resource_straps *straps) 1100{ 1101 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1102 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1103 1104} 1105 1106 1107static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, 1108 uint32_t inst) 1109{ 1110 struct dcn20_dsc *dsc = 1111 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1112 1113 if (!dsc) { 1114 BREAK_TO_DEBUGGER(); 1115 return NULL; 1116 } 1117 1118 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1119 return &dsc->base; 1120} 1121 1122static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) 1123{ 1124 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 1125 1126 if (!pp_smu) 1127 return pp_smu; 1128 1129 dm_pp_get_funcs(ctx, pp_smu); 1130 1131 if (pp_smu->ctx.ver != PP_SMU_VER_RN) 1132 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 1133 1134 1135 return pp_smu; 1136} 1137 1138static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 1139{ 1140 if (pp_smu && *pp_smu) { 1141 kfree(*pp_smu); 1142 *pp_smu = NULL; 1143 } 1144} 1145 1146static struct audio *dcn21_create_audio( 1147 struct dc_context *ctx, unsigned int inst) 1148{ 1149 return dce_audio_create(ctx, inst, 1150 &audio_regs[inst], &audio_shift, &audio_mask); 1151} 1152 1153static struct dc_cap_funcs cap_funcs = { 1154 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1155}; 1156 1157static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id, 1158 struct dc_context *ctx) 1159{ 1160 struct dcn10_stream_encoder *enc1 = 1161 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1162 1163 if (!enc1) 1164 return NULL; 1165 1166 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1167 &stream_enc_regs[eng_id], 1168 &se_shift, &se_mask); 1169 1170 return &enc1->base; 1171} 1172 1173static const struct dce_hwseq_registers hwseq_reg = { 1174 HWSEQ_DCN21_REG_LIST() 1175}; 1176 1177static const struct dce_hwseq_shift hwseq_shift = { 1178 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) 1179}; 1180 1181static const struct dce_hwseq_mask hwseq_mask = { 1182 HWSEQ_DCN21_MASK_SH_LIST(_MASK) 1183}; 1184 1185static struct dce_hwseq *dcn21_hwseq_create( 1186 struct dc_context *ctx) 1187{ 1188 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1189 1190 if (hws) { 1191 hws->ctx = ctx; 1192 hws->regs = &hwseq_reg; 1193 hws->shifts = &hwseq_shift; 1194 hws->masks = &hwseq_mask; 1195 hws->wa.DEGVIDCN21 = true; 1196 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; 1197 } 1198 return hws; 1199} 1200 1201static const struct resource_create_funcs res_create_funcs = { 1202 .read_dce_straps = read_dce_straps, 1203 .create_audio = dcn21_create_audio, 1204 .create_stream_encoder = dcn21_stream_encoder_create, 1205 .create_hwseq = dcn21_hwseq_create, 1206}; 1207 1208static const struct encoder_feature_support link_enc_feature = { 1209 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1210 .max_hdmi_pixel_clock = 600000, 1211 .hdmi_ycbcr420_supported = true, 1212 .dp_ycbcr420_supported = true, 1213 .fec_supported = true, 1214 .flags.bits.IS_HBR2_CAPABLE = true, 1215 .flags.bits.IS_HBR3_CAPABLE = true, 1216 .flags.bits.IS_TPS3_CAPABLE = true, 1217 .flags.bits.IS_TPS4_CAPABLE = true 1218}; 1219 1220 1221#define link_regs(id, phyid)\ 1222[id] = {\ 1223 LE_DCN2_REG_LIST(id), \ 1224 UNIPHY_DCN2_REG_LIST(phyid), \ 1225 DPCS_DCN21_REG_LIST(id), \ 1226 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 1227} 1228 1229static const struct dcn10_link_enc_registers link_enc_regs[] = { 1230 link_regs(0, A), 1231 link_regs(1, B), 1232 link_regs(2, C), 1233 link_regs(3, D), 1234 link_regs(4, E), 1235}; 1236 1237static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 1238 { DCN_PANEL_CNTL_REG_LIST() } 1239}; 1240 1241static const struct dce_panel_cntl_shift panel_cntl_shift = { 1242 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 1243}; 1244 1245static const struct dce_panel_cntl_mask panel_cntl_mask = { 1246 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 1247}; 1248 1249#define aux_regs(id)\ 1250[id] = {\ 1251 DCN2_AUX_REG_LIST(id)\ 1252} 1253 1254static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 1255 aux_regs(0), 1256 aux_regs(1), 1257 aux_regs(2), 1258 aux_regs(3), 1259 aux_regs(4) 1260}; 1261 1262#define hpd_regs(id)\ 1263[id] = {\ 1264 HPD_REG_LIST(id)\ 1265} 1266 1267static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 1268 hpd_regs(0), 1269 hpd_regs(1), 1270 hpd_regs(2), 1271 hpd_regs(3), 1272 hpd_regs(4) 1273}; 1274 1275static const struct dcn10_link_enc_shift le_shift = { 1276 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 1277 DPCS_DCN21_MASK_SH_LIST(__SHIFT) 1278}; 1279 1280static const struct dcn10_link_enc_mask le_mask = { 1281 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 1282 DPCS_DCN21_MASK_SH_LIST(_MASK) 1283}; 1284 1285static int map_transmitter_id_to_phy_instance( 1286 enum transmitter transmitter) 1287{ 1288 switch (transmitter) { 1289 case TRANSMITTER_UNIPHY_A: 1290 return 0; 1291 break; 1292 case TRANSMITTER_UNIPHY_B: 1293 return 1; 1294 break; 1295 case TRANSMITTER_UNIPHY_C: 1296 return 2; 1297 break; 1298 case TRANSMITTER_UNIPHY_D: 1299 return 3; 1300 break; 1301 case TRANSMITTER_UNIPHY_E: 1302 return 4; 1303 break; 1304 default: 1305 ASSERT(0); 1306 return 0; 1307 } 1308} 1309 1310static struct link_encoder *dcn21_link_encoder_create( 1311 struct dc_context *ctx, 1312 const struct encoder_init_data *enc_init_data) 1313{ 1314 struct dcn21_link_encoder *enc21 = 1315 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); 1316 int link_regs_id; 1317 1318 if (!enc21) 1319 return NULL; 1320 1321 link_regs_id = 1322 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 1323 1324 dcn21_link_encoder_construct(enc21, 1325 enc_init_data, 1326 &link_enc_feature, 1327 &link_enc_regs[link_regs_id], 1328 &link_enc_aux_regs[enc_init_data->channel - 1], 1329 &link_enc_hpd_regs[enc_init_data->hpd_source], 1330 &le_shift, 1331 &le_mask); 1332 1333 return &enc21->enc10.base; 1334} 1335 1336static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1337{ 1338 struct dce_panel_cntl *panel_cntl = 1339 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1340 1341 if (!panel_cntl) 1342 return NULL; 1343 1344 dce_panel_cntl_construct(panel_cntl, 1345 init_data, 1346 &panel_cntl_regs[init_data->inst], 1347 &panel_cntl_shift, 1348 &panel_cntl_mask); 1349 1350 return &panel_cntl->base; 1351} 1352 1353static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config) 1354{ 1355 *panel_config = panel_config_defaults; 1356} 1357 1358#define CTX ctx 1359 1360#define REG(reg_name) \ 1361 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1362 1363static uint32_t read_pipe_fuses(struct dc_context *ctx) 1364{ 1365 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1366 /* RV1 support max 4 pipes */ 1367 value = value & 0xf; 1368 return value; 1369} 1370 1371static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1372{ 1373 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) { 1374 plane_state->dcc.enable = 1; 1375 /* align to our worst case block width */ 1376 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024; 1377 } 1378 1379 return dcn20_patch_unknown_plane_state(plane_state); 1380} 1381 1382static const struct resource_funcs dcn21_res_pool_funcs = { 1383 .destroy = dcn21_destroy_resource_pool, 1384 .link_enc_create = dcn21_link_encoder_create, 1385 .panel_cntl_create = dcn21_panel_cntl_create, 1386 .validate_bandwidth = dcn21_validate_bandwidth, 1387 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, 1388 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 1389 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1390 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1391 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1392 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 1393 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state, 1394 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 1395 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1396 .update_bw_bounding_box = dcn21_update_bw_bounding_box, 1397 .get_panel_config_defaults = dcn21_get_panel_config_defaults, 1398}; 1399 1400static bool dcn21_resource_construct( 1401 uint8_t num_virtual_links, 1402 struct dc *dc, 1403 struct dcn21_resource_pool *pool) 1404{ 1405 int i, j; 1406 struct dc_context *ctx = dc->ctx; 1407 struct irq_service_init_data init_data; 1408 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1409 uint32_t num_pipes; 1410 1411 ctx->dc_bios->regs = &bios_regs; 1412 1413 pool->base.res_cap = &res_cap_rn; 1414#ifdef DIAGS_BUILD 1415 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 1416 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc; 1417 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; 1418#endif 1419 1420 pool->base.funcs = &dcn21_res_pool_funcs; 1421 1422 /************************************************* 1423 * Resource + asic cap harcoding * 1424 *************************************************/ 1425 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1426 1427 /* max pipe num for ASIC before check pipe fuses */ 1428 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1429 1430 dc->caps.max_downscale_ratio = 200; 1431 dc->caps.i2c_speed_in_khz = 100; 1432 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1433 dc->caps.max_cursor_size = 256; 1434 dc->caps.min_horizontal_blanking_period = 80; 1435 dc->caps.dmdata_alloc_size = 2048; 1436 1437 dc->caps.max_slave_planes = 1; 1438 dc->caps.max_slave_yuv_planes = 1; 1439 dc->caps.max_slave_rgb_planes = 1; 1440 dc->caps.post_blend_color_processing = true; 1441 dc->caps.force_dp_tps4_for_cp2520 = true; 1442 dc->caps.extended_aux_timeout_support = true; 1443 dc->caps.dmcub_support = true; 1444 dc->caps.is_apu = true; 1445 1446 /* Color pipeline capabilities */ 1447 dc->caps.color.dpp.dcn_arch = 1; 1448 dc->caps.color.dpp.input_lut_shared = 0; 1449 dc->caps.color.dpp.icsc = 1; 1450 dc->caps.color.dpp.dgam_ram = 1; 1451 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1452 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1453 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1454 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1455 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1456 dc->caps.color.dpp.post_csc = 0; 1457 dc->caps.color.dpp.gamma_corr = 0; 1458 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 1459 1460 dc->caps.color.dpp.hw_3d_lut = 1; 1461 dc->caps.color.dpp.ogam_ram = 1; 1462 // no OGAM ROM on DCN2 1463 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1464 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1465 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1466 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1467 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1468 dc->caps.color.dpp.ocsc = 0; 1469 1470 dc->caps.color.mpc.gamut_remap = 0; 1471 dc->caps.color.mpc.num_3dluts = 0; 1472 dc->caps.color.mpc.shared_3d_lut = 0; 1473 dc->caps.color.mpc.ogam_ram = 1; 1474 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1475 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1476 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1477 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1478 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1479 dc->caps.color.mpc.ocsc = 1; 1480 1481 dc->caps.dp_hdmi21_pcon_support = true; 1482 1483 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1484 dc->debug = debug_defaults_drv; 1485 1486 // Init the vm_helper 1487 if (dc->vm_helper) 1488 vm_helper_init(dc->vm_helper, 16); 1489 1490 /************************************************* 1491 * Create resources * 1492 *************************************************/ 1493 1494 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 1495 dcn21_clock_source_create(ctx, ctx->dc_bios, 1496 CLOCK_SOURCE_COMBO_PHY_PLL0, 1497 &clk_src_regs[0], false); 1498 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 1499 dcn21_clock_source_create(ctx, ctx->dc_bios, 1500 CLOCK_SOURCE_COMBO_PHY_PLL1, 1501 &clk_src_regs[1], false); 1502 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 1503 dcn21_clock_source_create(ctx, ctx->dc_bios, 1504 CLOCK_SOURCE_COMBO_PHY_PLL2, 1505 &clk_src_regs[2], false); 1506 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 1507 dcn21_clock_source_create(ctx, ctx->dc_bios, 1508 CLOCK_SOURCE_COMBO_PHY_PLL3, 1509 &clk_src_regs[3], false); 1510 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 1511 dcn21_clock_source_create(ctx, ctx->dc_bios, 1512 CLOCK_SOURCE_COMBO_PHY_PLL4, 1513 &clk_src_regs[4], false); 1514 1515 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 1516 1517 /* todo: not reuse phy_pll registers */ 1518 pool->base.dp_clock_source = 1519 dcn21_clock_source_create(ctx, ctx->dc_bios, 1520 CLOCK_SOURCE_ID_DP_DTO, 1521 &clk_src_regs[0], true); 1522 1523 for (i = 0; i < pool->base.clk_src_count; i++) { 1524 if (pool->base.clock_sources[i] == NULL) { 1525 dm_error("DC: failed to create clock sources!\n"); 1526 BREAK_TO_DEBUGGER(); 1527 goto create_fail; 1528 } 1529 } 1530 1531 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1532 if (pool->base.dccg == NULL) { 1533 dm_error("DC: failed to create dccg!\n"); 1534 BREAK_TO_DEBUGGER(); 1535 goto create_fail; 1536 } 1537 1538 if (!dc->config.disable_dmcu) { 1539 pool->base.dmcu = dcn21_dmcu_create(ctx, 1540 &dmcu_regs, 1541 &dmcu_shift, 1542 &dmcu_mask); 1543 if (pool->base.dmcu == NULL) { 1544 dm_error("DC: failed to create dmcu!\n"); 1545 BREAK_TO_DEBUGGER(); 1546 goto create_fail; 1547 } 1548 1549 dc->debug.dmub_command_table = false; 1550 } 1551 1552 if (dc->config.disable_dmcu) { 1553 pool->base.psr = dmub_psr_create(ctx); 1554 1555 if (pool->base.psr == NULL) { 1556 dm_error("DC: failed to create psr obj!\n"); 1557 BREAK_TO_DEBUGGER(); 1558 goto create_fail; 1559 } 1560 } 1561 1562 if (dc->config.disable_dmcu) 1563 pool->base.abm = dmub_abm_create(ctx, 1564 &abm_regs, 1565 &abm_shift, 1566 &abm_mask); 1567 else 1568 pool->base.abm = dce_abm_create(ctx, 1569 &abm_regs, 1570 &abm_shift, 1571 &abm_mask); 1572 1573 pool->base.pp_smu = dcn21_pp_smu_create(ctx); 1574 1575 num_pipes = dcn2_1_ip.max_num_dpp; 1576 1577 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++) 1578 if (pipe_fuses & 1 << i) 1579 num_pipes--; 1580 dcn2_1_ip.max_num_dpp = num_pipes; 1581 dcn2_1_ip.max_num_otg = num_pipes; 1582 1583 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); 1584 1585 init_data.ctx = dc->ctx; 1586 pool->base.irqs = dal_irq_service_dcn21_create(&init_data); 1587 if (!pool->base.irqs) 1588 goto create_fail; 1589 1590 j = 0; 1591 /* mem input -> ipp -> dpp -> opp -> TG */ 1592 for (i = 0; i < pool->base.pipe_count; i++) { 1593 /* if pipe is disabled, skip instance of HW pipe, 1594 * i.e, skip ASIC register instance 1595 */ 1596 if ((pipe_fuses & (1 << i)) != 0) 1597 continue; 1598 1599 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); 1600 if (pool->base.hubps[j] == NULL) { 1601 BREAK_TO_DEBUGGER(); 1602 dm_error( 1603 "DC: failed to create memory input!\n"); 1604 goto create_fail; 1605 } 1606 1607 pool->base.ipps[j] = dcn21_ipp_create(ctx, i); 1608 if (pool->base.ipps[j] == NULL) { 1609 BREAK_TO_DEBUGGER(); 1610 dm_error( 1611 "DC: failed to create input pixel processor!\n"); 1612 goto create_fail; 1613 } 1614 1615 pool->base.dpps[j] = dcn21_dpp_create(ctx, i); 1616 if (pool->base.dpps[j] == NULL) { 1617 BREAK_TO_DEBUGGER(); 1618 dm_error( 1619 "DC: failed to create dpps!\n"); 1620 goto create_fail; 1621 } 1622 1623 pool->base.opps[j] = dcn21_opp_create(ctx, i); 1624 if (pool->base.opps[j] == NULL) { 1625 BREAK_TO_DEBUGGER(); 1626 dm_error( 1627 "DC: failed to create output pixel processor!\n"); 1628 goto create_fail; 1629 } 1630 1631 pool->base.timing_generators[j] = dcn21_timing_generator_create( 1632 ctx, i); 1633 if (pool->base.timing_generators[j] == NULL) { 1634 BREAK_TO_DEBUGGER(); 1635 dm_error("DC: failed to create tg!\n"); 1636 goto create_fail; 1637 } 1638 j++; 1639 } 1640 1641 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1642 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); 1643 if (pool->base.engines[i] == NULL) { 1644 BREAK_TO_DEBUGGER(); 1645 dm_error( 1646 "DC:failed to create aux engine!!\n"); 1647 goto create_fail; 1648 } 1649 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); 1650 if (pool->base.hw_i2cs[i] == NULL) { 1651 BREAK_TO_DEBUGGER(); 1652 dm_error( 1653 "DC:failed to create hw i2c!!\n"); 1654 goto create_fail; 1655 } 1656 pool->base.sw_i2cs[i] = NULL; 1657 } 1658 1659 pool->base.timing_generator_count = j; 1660 pool->base.pipe_count = j; 1661 pool->base.mpcc_count = j; 1662 1663 pool->base.mpc = dcn21_mpc_create(ctx); 1664 if (pool->base.mpc == NULL) { 1665 BREAK_TO_DEBUGGER(); 1666 dm_error("DC: failed to create mpc!\n"); 1667 goto create_fail; 1668 } 1669 1670 pool->base.hubbub = dcn21_hubbub_create(ctx); 1671 if (pool->base.hubbub == NULL) { 1672 BREAK_TO_DEBUGGER(); 1673 dm_error("DC: failed to create hubbub!\n"); 1674 goto create_fail; 1675 } 1676 1677 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1678 pool->base.dscs[i] = dcn21_dsc_create(ctx, i); 1679 if (pool->base.dscs[i] == NULL) { 1680 BREAK_TO_DEBUGGER(); 1681 dm_error("DC: failed to create display stream compressor %d!\n", i); 1682 goto create_fail; 1683 } 1684 } 1685 1686 if (!dcn20_dwbc_create(ctx, &pool->base)) { 1687 BREAK_TO_DEBUGGER(); 1688 dm_error("DC: failed to create dwbc!\n"); 1689 goto create_fail; 1690 } 1691 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 1692 BREAK_TO_DEBUGGER(); 1693 dm_error("DC: failed to create mcif_wb!\n"); 1694 goto create_fail; 1695 } 1696 1697 if (!resource_construct(num_virtual_links, dc, &pool->base, 1698 &res_create_funcs)) 1699 goto create_fail; 1700 1701 dcn21_hw_sequencer_construct(dc); 1702 1703 dc->caps.max_planes = pool->base.pipe_count; 1704 1705 for (i = 0; i < dc->caps.max_planes; ++i) 1706 dc->caps.planes[i] = plane_cap; 1707 1708 dc->cap_funcs = cap_funcs; 1709 1710 return true; 1711 1712create_fail: 1713 1714 dcn21_resource_destruct(pool); 1715 1716 return false; 1717} 1718 1719struct resource_pool *dcn21_create_resource_pool( 1720 const struct dc_init_data *init_data, 1721 struct dc *dc) 1722{ 1723 struct dcn21_resource_pool *pool = 1724 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL); 1725 1726 if (!pool) 1727 return NULL; 1728 1729 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) 1730 return &pool->base; 1731 1732 BREAK_TO_DEBUGGER(); 1733 kfree(pool); 1734 return NULL; 1735} 1736