/openbsd-current/sys/dev/pci/drm/i915/display/ |
H A D | intel_dp.h | 34 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 79 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 116 u32 pipe_bpp, 130 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
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H A D | g4x_hdmi.c | 45 if (crtc_state->pipe_bpp > 24) 280 if (pipe_config->pipe_bpp > 24 && 329 if (pipe_config->pipe_bpp > 24) { 340 if (pipe_config->pipe_bpp > 24) {
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H A D | intel_dp.c | 702 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) argument 716 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 751 u32 pipe_bpp, 802 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); 1176 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); local 1196 pipe_bpp, 64) >> 4; 1387 bpc = crtc_state->pipe_bpp / 3; 1434 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); 1512 pipe_config->pipe_bpp = bpp; 1674 int pipe_bpp; local 747 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, u32 pipe_bpp, u32 timeslots) argument 3060 intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) argument [all...] |
H A D | intel_fdi.c | 257 pipe_config->pipe_bpp); 261 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, 268 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { 269 pipe_config->pipe_bpp -= 2*3; 272 pipe_config->pipe_bpp);
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H A D | intel_dp_mst.c | 140 crtc_state->pipe_bpp = bpp; 165 intel_link_compute_m_n(crtc_state->pipe_bpp, 241 crtc_state->pipe_bpp); 341 * their current pipe_bpp we should reduce pipe_bpp across 347 limits.max_bpp = min(pipe_config->pipe_bpp, 24); 973 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); local 983 pipe_bpp, 64) >> 4;
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H A D | intel_lvds.c | 297 if (crtc_state->dither && crtc_state->pipe_bpp == 18) 438 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { 441 crtc_state->pipe_bpp, lvds_bpp); 442 crtc_state->pipe_bpp = lvds_bpp;
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H A D | hsw_ips.c | 198 if (crtc_state->pipe_bpp > 24)
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H A D | intel_display.c | 2707 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2711 switch (crtc_state->pipe_bpp) { 2714 MISSING_CASE(crtc_state->pipe_bpp); 2919 pipe_config->pipe_bpp = 18; 2922 pipe_config->pipe_bpp = 24; 2925 pipe_config->pipe_bpp = 30; 3033 switch (crtc_state->pipe_bpp) { 3036 MISSING_CASE(crtc_state->pipe_bpp); 3119 switch (crtc_state->pipe_bpp) { 3135 MISSING_CASE(crtc_state->pipe_bpp); [all...] |
H A D | intel_hdmi.c | 927 static bool gcp_default_phase_possible(int pipe_bpp, argument 932 switch (pipe_bpp) { 1022 if (crtc_state->pipe_bpp > 24) 1026 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 2085 * pipe_bpp could already be below 8bpc due to FDI 2088 bpc = max(crtc_state->pipe_bpp / 3, 8); 2133 * pipe_bpp could already be below 8bpc due to 2137 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2141 bpc, crtc_state->pipe_bpp); [all...] |
H A D | intel_crtc_state_dump.c | 229 pipe_config->pipe_bpp, pipe_config->dither);
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H A D | icl_dsi.c | 1535 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1580 if (crtc_state->pipe_bpp < 8 * 3) 1646 pipe_config->pipe_bpp = 24; 1648 pipe_config->pipe_bpp = 18;
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H A D | intel_crt.c | 447 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 453 pipe_config->pipe_bpp = 24;
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H A D | intel_ddi.c | 398 switch (crtc_state->pipe_bpp) { 412 MISSING_CASE(crtc_state->pipe_bpp); 489 switch (crtc_state->pipe_bpp) { 491 MISSING_CASE(crtc_state->pipe_bpp); 3676 pipe_config->pipe_bpp = 18; 3679 pipe_config->pipe_bpp = 24; 3682 pipe_config->pipe_bpp = 30; 3685 pipe_config->pipe_bpp = 36; 3791 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
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H A D | vlv_dsi.c | 300 pipe_config->pipe_bpp = 24; 302 pipe_config->pipe_bpp = 18; 1040 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
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H A D | intel_panel.c | 665 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
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H A D | intel_audio.c | 222 if (crtc_state->pipe_bpp == 36) { 225 } else if (crtc_state->pipe_bpp == 30) {
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H A D | intel_display_debugfs.c | 587 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); 1450 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3);
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H A D | intel_vdsc.c | 286 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
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H A D | intel_modeset_setup.c | 322 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
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H A D | intel_display_types.h | 1194 int pipe_bpp; member in struct:intel_crtc_state
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H A D | intel_psr.c | 1140 if (crtc_state->pipe_bpp > max_bpp) { 1143 crtc_state->pipe_bpp, max_bpp);
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H A D | g4x_dp.c | 403 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
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H A D | intel_tv.c | 1219 pipe_config->pipe_bpp = 8*3;
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H A D | intel_bios.c | 3425 crtc_state->pipe_bpp = bpc * 3; 3427 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
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H A D | intel_sdvo.c | 1356 pipe_config->pipe_bpp = 8*3;
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