1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8#include "g4x_hdmi.h" 9#include "i915_reg.h" 10#include "intel_atomic.h" 11#include "intel_audio.h" 12#include "intel_connector.h" 13#include "intel_crtc.h" 14#include "intel_de.h" 15#include "intel_display_power.h" 16#include "intel_display_types.h" 17#include "intel_dp_aux.h" 18#include "intel_dpio_phy.h" 19#include "intel_fifo_underrun.h" 20#include "intel_hdmi.h" 21#include "intel_hotplug.h" 22#include "intel_sdvo.h" 23#include "vlv_sideband.h" 24 25static void intel_hdmi_prepare(struct intel_encoder *encoder, 26 const struct intel_crtc_state *crtc_state) 27{ 28 struct drm_device *dev = encoder->base.dev; 29 struct drm_i915_private *dev_priv = to_i915(dev); 30 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 31 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 32 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 33 u32 hdmi_val; 34 35 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 36 37 hdmi_val = SDVO_ENCODING_HDMI; 38 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 39 hdmi_val |= HDMI_COLOR_RANGE_16_235; 40 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 41 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 42 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 43 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 44 45 if (crtc_state->pipe_bpp > 24) 46 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 47 else 48 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 49 50 if (crtc_state->has_hdmi_sink) 51 hdmi_val |= HDMI_MODE_SELECT_HDMI; 52 53 if (HAS_PCH_CPT(dev_priv)) 54 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 55 else if (IS_CHERRYVIEW(dev_priv)) 56 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 57 else 58 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 59 60 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 61 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 62} 63 64static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 65 enum pipe *pipe) 66{ 67 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 68 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 69 intel_wakeref_t wakeref; 70 bool ret; 71 72 wakeref = intel_display_power_get_if_enabled(dev_priv, 73 encoder->power_domain); 74 if (!wakeref) 75 return false; 76 77 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 78 79 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 80 81 return ret; 82} 83 84static bool connector_is_hdmi(struct drm_connector *connector) 85{ 86 struct intel_encoder *encoder = 87 intel_attached_encoder(to_intel_connector(connector)); 88 89 return encoder && encoder->type == INTEL_OUTPUT_HDMI; 90} 91 92static bool g4x_compute_has_hdmi_sink(struct intel_atomic_state *state, 93 struct intel_crtc *this_crtc) 94{ 95 const struct drm_connector_state *conn_state; 96 struct drm_connector *connector; 97 int i; 98 99 /* 100 * On g4x only one HDMI port can transmit infoframes/audio at 101 * any given time. Select the first suitable port for this duty. 102 * 103 * See also g4x_hdmi_connector_atomic_check(). 104 */ 105 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 106 struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); 107 const struct intel_crtc_state *crtc_state; 108 struct intel_crtc *crtc; 109 110 if (!connector_is_hdmi(connector)) 111 continue; 112 113 crtc = to_intel_crtc(conn_state->crtc); 114 if (!crtc) 115 continue; 116 117 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 118 119 if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state)) 120 continue; 121 122 return crtc == this_crtc; 123 } 124 125 return false; 126} 127 128static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 129 struct intel_crtc_state *crtc_state, 130 struct drm_connector_state *conn_state) 131{ 132 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 133 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 134 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 135 136 if (HAS_PCH_SPLIT(i915)) 137 crtc_state->has_pch_encoder = true; 138 139 if (IS_G4X(i915)) 140 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc); 141 else 142 crtc_state->has_hdmi_sink = 143 intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state); 144 145 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 146} 147 148static void intel_hdmi_get_config(struct intel_encoder *encoder, 149 struct intel_crtc_state *pipe_config) 150{ 151 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 152 struct drm_device *dev = encoder->base.dev; 153 struct drm_i915_private *dev_priv = to_i915(dev); 154 u32 tmp, flags = 0; 155 int dotclock; 156 157 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 158 159 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 160 161 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 162 flags |= DRM_MODE_FLAG_PHSYNC; 163 else 164 flags |= DRM_MODE_FLAG_NHSYNC; 165 166 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 167 flags |= DRM_MODE_FLAG_PVSYNC; 168 else 169 flags |= DRM_MODE_FLAG_NVSYNC; 170 171 if (tmp & HDMI_MODE_SELECT_HDMI) 172 pipe_config->has_hdmi_sink = true; 173 174 pipe_config->infoframes.enable |= 175 intel_hdmi_infoframes_enabled(encoder, pipe_config); 176 177 if (pipe_config->infoframes.enable) 178 pipe_config->has_infoframe = true; 179 180 if (tmp & HDMI_AUDIO_ENABLE) 181 pipe_config->has_audio = true; 182 183 if (!HAS_PCH_SPLIT(dev_priv) && 184 tmp & HDMI_COLOR_RANGE_16_235) 185 pipe_config->limited_color_range = true; 186 187 pipe_config->hw.adjusted_mode.flags |= flags; 188 189 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 190 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 191 else 192 dotclock = pipe_config->port_clock; 193 194 if (pipe_config->pixel_multiplier) 195 dotclock /= pipe_config->pixel_multiplier; 196 197 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 198 199 pipe_config->lane_count = 4; 200 201 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 202 203 intel_read_infoframe(encoder, pipe_config, 204 HDMI_INFOFRAME_TYPE_AVI, 205 &pipe_config->infoframes.avi); 206 intel_read_infoframe(encoder, pipe_config, 207 HDMI_INFOFRAME_TYPE_SPD, 208 &pipe_config->infoframes.spd); 209 intel_read_infoframe(encoder, pipe_config, 210 HDMI_INFOFRAME_TYPE_VENDOR, 211 &pipe_config->infoframes.hdmi); 212 213 intel_audio_codec_get_config(encoder, pipe_config); 214} 215 216static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 217 const struct intel_crtc_state *pipe_config) 218{ 219 struct drm_device *dev = encoder->base.dev; 220 struct drm_i915_private *dev_priv = to_i915(dev); 221 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 222 u32 temp; 223 224 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 225 226 temp |= SDVO_ENABLE; 227 if (pipe_config->has_audio) 228 temp |= HDMI_AUDIO_ENABLE; 229 230 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 231 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 232} 233 234static void g4x_enable_hdmi(struct intel_atomic_state *state, 235 struct intel_encoder *encoder, 236 const struct intel_crtc_state *pipe_config, 237 const struct drm_connector_state *conn_state) 238{ 239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 240 241 g4x_hdmi_enable_port(encoder, pipe_config); 242 243 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 244 !pipe_config->has_hdmi_sink); 245 intel_audio_codec_enable(encoder, pipe_config, conn_state); 246} 247 248static void ibx_enable_hdmi(struct intel_atomic_state *state, 249 struct intel_encoder *encoder, 250 const struct intel_crtc_state *pipe_config, 251 const struct drm_connector_state *conn_state) 252{ 253 struct drm_device *dev = encoder->base.dev; 254 struct drm_i915_private *dev_priv = to_i915(dev); 255 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 256 u32 temp; 257 258 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 259 260 temp |= SDVO_ENABLE; 261 if (pipe_config->has_audio) 262 temp |= HDMI_AUDIO_ENABLE; 263 264 /* 265 * HW workaround, need to write this twice for issue 266 * that may result in first write getting masked. 267 */ 268 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 269 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 270 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 271 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 272 273 /* 274 * HW workaround, need to toggle enable bit off and on 275 * for 12bpc with pixel repeat. 276 * 277 * FIXME: BSpec says this should be done at the end of 278 * the modeset sequence, so not sure if this isn't too soon. 279 */ 280 if (pipe_config->pipe_bpp > 24 && 281 pipe_config->pixel_multiplier > 1) { 282 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 283 temp & ~SDVO_ENABLE); 284 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 285 286 /* 287 * HW workaround, need to write this twice for issue 288 * that may result in first write getting masked. 289 */ 290 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 291 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 292 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 293 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 294 } 295 296 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 297 !pipe_config->has_hdmi_sink); 298 intel_audio_codec_enable(encoder, pipe_config, conn_state); 299} 300 301static void cpt_enable_hdmi(struct intel_atomic_state *state, 302 struct intel_encoder *encoder, 303 const struct intel_crtc_state *pipe_config, 304 const struct drm_connector_state *conn_state) 305{ 306 struct drm_device *dev = encoder->base.dev; 307 struct drm_i915_private *dev_priv = to_i915(dev); 308 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 309 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 310 enum pipe pipe = crtc->pipe; 311 u32 temp; 312 313 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 314 315 temp |= SDVO_ENABLE; 316 if (pipe_config->has_audio) 317 temp |= HDMI_AUDIO_ENABLE; 318 319 /* 320 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 321 * 322 * The procedure for 12bpc is as follows: 323 * 1. disable HDMI clock gating 324 * 2. enable HDMI with 8bpc 325 * 3. enable HDMI with 12bpc 326 * 4. enable HDMI clock gating 327 */ 328 329 if (pipe_config->pipe_bpp > 24) { 330 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 331 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 332 333 temp &= ~SDVO_COLOR_FORMAT_MASK; 334 temp |= SDVO_COLOR_FORMAT_8bpc; 335 } 336 337 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 338 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 339 340 if (pipe_config->pipe_bpp > 24) { 341 temp &= ~SDVO_COLOR_FORMAT_MASK; 342 temp |= HDMI_COLOR_FORMAT_12bpc; 343 344 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 345 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 346 347 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 348 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); 349 } 350 351 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 352 !pipe_config->has_hdmi_sink); 353 intel_audio_codec_enable(encoder, pipe_config, conn_state); 354} 355 356static void vlv_enable_hdmi(struct intel_atomic_state *state, 357 struct intel_encoder *encoder, 358 const struct intel_crtc_state *pipe_config, 359 const struct drm_connector_state *conn_state) 360{ 361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 362 363 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 364 !pipe_config->has_hdmi_sink); 365 intel_audio_codec_enable(encoder, pipe_config, conn_state); 366} 367 368static void intel_disable_hdmi(struct intel_atomic_state *state, 369 struct intel_encoder *encoder, 370 const struct intel_crtc_state *old_crtc_state, 371 const struct drm_connector_state *old_conn_state) 372{ 373 struct drm_device *dev = encoder->base.dev; 374 struct drm_i915_private *dev_priv = to_i915(dev); 375 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 376 struct intel_digital_port *dig_port = 377 hdmi_to_dig_port(intel_hdmi); 378 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 379 u32 temp; 380 381 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 382 383 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 384 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 385 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 386 387 /* 388 * HW workaround for IBX, we need to move the port 389 * to transcoder A after disabling it to allow the 390 * matching DP port to be enabled on transcoder A. 391 */ 392 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 393 /* 394 * We get CPU/PCH FIFO underruns on the other pipe when 395 * doing the workaround. Sweep them under the rug. 396 */ 397 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 398 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 399 400 temp &= ~SDVO_PIPE_SEL_MASK; 401 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 402 /* 403 * HW workaround, need to write this twice for issue 404 * that may result in first write getting masked. 405 */ 406 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 407 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 408 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 409 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 410 411 temp &= ~SDVO_ENABLE; 412 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 413 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 414 415 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 416 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 417 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 418 } 419 420 dig_port->set_infoframes(encoder, 421 false, 422 old_crtc_state, old_conn_state); 423 424 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 425} 426 427static void g4x_disable_hdmi(struct intel_atomic_state *state, 428 struct intel_encoder *encoder, 429 const struct intel_crtc_state *old_crtc_state, 430 const struct drm_connector_state *old_conn_state) 431{ 432 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 433 434 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 435} 436 437static void pch_disable_hdmi(struct intel_atomic_state *state, 438 struct intel_encoder *encoder, 439 const struct intel_crtc_state *old_crtc_state, 440 const struct drm_connector_state *old_conn_state) 441{ 442 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 443} 444 445static void pch_post_disable_hdmi(struct intel_atomic_state *state, 446 struct intel_encoder *encoder, 447 const struct intel_crtc_state *old_crtc_state, 448 const struct drm_connector_state *old_conn_state) 449{ 450 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 451} 452 453static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 454 struct intel_encoder *encoder, 455 const struct intel_crtc_state *pipe_config, 456 const struct drm_connector_state *conn_state) 457{ 458 struct intel_digital_port *dig_port = 459 enc_to_dig_port(encoder); 460 461 intel_hdmi_prepare(encoder, pipe_config); 462 463 dig_port->set_infoframes(encoder, 464 pipe_config->has_infoframe, 465 pipe_config, conn_state); 466} 467 468static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 469 struct intel_encoder *encoder, 470 const struct intel_crtc_state *pipe_config, 471 const struct drm_connector_state *conn_state) 472{ 473 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 474 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 475 476 vlv_phy_pre_encoder_enable(encoder, pipe_config); 477 478 /* HDMI 1.0V-2dB */ 479 vlv_set_phy_signal_level(encoder, pipe_config, 480 0x2b245f5f, 0x00002000, 481 0x5578b83a, 0x2b247878); 482 483 dig_port->set_infoframes(encoder, 484 pipe_config->has_infoframe, 485 pipe_config, conn_state); 486 487 g4x_hdmi_enable_port(encoder, pipe_config); 488 489 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 490} 491 492static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 493 struct intel_encoder *encoder, 494 const struct intel_crtc_state *pipe_config, 495 const struct drm_connector_state *conn_state) 496{ 497 intel_hdmi_prepare(encoder, pipe_config); 498 499 vlv_phy_pre_pll_enable(encoder, pipe_config); 500} 501 502static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 503 struct intel_encoder *encoder, 504 const struct intel_crtc_state *pipe_config, 505 const struct drm_connector_state *conn_state) 506{ 507 intel_hdmi_prepare(encoder, pipe_config); 508 509 chv_phy_pre_pll_enable(encoder, pipe_config); 510} 511 512static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 513 struct intel_encoder *encoder, 514 const struct intel_crtc_state *old_crtc_state, 515 const struct drm_connector_state *old_conn_state) 516{ 517 chv_phy_post_pll_disable(encoder, old_crtc_state); 518} 519 520static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 521 struct intel_encoder *encoder, 522 const struct intel_crtc_state *old_crtc_state, 523 const struct drm_connector_state *old_conn_state) 524{ 525 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 526 vlv_phy_reset_lanes(encoder, old_crtc_state); 527} 528 529static void chv_hdmi_post_disable(struct intel_atomic_state *state, 530 struct intel_encoder *encoder, 531 const struct intel_crtc_state *old_crtc_state, 532 const struct drm_connector_state *old_conn_state) 533{ 534 struct drm_device *dev = encoder->base.dev; 535 struct drm_i915_private *dev_priv = to_i915(dev); 536 537 vlv_dpio_get(dev_priv); 538 539 /* Assert data lane reset */ 540 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 541 542 vlv_dpio_put(dev_priv); 543} 544 545static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 546 struct intel_encoder *encoder, 547 const struct intel_crtc_state *pipe_config, 548 const struct drm_connector_state *conn_state) 549{ 550 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 551 struct drm_device *dev = encoder->base.dev; 552 struct drm_i915_private *dev_priv = to_i915(dev); 553 554 chv_phy_pre_encoder_enable(encoder, pipe_config); 555 556 /* FIXME: Program the support xxx V-dB */ 557 /* Use 800mV-0dB */ 558 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 559 560 dig_port->set_infoframes(encoder, 561 pipe_config->has_infoframe, 562 pipe_config, conn_state); 563 564 g4x_hdmi_enable_port(encoder, pipe_config); 565 566 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 567 568 /* Second common lane will stay alive on its own now */ 569 chv_phy_release_cl2_override(encoder); 570} 571 572static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 573 .destroy = intel_encoder_destroy, 574}; 575 576static enum intel_hotplug_state 577intel_hdmi_hotplug(struct intel_encoder *encoder, 578 struct intel_connector *connector) 579{ 580 enum intel_hotplug_state state; 581 582 state = intel_encoder_hotplug(encoder, connector); 583 584 /* 585 * On many platforms the HDMI live state signal is known to be 586 * unreliable, so we can't use it to detect if a sink is connected or 587 * not. Instead we detect if it's connected based on whether we can 588 * read the EDID or not. That in turn has a problem during disconnect, 589 * since the HPD interrupt may be raised before the DDC lines get 590 * disconnected (due to how the required length of DDC vs. HPD 591 * connector pins are specified) and so we'll still be able to get a 592 * valid EDID. To solve this schedule another detection cycle if this 593 * time around we didn't detect any change in the sink's connection 594 * status. 595 */ 596 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 597 state = INTEL_HOTPLUG_RETRY; 598 599 return state; 600} 601 602int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, 603 struct drm_atomic_state *state) 604{ 605 struct drm_i915_private *i915 = to_i915(state->dev); 606 struct drm_connector_list_iter conn_iter; 607 struct drm_connector *conn; 608 int ret; 609 610 ret = intel_digital_connector_atomic_check(connector, state); 611 if (ret) 612 return ret; 613 614 if (!IS_G4X(i915)) 615 return 0; 616 617 if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector)) 618 return 0; 619 620 /* 621 * On g4x only one HDMI port can transmit infoframes/audio 622 * at any given time. Make sure all enabled HDMI ports are 623 * included in the state so that it's possible to select 624 * one of them for this duty. 625 * 626 * See also g4x_compute_has_hdmi_sink(). 627 */ 628 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 629 drm_for_each_connector_iter(conn, &conn_iter) { 630 struct drm_connector_state *conn_state; 631 struct drm_crtc_state *crtc_state; 632 struct drm_crtc *crtc; 633 634 if (!connector_is_hdmi(conn)) 635 continue; 636 637 drm_dbg_kms(&i915->drm, "Adding [CONNECTOR:%d:%s]\n", 638 conn->base.id, conn->name); 639 640 conn_state = drm_atomic_get_connector_state(state, conn); 641 if (IS_ERR(conn_state)) { 642 ret = PTR_ERR(conn_state); 643 break; 644 } 645 646 crtc = conn_state->crtc; 647 if (!crtc) 648 continue; 649 650 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 651 crtc_state->mode_changed = true; 652 653 ret = drm_atomic_add_affected_planes(state, crtc); 654 if (ret) 655 break; 656 } 657 drm_connector_list_iter_end(&conn_iter); 658 659 return ret; 660} 661 662static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port port) 663{ 664 if (IS_G4X(i915) || IS_VALLEYVIEW(i915)) 665 return port == PORT_B || port == PORT_C; 666 else 667 return port == PORT_B || port == PORT_C || port == PORT_D; 668} 669 670static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum port port) 671{ 672 return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port), 673 "Platform does not support HDMI %c\n", port_name(port)); 674} 675 676void g4x_hdmi_init(struct drm_i915_private *dev_priv, 677 i915_reg_t hdmi_reg, enum port port) 678{ 679 const struct intel_bios_encoder_data *devdata; 680 struct intel_digital_port *dig_port; 681 struct intel_encoder *intel_encoder; 682 struct intel_connector *intel_connector; 683 684 if (!assert_port_valid(dev_priv, port)) 685 return; 686 687 if (!assert_hdmi_port_valid(dev_priv, port)) 688 return; 689 690 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 691 692 /* FIXME bail? */ 693 if (!devdata) 694 drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n", 695 port_name(port)); 696 697 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 698 if (!dig_port) 699 return; 700 701 dig_port->aux_ch = AUX_CH_NONE; 702 703 intel_connector = intel_connector_alloc(); 704 if (!intel_connector) { 705 kfree(dig_port); 706 return; 707 } 708 709 intel_encoder = &dig_port->base; 710 711 intel_encoder->devdata = devdata; 712 713 rw_init(&dig_port->hdcp_mutex, "hhdcp"); 714 715 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 716 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 717 "HDMI %c", port_name(port)); 718 719 intel_encoder->hotplug = intel_hdmi_hotplug; 720 intel_encoder->compute_config = g4x_hdmi_compute_config; 721 if (HAS_PCH_SPLIT(dev_priv)) { 722 intel_encoder->disable = pch_disable_hdmi; 723 intel_encoder->post_disable = pch_post_disable_hdmi; 724 } else { 725 intel_encoder->disable = g4x_disable_hdmi; 726 } 727 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 728 intel_encoder->get_config = intel_hdmi_get_config; 729 if (IS_CHERRYVIEW(dev_priv)) { 730 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 731 intel_encoder->pre_enable = chv_hdmi_pre_enable; 732 intel_encoder->enable = vlv_enable_hdmi; 733 intel_encoder->post_disable = chv_hdmi_post_disable; 734 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 735 } else if (IS_VALLEYVIEW(dev_priv)) { 736 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 737 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 738 intel_encoder->enable = vlv_enable_hdmi; 739 intel_encoder->post_disable = vlv_hdmi_post_disable; 740 } else { 741 intel_encoder->pre_enable = intel_hdmi_pre_enable; 742 if (HAS_PCH_CPT(dev_priv)) 743 intel_encoder->enable = cpt_enable_hdmi; 744 else if (HAS_PCH_IBX(dev_priv)) 745 intel_encoder->enable = ibx_enable_hdmi; 746 else 747 intel_encoder->enable = g4x_enable_hdmi; 748 } 749 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 750 751 intel_encoder->type = INTEL_OUTPUT_HDMI; 752 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 753 intel_encoder->port = port; 754 if (IS_CHERRYVIEW(dev_priv)) { 755 if (port == PORT_D) 756 intel_encoder->pipe_mask = BIT(PIPE_C); 757 else 758 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 759 } else { 760 intel_encoder->pipe_mask = ~0; 761 } 762 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 763 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 764 /* 765 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 766 * to work on real hardware. And since g4x can send infoframes to 767 * only one port anyway, nothing is lost by allowing it. 768 */ 769 if (IS_G4X(dev_priv)) 770 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 771 772 dig_port->hdmi.hdmi_reg = hdmi_reg; 773 dig_port->dp.output_reg = INVALID_MMIO_REG; 774 dig_port->max_lanes = 4; 775 776 intel_infoframe_init(dig_port); 777 778 intel_hdmi_init_connector(dig_port, intel_connector); 779} 780