1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright �� 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29#include <linux/delay.h> 30#include <linux/hdmi.h> 31#include <linux/i2c.h> 32#include <linux/slab.h> 33#include <linux/string_helpers.h> 34 35#include <drm/display/drm_hdcp_helper.h> 36#include <drm/display/drm_hdmi_helper.h> 37#include <drm/display/drm_scdc_helper.h> 38#include <drm/drm_atomic_helper.h> 39#include <drm/drm_crtc.h> 40#include <drm/drm_edid.h> 41#include <drm/intel_lpe_audio.h> 42 43#include "g4x_hdmi.h" 44#include "i915_drv.h" 45#include "i915_reg.h" 46#include "intel_atomic.h" 47#include "intel_audio.h" 48#include "intel_connector.h" 49#include "intel_cx0_phy.h" 50#include "intel_ddi.h" 51#include "intel_de.h" 52#include "intel_display_types.h" 53#include "intel_dp.h" 54#include "intel_gmbus.h" 55#include "intel_hdcp.h" 56#include "intel_hdcp_regs.h" 57#include "intel_hdmi.h" 58#include "intel_lspcon.h" 59#include "intel_panel.h" 60#include "intel_snps_phy.h" 61 62inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi) 63{ 64 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); 65} 66 67static void 68assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 69{ 70 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi); 71 u32 enabled_bits; 72 73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 74 75 drm_WARN(&dev_priv->drm, 76 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 77 "HDMI port enabled, expecting disabled\n"); 78} 79 80static void 81assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 82 enum transcoder cpu_transcoder) 83{ 84 drm_WARN(&dev_priv->drm, 85 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 86 TRANS_DDI_FUNC_ENABLE, 87 "HDMI transcoder function enabled, expecting disabled\n"); 88} 89 90static u32 g4x_infoframe_index(unsigned int type) 91{ 92 switch (type) { 93 case HDMI_PACKET_TYPE_GAMUT_METADATA: 94 return VIDEO_DIP_SELECT_GAMUT; 95 case HDMI_INFOFRAME_TYPE_AVI: 96 return VIDEO_DIP_SELECT_AVI; 97 case HDMI_INFOFRAME_TYPE_SPD: 98 return VIDEO_DIP_SELECT_SPD; 99 case HDMI_INFOFRAME_TYPE_VENDOR: 100 return VIDEO_DIP_SELECT_VENDOR; 101 default: 102 MISSING_CASE(type); 103 return 0; 104 } 105} 106 107static u32 g4x_infoframe_enable(unsigned int type) 108{ 109 switch (type) { 110 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 111 return VIDEO_DIP_ENABLE_GCP; 112 case HDMI_PACKET_TYPE_GAMUT_METADATA: 113 return VIDEO_DIP_ENABLE_GAMUT; 114 case DP_SDP_VSC: 115 return 0; 116 case HDMI_INFOFRAME_TYPE_AVI: 117 return VIDEO_DIP_ENABLE_AVI; 118 case HDMI_INFOFRAME_TYPE_SPD: 119 return VIDEO_DIP_ENABLE_SPD; 120 case HDMI_INFOFRAME_TYPE_VENDOR: 121 return VIDEO_DIP_ENABLE_VENDOR; 122 case HDMI_INFOFRAME_TYPE_DRM: 123 return 0; 124 default: 125 MISSING_CASE(type); 126 return 0; 127 } 128} 129 130static u32 hsw_infoframe_enable(unsigned int type) 131{ 132 switch (type) { 133 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 134 return VIDEO_DIP_ENABLE_GCP_HSW; 135 case HDMI_PACKET_TYPE_GAMUT_METADATA: 136 return VIDEO_DIP_ENABLE_GMP_HSW; 137 case DP_SDP_VSC: 138 return VIDEO_DIP_ENABLE_VSC_HSW; 139 case DP_SDP_PPS: 140 return VDIP_ENABLE_PPS; 141 case HDMI_INFOFRAME_TYPE_AVI: 142 return VIDEO_DIP_ENABLE_AVI_HSW; 143 case HDMI_INFOFRAME_TYPE_SPD: 144 return VIDEO_DIP_ENABLE_SPD_HSW; 145 case HDMI_INFOFRAME_TYPE_VENDOR: 146 return VIDEO_DIP_ENABLE_VS_HSW; 147 case HDMI_INFOFRAME_TYPE_DRM: 148 return VIDEO_DIP_ENABLE_DRM_GLK; 149 default: 150 MISSING_CASE(type); 151 return 0; 152 } 153} 154 155static i915_reg_t 156hsw_dip_data_reg(struct drm_i915_private *dev_priv, 157 enum transcoder cpu_transcoder, 158 unsigned int type, 159 int i) 160{ 161 switch (type) { 162 case HDMI_PACKET_TYPE_GAMUT_METADATA: 163 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 164 case DP_SDP_VSC: 165 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 166 case DP_SDP_PPS: 167 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 168 case HDMI_INFOFRAME_TYPE_AVI: 169 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 170 case HDMI_INFOFRAME_TYPE_SPD: 171 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 172 case HDMI_INFOFRAME_TYPE_VENDOR: 173 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 174 case HDMI_INFOFRAME_TYPE_DRM: 175 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 176 default: 177 MISSING_CASE(type); 178 return INVALID_MMIO_REG; 179 } 180} 181 182static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 183 unsigned int type) 184{ 185 switch (type) { 186 case DP_SDP_VSC: 187 return VIDEO_DIP_VSC_DATA_SIZE; 188 case DP_SDP_PPS: 189 return VIDEO_DIP_PPS_DATA_SIZE; 190 case HDMI_PACKET_TYPE_GAMUT_METADATA: 191 if (DISPLAY_VER(dev_priv) >= 11) 192 return VIDEO_DIP_GMP_DATA_SIZE; 193 else 194 return VIDEO_DIP_DATA_SIZE; 195 default: 196 return VIDEO_DIP_DATA_SIZE; 197 } 198} 199 200static void g4x_write_infoframe(struct intel_encoder *encoder, 201 const struct intel_crtc_state *crtc_state, 202 unsigned int type, 203 const void *frame, ssize_t len) 204{ 205 const u32 *data = frame; 206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 207 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 208 int i; 209 210 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 211 "Writing DIP with CTL reg disabled\n"); 212 213 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 214 val |= g4x_infoframe_index(type); 215 216 val &= ~g4x_infoframe_enable(type); 217 218 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 219 220 for (i = 0; i < len; i += 4) { 221 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 222 data++; 223 } 224 /* Write every possible data byte to force correct ECC calculation. */ 225 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 226 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 227 228 val |= g4x_infoframe_enable(type); 229 val &= ~VIDEO_DIP_FREQ_MASK; 230 val |= VIDEO_DIP_FREQ_VSYNC; 231 232 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 233 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 234} 235 236static void g4x_read_infoframe(struct intel_encoder *encoder, 237 const struct intel_crtc_state *crtc_state, 238 unsigned int type, 239 void *frame, ssize_t len) 240{ 241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 242 u32 *data = frame; 243 int i; 244 245 intel_de_rmw(dev_priv, VIDEO_DIP_CTL, 246 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 247 248 for (i = 0; i < len; i += 4) 249 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 250} 251 252static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 253 const struct intel_crtc_state *pipe_config) 254{ 255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 256 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 257 258 if ((val & VIDEO_DIP_ENABLE) == 0) 259 return 0; 260 261 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 262 return 0; 263 264 return val & (VIDEO_DIP_ENABLE_AVI | 265 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 266} 267 268static void ibx_write_infoframe(struct intel_encoder *encoder, 269 const struct intel_crtc_state *crtc_state, 270 unsigned int type, 271 const void *frame, ssize_t len) 272{ 273 const u32 *data = frame; 274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 276 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 277 u32 val = intel_de_read(dev_priv, reg); 278 int i; 279 280 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 281 "Writing DIP with CTL reg disabled\n"); 282 283 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 284 val |= g4x_infoframe_index(type); 285 286 val &= ~g4x_infoframe_enable(type); 287 288 intel_de_write(dev_priv, reg, val); 289 290 for (i = 0; i < len; i += 4) { 291 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 292 *data); 293 data++; 294 } 295 /* Write every possible data byte to force correct ECC calculation. */ 296 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 297 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 298 299 val |= g4x_infoframe_enable(type); 300 val &= ~VIDEO_DIP_FREQ_MASK; 301 val |= VIDEO_DIP_FREQ_VSYNC; 302 303 intel_de_write(dev_priv, reg, val); 304 intel_de_posting_read(dev_priv, reg); 305} 306 307static void ibx_read_infoframe(struct intel_encoder *encoder, 308 const struct intel_crtc_state *crtc_state, 309 unsigned int type, 310 void *frame, ssize_t len) 311{ 312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 314 u32 *data = frame; 315 int i; 316 317 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), 318 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 319 320 for (i = 0; i < len; i += 4) 321 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 322} 323 324static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 325 const struct intel_crtc_state *pipe_config) 326{ 327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 328 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 329 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 330 u32 val = intel_de_read(dev_priv, reg); 331 332 if ((val & VIDEO_DIP_ENABLE) == 0) 333 return 0; 334 335 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 336 return 0; 337 338 return val & (VIDEO_DIP_ENABLE_AVI | 339 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 340 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 341} 342 343static void cpt_write_infoframe(struct intel_encoder *encoder, 344 const struct intel_crtc_state *crtc_state, 345 unsigned int type, 346 const void *frame, ssize_t len) 347{ 348 const u32 *data = frame; 349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 351 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 352 u32 val = intel_de_read(dev_priv, reg); 353 int i; 354 355 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 356 "Writing DIP with CTL reg disabled\n"); 357 358 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 359 val |= g4x_infoframe_index(type); 360 361 /* The DIP control register spec says that we need to update the AVI 362 * infoframe without clearing its enable bit */ 363 if (type != HDMI_INFOFRAME_TYPE_AVI) 364 val &= ~g4x_infoframe_enable(type); 365 366 intel_de_write(dev_priv, reg, val); 367 368 for (i = 0; i < len; i += 4) { 369 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 370 *data); 371 data++; 372 } 373 /* Write every possible data byte to force correct ECC calculation. */ 374 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 376 377 val |= g4x_infoframe_enable(type); 378 val &= ~VIDEO_DIP_FREQ_MASK; 379 val |= VIDEO_DIP_FREQ_VSYNC; 380 381 intel_de_write(dev_priv, reg, val); 382 intel_de_posting_read(dev_priv, reg); 383} 384 385static void cpt_read_infoframe(struct intel_encoder *encoder, 386 const struct intel_crtc_state *crtc_state, 387 unsigned int type, 388 void *frame, ssize_t len) 389{ 390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 392 u32 *data = frame; 393 int i; 394 395 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), 396 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 397 398 for (i = 0; i < len; i += 4) 399 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 400} 401 402static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 403 const struct intel_crtc_state *pipe_config) 404{ 405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 406 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 407 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 408 409 if ((val & VIDEO_DIP_ENABLE) == 0) 410 return 0; 411 412 return val & (VIDEO_DIP_ENABLE_AVI | 413 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 414 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 415} 416 417static void vlv_write_infoframe(struct intel_encoder *encoder, 418 const struct intel_crtc_state *crtc_state, 419 unsigned int type, 420 const void *frame, ssize_t len) 421{ 422 const u32 *data = frame; 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 425 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 426 u32 val = intel_de_read(dev_priv, reg); 427 int i; 428 429 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 430 "Writing DIP with CTL reg disabled\n"); 431 432 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 433 val |= g4x_infoframe_index(type); 434 435 val &= ~g4x_infoframe_enable(type); 436 437 intel_de_write(dev_priv, reg, val); 438 439 for (i = 0; i < len; i += 4) { 440 intel_de_write(dev_priv, 441 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 442 data++; 443 } 444 /* Write every possible data byte to force correct ECC calculation. */ 445 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 446 intel_de_write(dev_priv, 447 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 448 449 val |= g4x_infoframe_enable(type); 450 val &= ~VIDEO_DIP_FREQ_MASK; 451 val |= VIDEO_DIP_FREQ_VSYNC; 452 453 intel_de_write(dev_priv, reg, val); 454 intel_de_posting_read(dev_priv, reg); 455} 456 457static void vlv_read_infoframe(struct intel_encoder *encoder, 458 const struct intel_crtc_state *crtc_state, 459 unsigned int type, 460 void *frame, ssize_t len) 461{ 462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 464 u32 *data = frame; 465 int i; 466 467 intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), 468 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 469 470 for (i = 0; i < len; i += 4) 471 *data++ = intel_de_read(dev_priv, 472 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 473} 474 475static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 476 const struct intel_crtc_state *pipe_config) 477{ 478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 479 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 480 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 481 482 if ((val & VIDEO_DIP_ENABLE) == 0) 483 return 0; 484 485 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 486 return 0; 487 488 return val & (VIDEO_DIP_ENABLE_AVI | 489 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 490 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 491} 492 493void hsw_write_infoframe(struct intel_encoder *encoder, 494 const struct intel_crtc_state *crtc_state, 495 unsigned int type, 496 const void *frame, ssize_t len) 497{ 498 const u32 *data = frame; 499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 500 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 501 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 502 int data_size; 503 int i; 504 u32 val = intel_de_read(dev_priv, ctl_reg); 505 506 data_size = hsw_dip_data_size(dev_priv, type); 507 508 drm_WARN_ON(&dev_priv->drm, len > data_size); 509 510 val &= ~hsw_infoframe_enable(type); 511 intel_de_write(dev_priv, ctl_reg, val); 512 513 for (i = 0; i < len; i += 4) { 514 intel_de_write(dev_priv, 515 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 516 *data); 517 data++; 518 } 519 /* Write every possible data byte to force correct ECC calculation. */ 520 for (; i < data_size; i += 4) 521 intel_de_write(dev_priv, 522 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 523 0); 524 525 /* Wa_14013475917 */ 526 if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC) 527 return; 528 529 val |= hsw_infoframe_enable(type); 530 intel_de_write(dev_priv, ctl_reg, val); 531 intel_de_posting_read(dev_priv, ctl_reg); 532} 533 534void hsw_read_infoframe(struct intel_encoder *encoder, 535 const struct intel_crtc_state *crtc_state, 536 unsigned int type, void *frame, ssize_t len) 537{ 538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 539 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 540 u32 *data = frame; 541 int i; 542 543 for (i = 0; i < len; i += 4) 544 *data++ = intel_de_read(dev_priv, 545 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 546} 547 548static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 549 const struct intel_crtc_state *pipe_config) 550{ 551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 552 u32 val = intel_de_read(dev_priv, 553 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 554 u32 mask; 555 556 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 557 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 558 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 559 560 if (DISPLAY_VER(dev_priv) >= 10) 561 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 562 563 return val & mask; 564} 565 566static const u8 infoframe_type_to_idx[] = { 567 HDMI_PACKET_TYPE_GENERAL_CONTROL, 568 HDMI_PACKET_TYPE_GAMUT_METADATA, 569 DP_SDP_VSC, 570 HDMI_INFOFRAME_TYPE_AVI, 571 HDMI_INFOFRAME_TYPE_SPD, 572 HDMI_INFOFRAME_TYPE_VENDOR, 573 HDMI_INFOFRAME_TYPE_DRM, 574}; 575 576u32 intel_hdmi_infoframe_enable(unsigned int type) 577{ 578 int i; 579 580 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 581 if (infoframe_type_to_idx[i] == type) 582 return BIT(i); 583 } 584 585 return 0; 586} 587 588u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 589 const struct intel_crtc_state *crtc_state) 590{ 591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 592 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 593 u32 val, ret = 0; 594 int i; 595 596 val = dig_port->infoframes_enabled(encoder, crtc_state); 597 598 /* map from hardware bits to dip idx */ 599 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 600 unsigned int type = infoframe_type_to_idx[i]; 601 602 if (HAS_DDI(dev_priv)) { 603 if (val & hsw_infoframe_enable(type)) 604 ret |= BIT(i); 605 } else { 606 if (val & g4x_infoframe_enable(type)) 607 ret |= BIT(i); 608 } 609 } 610 611 return ret; 612} 613 614/* 615 * The data we write to the DIP data buffer registers is 1 byte bigger than the 616 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 617 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 618 * used for both technologies. 619 * 620 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 621 * DW1: DB3 | DB2 | DB1 | DB0 622 * DW2: DB7 | DB6 | DB5 | DB4 623 * DW3: ... 624 * 625 * (HB is Header Byte, DB is Data Byte) 626 * 627 * The hdmi pack() functions don't know about that hardware specific hole so we 628 * trick them by giving an offset into the buffer and moving back the header 629 * bytes by one. 630 */ 631static void intel_write_infoframe(struct intel_encoder *encoder, 632 const struct intel_crtc_state *crtc_state, 633 enum hdmi_infoframe_type type, 634 const union hdmi_infoframe *frame) 635{ 636 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 637 u8 buffer[VIDEO_DIP_DATA_SIZE]; 638 ssize_t len; 639 640 if ((crtc_state->infoframes.enable & 641 intel_hdmi_infoframe_enable(type)) == 0) 642 return; 643 644 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 645 return; 646 647 /* see comment above for the reason for this offset */ 648 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 649 if (drm_WARN_ON(encoder->base.dev, len < 0)) 650 return; 651 652 /* Insert the 'hole' (see big comment above) at position 3 */ 653 memmove(&buffer[0], &buffer[1], 3); 654 buffer[3] = 0; 655 len++; 656 657 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 658} 659 660void intel_read_infoframe(struct intel_encoder *encoder, 661 const struct intel_crtc_state *crtc_state, 662 enum hdmi_infoframe_type type, 663 union hdmi_infoframe *frame) 664{ 665 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 666 u8 buffer[VIDEO_DIP_DATA_SIZE]; 667 int ret; 668 669 if ((crtc_state->infoframes.enable & 670 intel_hdmi_infoframe_enable(type)) == 0) 671 return; 672 673 dig_port->read_infoframe(encoder, crtc_state, 674 type, buffer, sizeof(buffer)); 675 676 /* Fill the 'hole' (see big comment above) at position 3 */ 677 memmove(&buffer[1], &buffer[0], 3); 678 679 /* see comment above for the reason for this offset */ 680 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 681 if (ret) { 682 drm_dbg_kms(encoder->base.dev, 683 "Failed to unpack infoframe type 0x%02x\n", type); 684 return; 685 } 686 687 if (frame->any.type != type) 688 drm_dbg_kms(encoder->base.dev, 689 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 690 frame->any.type, type); 691} 692 693static bool 694intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 695 struct intel_crtc_state *crtc_state, 696 struct drm_connector_state *conn_state) 697{ 698 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 699 const struct drm_display_mode *adjusted_mode = 700 &crtc_state->hw.adjusted_mode; 701 struct drm_connector *connector = conn_state->connector; 702 int ret; 703 704 if (!crtc_state->has_infoframe) 705 return true; 706 707 crtc_state->infoframes.enable |= 708 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 709 710 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 711 adjusted_mode); 712 if (ret) 713 return false; 714 715 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 716 frame->colorspace = HDMI_COLORSPACE_YUV420; 717 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 718 frame->colorspace = HDMI_COLORSPACE_YUV444; 719 else 720 frame->colorspace = HDMI_COLORSPACE_RGB; 721 722 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 723 724 /* nonsense combination */ 725 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 726 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 727 728 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 729 drm_hdmi_avi_infoframe_quant_range(frame, connector, 730 adjusted_mode, 731 crtc_state->limited_color_range ? 732 HDMI_QUANTIZATION_RANGE_LIMITED : 733 HDMI_QUANTIZATION_RANGE_FULL); 734 } else { 735 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 736 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 737 } 738 739 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 740 741 /* TODO: handle pixel repetition for YCBCR420 outputs */ 742 743 ret = hdmi_avi_infoframe_check(frame); 744 if (drm_WARN_ON(encoder->base.dev, ret)) 745 return false; 746 747 return true; 748} 749 750static bool 751intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 752 struct intel_crtc_state *crtc_state, 753 struct drm_connector_state *conn_state) 754{ 755 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 756 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 757 int ret; 758 759 if (!crtc_state->has_infoframe) 760 return true; 761 762 crtc_state->infoframes.enable |= 763 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 764 765 if (IS_DGFX(i915)) 766 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 767 else 768 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 769 770 if (drm_WARN_ON(encoder->base.dev, ret)) 771 return false; 772 773 frame->sdi = HDMI_SPD_SDI_PC; 774 775 ret = hdmi_spd_infoframe_check(frame); 776 if (drm_WARN_ON(encoder->base.dev, ret)) 777 return false; 778 779 return true; 780} 781 782static bool 783intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 784 struct intel_crtc_state *crtc_state, 785 struct drm_connector_state *conn_state) 786{ 787 struct hdmi_vendor_infoframe *frame = 788 &crtc_state->infoframes.hdmi.vendor.hdmi; 789 const struct drm_display_info *info = 790 &conn_state->connector->display_info; 791 int ret; 792 793 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 794 return true; 795 796 crtc_state->infoframes.enable |= 797 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 798 799 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 800 conn_state->connector, 801 &crtc_state->hw.adjusted_mode); 802 if (drm_WARN_ON(encoder->base.dev, ret)) 803 return false; 804 805 ret = hdmi_vendor_infoframe_check(frame); 806 if (drm_WARN_ON(encoder->base.dev, ret)) 807 return false; 808 809 return true; 810} 811 812static bool 813intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 814 struct intel_crtc_state *crtc_state, 815 struct drm_connector_state *conn_state) 816{ 817 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 819 int ret; 820 821 if (DISPLAY_VER(dev_priv) < 10) 822 return true; 823 824 if (!crtc_state->has_infoframe) 825 return true; 826 827 if (!conn_state->hdr_output_metadata) 828 return true; 829 830 crtc_state->infoframes.enable |= 831 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 832 833 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 834 if (ret < 0) { 835 drm_dbg_kms(&dev_priv->drm, 836 "couldn't set HDR metadata in infoframe\n"); 837 return false; 838 } 839 840 ret = hdmi_drm_infoframe_check(frame); 841 if (drm_WARN_ON(&dev_priv->drm, ret)) 842 return false; 843 844 return true; 845} 846 847static void g4x_set_infoframes(struct intel_encoder *encoder, 848 bool enable, 849 const struct intel_crtc_state *crtc_state, 850 const struct drm_connector_state *conn_state) 851{ 852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 853 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 854 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 855 i915_reg_t reg = VIDEO_DIP_CTL; 856 u32 val = intel_de_read(dev_priv, reg); 857 u32 port = VIDEO_DIP_PORT(encoder->port); 858 859 assert_hdmi_port_disabled(intel_hdmi); 860 861 /* If the registers were not initialized yet, they might be zeroes, 862 * which means we're selecting the AVI DIP and we're setting its 863 * frequency to once. This seems to really confuse the HW and make 864 * things stop working (the register spec says the AVI always needs to 865 * be sent every VSync). So here we avoid writing to the register more 866 * than we need and also explicitly select the AVI DIP and explicitly 867 * set its frequency to every VSync. Avoiding to write it twice seems to 868 * be enough to solve the problem, but being defensive shouldn't hurt us 869 * either. */ 870 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 871 872 if (!enable) { 873 if (!(val & VIDEO_DIP_ENABLE)) 874 return; 875 if (port != (val & VIDEO_DIP_PORT_MASK)) { 876 drm_dbg_kms(&dev_priv->drm, 877 "video DIP still enabled on port %c\n", 878 (val & VIDEO_DIP_PORT_MASK) >> 29); 879 return; 880 } 881 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 882 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 883 intel_de_write(dev_priv, reg, val); 884 intel_de_posting_read(dev_priv, reg); 885 return; 886 } 887 888 if (port != (val & VIDEO_DIP_PORT_MASK)) { 889 if (val & VIDEO_DIP_ENABLE) { 890 drm_dbg_kms(&dev_priv->drm, 891 "video DIP already enabled on port %c\n", 892 (val & VIDEO_DIP_PORT_MASK) >> 29); 893 return; 894 } 895 val &= ~VIDEO_DIP_PORT_MASK; 896 val |= port; 897 } 898 899 val |= VIDEO_DIP_ENABLE; 900 val &= ~(VIDEO_DIP_ENABLE_AVI | 901 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 902 903 intel_de_write(dev_priv, reg, val); 904 intel_de_posting_read(dev_priv, reg); 905 906 intel_write_infoframe(encoder, crtc_state, 907 HDMI_INFOFRAME_TYPE_AVI, 908 &crtc_state->infoframes.avi); 909 intel_write_infoframe(encoder, crtc_state, 910 HDMI_INFOFRAME_TYPE_SPD, 911 &crtc_state->infoframes.spd); 912 intel_write_infoframe(encoder, crtc_state, 913 HDMI_INFOFRAME_TYPE_VENDOR, 914 &crtc_state->infoframes.hdmi); 915} 916 917/* 918 * Determine if default_phase=1 can be indicated in the GCP infoframe. 919 * 920 * From HDMI specification 1.4a: 921 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 922 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 923 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 924 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 925 * phase of 0 926 */ 927static bool gcp_default_phase_possible(int pipe_bpp, 928 const struct drm_display_mode *mode) 929{ 930 unsigned int pixels_per_group; 931 932 switch (pipe_bpp) { 933 case 30: 934 /* 4 pixels in 5 clocks */ 935 pixels_per_group = 4; 936 break; 937 case 36: 938 /* 2 pixels in 3 clocks */ 939 pixels_per_group = 2; 940 break; 941 case 48: 942 /* 1 pixel in 2 clocks */ 943 pixels_per_group = 1; 944 break; 945 default: 946 /* phase information not relevant for 8bpc */ 947 return false; 948 } 949 950 return mode->crtc_hdisplay % pixels_per_group == 0 && 951 mode->crtc_htotal % pixels_per_group == 0 && 952 mode->crtc_hblank_start % pixels_per_group == 0 && 953 mode->crtc_hblank_end % pixels_per_group == 0 && 954 mode->crtc_hsync_start % pixels_per_group == 0 && 955 mode->crtc_hsync_end % pixels_per_group == 0 && 956 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 957 mode->crtc_htotal/2 % pixels_per_group == 0); 958} 959 960static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 961 const struct intel_crtc_state *crtc_state, 962 const struct drm_connector_state *conn_state) 963{ 964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 966 i915_reg_t reg; 967 968 if ((crtc_state->infoframes.enable & 969 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 970 return false; 971 972 if (HAS_DDI(dev_priv)) 973 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 974 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 975 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 976 else if (HAS_PCH_SPLIT(dev_priv)) 977 reg = TVIDEO_DIP_GCP(crtc->pipe); 978 else 979 return false; 980 981 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 982 983 return true; 984} 985 986void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 987 struct intel_crtc_state *crtc_state) 988{ 989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 991 i915_reg_t reg; 992 993 if ((crtc_state->infoframes.enable & 994 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 995 return; 996 997 if (HAS_DDI(dev_priv)) 998 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 999 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1000 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1001 else if (HAS_PCH_SPLIT(dev_priv)) 1002 reg = TVIDEO_DIP_GCP(crtc->pipe); 1003 else 1004 return; 1005 1006 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1007} 1008 1009static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1010 struct intel_crtc_state *crtc_state, 1011 struct drm_connector_state *conn_state) 1012{ 1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1014 1015 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1016 return; 1017 1018 crtc_state->infoframes.enable |= 1019 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1020 1021 /* Indicate color indication for deep color mode */ 1022 if (crtc_state->pipe_bpp > 24) 1023 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1024 1025 /* Enable default_phase whenever the display mode is suitably aligned */ 1026 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1027 &crtc_state->hw.adjusted_mode)) 1028 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1029} 1030 1031static void ibx_set_infoframes(struct intel_encoder *encoder, 1032 bool enable, 1033 const struct intel_crtc_state *crtc_state, 1034 const struct drm_connector_state *conn_state) 1035{ 1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1037 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1038 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1039 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1040 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1041 u32 val = intel_de_read(dev_priv, reg); 1042 u32 port = VIDEO_DIP_PORT(encoder->port); 1043 1044 assert_hdmi_port_disabled(intel_hdmi); 1045 1046 /* See the big comment in g4x_set_infoframes() */ 1047 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1048 1049 if (!enable) { 1050 if (!(val & VIDEO_DIP_ENABLE)) 1051 return; 1052 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1053 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1054 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1055 intel_de_write(dev_priv, reg, val); 1056 intel_de_posting_read(dev_priv, reg); 1057 return; 1058 } 1059 1060 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1061 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1062 "DIP already enabled on port %c\n", 1063 (val & VIDEO_DIP_PORT_MASK) >> 29); 1064 val &= ~VIDEO_DIP_PORT_MASK; 1065 val |= port; 1066 } 1067 1068 val |= VIDEO_DIP_ENABLE; 1069 val &= ~(VIDEO_DIP_ENABLE_AVI | 1070 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1071 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1072 1073 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1074 val |= VIDEO_DIP_ENABLE_GCP; 1075 1076 intel_de_write(dev_priv, reg, val); 1077 intel_de_posting_read(dev_priv, reg); 1078 1079 intel_write_infoframe(encoder, crtc_state, 1080 HDMI_INFOFRAME_TYPE_AVI, 1081 &crtc_state->infoframes.avi); 1082 intel_write_infoframe(encoder, crtc_state, 1083 HDMI_INFOFRAME_TYPE_SPD, 1084 &crtc_state->infoframes.spd); 1085 intel_write_infoframe(encoder, crtc_state, 1086 HDMI_INFOFRAME_TYPE_VENDOR, 1087 &crtc_state->infoframes.hdmi); 1088} 1089 1090static void cpt_set_infoframes(struct intel_encoder *encoder, 1091 bool enable, 1092 const struct intel_crtc_state *crtc_state, 1093 const struct drm_connector_state *conn_state) 1094{ 1095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1096 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1097 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1098 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1099 u32 val = intel_de_read(dev_priv, reg); 1100 1101 assert_hdmi_port_disabled(intel_hdmi); 1102 1103 /* See the big comment in g4x_set_infoframes() */ 1104 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1105 1106 if (!enable) { 1107 if (!(val & VIDEO_DIP_ENABLE)) 1108 return; 1109 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1110 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1111 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1112 intel_de_write(dev_priv, reg, val); 1113 intel_de_posting_read(dev_priv, reg); 1114 return; 1115 } 1116 1117 /* Set both together, unset both together: see the spec. */ 1118 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1119 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1120 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1121 1122 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1123 val |= VIDEO_DIP_ENABLE_GCP; 1124 1125 intel_de_write(dev_priv, reg, val); 1126 intel_de_posting_read(dev_priv, reg); 1127 1128 intel_write_infoframe(encoder, crtc_state, 1129 HDMI_INFOFRAME_TYPE_AVI, 1130 &crtc_state->infoframes.avi); 1131 intel_write_infoframe(encoder, crtc_state, 1132 HDMI_INFOFRAME_TYPE_SPD, 1133 &crtc_state->infoframes.spd); 1134 intel_write_infoframe(encoder, crtc_state, 1135 HDMI_INFOFRAME_TYPE_VENDOR, 1136 &crtc_state->infoframes.hdmi); 1137} 1138 1139static void vlv_set_infoframes(struct intel_encoder *encoder, 1140 bool enable, 1141 const struct intel_crtc_state *crtc_state, 1142 const struct drm_connector_state *conn_state) 1143{ 1144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1146 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1147 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1148 u32 val = intel_de_read(dev_priv, reg); 1149 u32 port = VIDEO_DIP_PORT(encoder->port); 1150 1151 assert_hdmi_port_disabled(intel_hdmi); 1152 1153 /* See the big comment in g4x_set_infoframes() */ 1154 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1155 1156 if (!enable) { 1157 if (!(val & VIDEO_DIP_ENABLE)) 1158 return; 1159 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1160 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1161 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1162 intel_de_write(dev_priv, reg, val); 1163 intel_de_posting_read(dev_priv, reg); 1164 return; 1165 } 1166 1167 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1168 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1169 "DIP already enabled on port %c\n", 1170 (val & VIDEO_DIP_PORT_MASK) >> 29); 1171 val &= ~VIDEO_DIP_PORT_MASK; 1172 val |= port; 1173 } 1174 1175 val |= VIDEO_DIP_ENABLE; 1176 val &= ~(VIDEO_DIP_ENABLE_AVI | 1177 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1178 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1179 1180 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1181 val |= VIDEO_DIP_ENABLE_GCP; 1182 1183 intel_de_write(dev_priv, reg, val); 1184 intel_de_posting_read(dev_priv, reg); 1185 1186 intel_write_infoframe(encoder, crtc_state, 1187 HDMI_INFOFRAME_TYPE_AVI, 1188 &crtc_state->infoframes.avi); 1189 intel_write_infoframe(encoder, crtc_state, 1190 HDMI_INFOFRAME_TYPE_SPD, 1191 &crtc_state->infoframes.spd); 1192 intel_write_infoframe(encoder, crtc_state, 1193 HDMI_INFOFRAME_TYPE_VENDOR, 1194 &crtc_state->infoframes.hdmi); 1195} 1196 1197static void hsw_set_infoframes(struct intel_encoder *encoder, 1198 bool enable, 1199 const struct intel_crtc_state *crtc_state, 1200 const struct drm_connector_state *conn_state) 1201{ 1202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1203 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1204 u32 val = intel_de_read(dev_priv, reg); 1205 1206 assert_hdmi_transcoder_func_disabled(dev_priv, 1207 crtc_state->cpu_transcoder); 1208 1209 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1210 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1211 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1212 VIDEO_DIP_ENABLE_DRM_GLK); 1213 1214 if (!enable) { 1215 intel_de_write(dev_priv, reg, val); 1216 intel_de_posting_read(dev_priv, reg); 1217 return; 1218 } 1219 1220 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1221 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1222 1223 intel_de_write(dev_priv, reg, val); 1224 intel_de_posting_read(dev_priv, reg); 1225 1226 intel_write_infoframe(encoder, crtc_state, 1227 HDMI_INFOFRAME_TYPE_AVI, 1228 &crtc_state->infoframes.avi); 1229 intel_write_infoframe(encoder, crtc_state, 1230 HDMI_INFOFRAME_TYPE_SPD, 1231 &crtc_state->infoframes.spd); 1232 intel_write_infoframe(encoder, crtc_state, 1233 HDMI_INFOFRAME_TYPE_VENDOR, 1234 &crtc_state->infoframes.hdmi); 1235 intel_write_infoframe(encoder, crtc_state, 1236 HDMI_INFOFRAME_TYPE_DRM, 1237 &crtc_state->infoframes.drm); 1238} 1239 1240void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1241{ 1242 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1243 struct i2c_adapter *adapter; 1244 1245 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1246 return; 1247 1248 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1249 1250 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1251 enable ? "Enabling" : "Disabling"); 1252 1253 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); 1254} 1255 1256static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1257 unsigned int offset, void *buffer, size_t size) 1258{ 1259 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1260 struct intel_hdmi *hdmi = &dig_port->hdmi; 1261 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1262 hdmi->ddc_bus); 1263 int ret; 1264 u8 start = offset & 0xff; 1265 struct i2c_msg msgs[] = { 1266 { 1267 .addr = DRM_HDCP_DDC_ADDR, 1268 .flags = 0, 1269 .len = 1, 1270 .buf = &start, 1271 }, 1272 { 1273 .addr = DRM_HDCP_DDC_ADDR, 1274 .flags = I2C_M_RD, 1275 .len = size, 1276 .buf = buffer 1277 } 1278 }; 1279 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1280 if (ret == ARRAY_SIZE(msgs)) 1281 return 0; 1282 return ret >= 0 ? -EIO : ret; 1283} 1284 1285static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1286 unsigned int offset, void *buffer, size_t size) 1287{ 1288 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1289 struct intel_hdmi *hdmi = &dig_port->hdmi; 1290 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1291 hdmi->ddc_bus); 1292 int ret; 1293 u8 *write_buf; 1294 struct i2c_msg msg; 1295 1296 write_buf = kzalloc(size + 1, GFP_KERNEL); 1297 if (!write_buf) 1298 return -ENOMEM; 1299 1300 write_buf[0] = offset & 0xff; 1301 memcpy(&write_buf[1], buffer, size); 1302 1303 msg.addr = DRM_HDCP_DDC_ADDR; 1304 msg.flags = 0, 1305 msg.len = size + 1, 1306 msg.buf = write_buf; 1307 1308 ret = i2c_transfer(adapter, &msg, 1); 1309 if (ret == 1) 1310 ret = 0; 1311 else if (ret >= 0) 1312 ret = -EIO; 1313 1314 kfree(write_buf); 1315 return ret; 1316} 1317 1318static 1319int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1320 u8 *an) 1321{ 1322 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1323 struct intel_hdmi *hdmi = &dig_port->hdmi; 1324 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1325 hdmi->ddc_bus); 1326 int ret; 1327 1328 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1329 DRM_HDCP_AN_LEN); 1330 if (ret) { 1331 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1332 ret); 1333 return ret; 1334 } 1335 1336 ret = intel_gmbus_output_aksv(adapter); 1337 if (ret < 0) { 1338 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1339 return ret; 1340 } 1341 return 0; 1342} 1343 1344static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1345 u8 *bksv) 1346{ 1347 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1348 1349 int ret; 1350 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1351 DRM_HDCP_KSV_LEN); 1352 if (ret) 1353 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1354 ret); 1355 return ret; 1356} 1357 1358static 1359int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1360 u8 *bstatus) 1361{ 1362 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1363 1364 int ret; 1365 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1366 bstatus, DRM_HDCP_BSTATUS_LEN); 1367 if (ret) 1368 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1369 ret); 1370 return ret; 1371} 1372 1373static 1374int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1375 bool *repeater_present) 1376{ 1377 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1378 int ret; 1379 u8 val; 1380 1381 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1382 if (ret) { 1383 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1384 ret); 1385 return ret; 1386 } 1387 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1388 return 0; 1389} 1390 1391static 1392int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1393 u8 *ri_prime) 1394{ 1395 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1396 1397 int ret; 1398 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1399 ri_prime, DRM_HDCP_RI_LEN); 1400 if (ret) 1401 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1402 ret); 1403 return ret; 1404} 1405 1406static 1407int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1408 bool *ksv_ready) 1409{ 1410 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1411 int ret; 1412 u8 val; 1413 1414 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1415 if (ret) { 1416 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1417 ret); 1418 return ret; 1419 } 1420 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1421 return 0; 1422} 1423 1424static 1425int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1426 int num_downstream, u8 *ksv_fifo) 1427{ 1428 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1429 int ret; 1430 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1431 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1432 if (ret) { 1433 drm_dbg_kms(&i915->drm, 1434 "Read ksv fifo over DDC failed (%d)\n", ret); 1435 return ret; 1436 } 1437 return 0; 1438} 1439 1440static 1441int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1442 int i, u32 *part) 1443{ 1444 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1445 int ret; 1446 1447 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1448 return -EINVAL; 1449 1450 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1451 part, DRM_HDCP_V_PRIME_PART_LEN); 1452 if (ret) 1453 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1454 i, ret); 1455 return ret; 1456} 1457 1458static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1459 enum transcoder cpu_transcoder) 1460{ 1461 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1462 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1463 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1464 u32 scanline; 1465 int ret; 1466 1467 for (;;) { 1468 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); 1469 if (scanline > 100 && scanline < 200) 1470 break; 1471 usleep_range(25, 50); 1472 } 1473 1474 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1475 false, TRANS_DDI_HDCP_SIGNALLING); 1476 if (ret) { 1477 drm_err(&dev_priv->drm, 1478 "Disable HDCP signalling failed (%d)\n", ret); 1479 return ret; 1480 } 1481 1482 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1483 true, TRANS_DDI_HDCP_SIGNALLING); 1484 if (ret) { 1485 drm_err(&dev_priv->drm, 1486 "Enable HDCP signalling failed (%d)\n", ret); 1487 return ret; 1488 } 1489 1490 return 0; 1491} 1492 1493static 1494int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1495 enum transcoder cpu_transcoder, 1496 bool enable) 1497{ 1498 struct intel_hdmi *hdmi = &dig_port->hdmi; 1499 struct intel_connector *connector = hdmi->attached_connector; 1500 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1501 int ret; 1502 1503 if (!enable) 1504 usleep_range(6, 60); /* Bspec says >= 6us */ 1505 1506 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1507 cpu_transcoder, enable, 1508 TRANS_DDI_HDCP_SIGNALLING); 1509 if (ret) { 1510 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1511 enable ? "Enable" : "Disable", ret); 1512 return ret; 1513 } 1514 1515 /* 1516 * WA: To fix incorrect positioning of the window of 1517 * opportunity and enc_en signalling in KABYLAKE. 1518 */ 1519 if (IS_KABYLAKE(dev_priv) && enable) 1520 return kbl_repositioning_enc_en_signal(connector, 1521 cpu_transcoder); 1522 1523 return 0; 1524} 1525 1526static 1527bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1528 struct intel_connector *connector) 1529{ 1530 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1531 enum port port = dig_port->base.port; 1532 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1533 int ret; 1534 union { 1535 u32 reg; 1536 u8 shim[DRM_HDCP_RI_LEN]; 1537 } ri; 1538 1539 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1540 if (ret) 1541 return false; 1542 1543 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1544 1545 /* Wait for Ri prime match */ 1546 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1547 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1548 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1549 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1550 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1551 port))); 1552 return false; 1553 } 1554 return true; 1555} 1556 1557static 1558bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1559 struct intel_connector *connector) 1560{ 1561 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1562 int retry; 1563 1564 for (retry = 0; retry < 3; retry++) 1565 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1566 return true; 1567 1568 drm_err(&i915->drm, "Link check failed\n"); 1569 return false; 1570} 1571 1572struct hdcp2_hdmi_msg_timeout { 1573 u8 msg_id; 1574 u16 timeout; 1575}; 1576 1577static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1578 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1579 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1580 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1581 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1582 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1583}; 1584 1585static 1586int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1587 u8 *rx_status) 1588{ 1589 return intel_hdmi_hdcp_read(dig_port, 1590 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1591 rx_status, 1592 HDCP_2_2_HDMI_RXSTATUS_LEN); 1593} 1594 1595static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1596{ 1597 int i; 1598 1599 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1600 if (is_paired) 1601 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1602 else 1603 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1604 } 1605 1606 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1607 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1608 return hdcp2_msg_timeout[i].timeout; 1609 } 1610 1611 return -EINVAL; 1612} 1613 1614static int 1615hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1616 u8 msg_id, bool *msg_ready, 1617 ssize_t *msg_sz) 1618{ 1619 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1620 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1621 int ret; 1622 1623 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1624 if (ret < 0) { 1625 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1626 ret); 1627 return ret; 1628 } 1629 1630 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1631 rx_status[0]); 1632 1633 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1634 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1635 *msg_sz); 1636 else 1637 *msg_ready = *msg_sz; 1638 1639 return 0; 1640} 1641 1642static ssize_t 1643intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1644 u8 msg_id, bool paired) 1645{ 1646 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1647 bool msg_ready = false; 1648 int timeout, ret; 1649 ssize_t msg_sz = 0; 1650 1651 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1652 if (timeout < 0) 1653 return timeout; 1654 1655 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1656 msg_id, &msg_ready, 1657 &msg_sz), 1658 !ret && msg_ready && msg_sz, timeout * 1000, 1659 1000, 5 * 1000); 1660 if (ret) 1661 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1662 msg_id, ret, timeout); 1663 1664 return ret ? ret : msg_sz; 1665} 1666 1667static 1668int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1669 void *buf, size_t size) 1670{ 1671 unsigned int offset; 1672 1673 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1674 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1675} 1676 1677static 1678int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1679 u8 msg_id, void *buf, size_t size) 1680{ 1681 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1682 struct intel_hdmi *hdmi = &dig_port->hdmi; 1683 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1684 unsigned int offset; 1685 ssize_t ret; 1686 1687 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1688 hdcp->is_paired); 1689 if (ret < 0) 1690 return ret; 1691 1692 /* 1693 * Available msg size should be equal to or lesser than the 1694 * available buffer. 1695 */ 1696 if (ret > size) { 1697 drm_dbg_kms(&i915->drm, 1698 "msg_sz(%zd) is more than exp size(%zu)\n", 1699 ret, size); 1700 return -EINVAL; 1701 } 1702 1703 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1704 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1705 if (ret) 1706 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1707 msg_id, ret); 1708 1709 return ret; 1710} 1711 1712static 1713int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1714 struct intel_connector *connector) 1715{ 1716 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1717 int ret; 1718 1719 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1720 if (ret) 1721 return ret; 1722 1723 /* 1724 * Re-auth request and Link Integrity Failures are represented by 1725 * same bit. i.e reauth_req. 1726 */ 1727 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1728 ret = HDCP_REAUTH_REQUEST; 1729 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1730 ret = HDCP_TOPOLOGY_CHANGE; 1731 1732 return ret; 1733} 1734 1735static 1736int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1737 bool *capable) 1738{ 1739 u8 hdcp2_version; 1740 int ret; 1741 1742 *capable = false; 1743 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1744 &hdcp2_version, sizeof(hdcp2_version)); 1745 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1746 *capable = true; 1747 1748 return ret; 1749} 1750 1751static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1752 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1753 .read_bksv = intel_hdmi_hdcp_read_bksv, 1754 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1755 .repeater_present = intel_hdmi_hdcp_repeater_present, 1756 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1757 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1758 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1759 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1760 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1761 .check_link = intel_hdmi_hdcp_check_link, 1762 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1763 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1764 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1765 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1766 .protocol = HDCP_PROTOCOL_HDMI, 1767}; 1768 1769static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1770{ 1771 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1772 int max_tmds_clock, vbt_max_tmds_clock; 1773 1774 if (DISPLAY_VER(dev_priv) >= 10) 1775 max_tmds_clock = 594000; 1776 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1777 max_tmds_clock = 300000; 1778 else if (DISPLAY_VER(dev_priv) >= 5) 1779 max_tmds_clock = 225000; 1780 else 1781 max_tmds_clock = 165000; 1782 1783 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1784 if (vbt_max_tmds_clock) 1785 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1786 1787 return max_tmds_clock; 1788} 1789 1790static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1791 const struct drm_connector_state *conn_state) 1792{ 1793 struct intel_connector *connector = hdmi->attached_connector; 1794 1795 return connector->base.display_info.is_hdmi && 1796 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1797} 1798 1799static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1800{ 1801 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1802} 1803 1804static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1805 bool respect_downstream_limits, 1806 bool has_hdmi_sink) 1807{ 1808 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1809 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1810 1811 if (respect_downstream_limits) { 1812 struct intel_connector *connector = hdmi->attached_connector; 1813 const struct drm_display_info *info = &connector->base.display_info; 1814 1815 if (hdmi->dp_dual_mode.max_tmds_clock) 1816 max_tmds_clock = min(max_tmds_clock, 1817 hdmi->dp_dual_mode.max_tmds_clock); 1818 1819 if (info->max_tmds_clock) 1820 max_tmds_clock = min(max_tmds_clock, 1821 info->max_tmds_clock); 1822 else if (!has_hdmi_sink) 1823 max_tmds_clock = min(max_tmds_clock, 165000); 1824 } 1825 1826 return max_tmds_clock; 1827} 1828 1829static enum drm_mode_status 1830hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1831 int clock, bool respect_downstream_limits, 1832 bool has_hdmi_sink) 1833{ 1834 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1835 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); 1836 1837 if (clock < 25000) 1838 return MODE_CLOCK_LOW; 1839 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1840 has_hdmi_sink)) 1841 return MODE_CLOCK_HIGH; 1842 1843 /* GLK DPLL can't generate 446-480 MHz */ 1844 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1845 return MODE_CLOCK_RANGE; 1846 1847 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1848 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1849 clock > 223333 && clock < 240000) 1850 return MODE_CLOCK_RANGE; 1851 1852 /* CHV DPLL can't generate 216-240 MHz */ 1853 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1854 return MODE_CLOCK_RANGE; 1855 1856 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1857 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) 1858 return MODE_CLOCK_RANGE; 1859 1860 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1861 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) 1862 return MODE_CLOCK_RANGE; 1863 1864 /* 1865 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1866 * set of link rates. 1867 * 1868 * FIXME: We will hopefully get an algorithmic way of programming 1869 * the MPLLB for HDMI in the future. 1870 */ 1871 if (DISPLAY_VER(dev_priv) >= 14) 1872 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); 1873 else if (IS_DG2(dev_priv)) 1874 return intel_snps_phy_check_hdmi_link_rate(clock); 1875 1876 return MODE_OK; 1877} 1878 1879int intel_hdmi_tmds_clock(int clock, int bpc, 1880 enum intel_output_format sink_format) 1881{ 1882 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1883 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1884 clock /= 2; 1885 1886 /* 1887 * Need to adjust the port link by: 1888 * 1.5x for 12bpc 1889 * 1.25x for 10bpc 1890 */ 1891 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1892} 1893 1894static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc) 1895{ 1896 switch (bpc) { 1897 case 12: 1898 return !HAS_GMCH(i915); 1899 case 10: 1900 return DISPLAY_VER(i915) >= 11; 1901 case 8: 1902 return true; 1903 default: 1904 MISSING_CASE(bpc); 1905 return false; 1906 } 1907} 1908 1909static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1910 int bpc, bool has_hdmi_sink, 1911 enum intel_output_format sink_format) 1912{ 1913 const struct drm_display_info *info = &connector->display_info; 1914 const struct drm_hdmi_info *hdmi = &info->hdmi; 1915 1916 switch (bpc) { 1917 case 12: 1918 if (!has_hdmi_sink) 1919 return false; 1920 1921 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1922 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1923 else 1924 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1925 case 10: 1926 if (!has_hdmi_sink) 1927 return false; 1928 1929 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1930 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1931 else 1932 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1933 case 8: 1934 return true; 1935 default: 1936 MISSING_CASE(bpc); 1937 return false; 1938 } 1939} 1940 1941static enum drm_mode_status 1942intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1943 bool has_hdmi_sink, 1944 enum intel_output_format sink_format) 1945{ 1946 struct drm_i915_private *i915 = to_i915(connector->dev); 1947 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1948 enum drm_mode_status status = MODE_OK; 1949 int bpc; 1950 1951 /* 1952 * Try all color depths since valid port clock range 1953 * can have holes. Any mode that can be used with at 1954 * least one color depth is accepted. 1955 */ 1956 for (bpc = 12; bpc >= 8; bpc -= 2) { 1957 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1958 1959 if (!intel_hdmi_source_bpc_possible(i915, bpc)) 1960 continue; 1961 1962 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) 1963 continue; 1964 1965 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1966 if (status == MODE_OK) 1967 return MODE_OK; 1968 } 1969 1970 /* can never happen */ 1971 drm_WARN_ON(&i915->drm, status == MODE_OK); 1972 1973 return status; 1974} 1975 1976static enum drm_mode_status 1977intel_hdmi_mode_valid(struct drm_connector *connector, 1978 struct drm_display_mode *mode) 1979{ 1980 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1981 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1982 enum drm_mode_status status; 1983 int clock = mode->clock; 1984 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1985 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1986 bool ycbcr_420_only; 1987 enum intel_output_format sink_format; 1988 1989 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 1990 if (status != MODE_OK) 1991 return status; 1992 1993 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1994 clock *= 2; 1995 1996 if (clock > max_dotclk) 1997 return MODE_CLOCK_HIGH; 1998 1999 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2000 if (!has_hdmi_sink) 2001 return MODE_CLOCK_LOW; 2002 clock *= 2; 2003 } 2004 2005 /* 2006 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2007 * enumerated only if FRL is supported. Current platforms do not support 2008 * FRL so prune the higher resolution modes that require doctclock more 2009 * than 600MHz. 2010 */ 2011 if (clock > 600000) 2012 return MODE_CLOCK_HIGH; 2013 2014 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2015 2016 if (ycbcr_420_only) 2017 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2018 else 2019 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2020 2021 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2022 if (status != MODE_OK) { 2023 if (ycbcr_420_only || 2024 !connector->ycbcr_420_allowed || 2025 !drm_mode_is_420_also(&connector->display_info, mode)) 2026 return status; 2027 2028 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2029 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2030 if (status != MODE_OK) 2031 return status; 2032 } 2033 2034 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2035} 2036 2037bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2038 int bpc, bool has_hdmi_sink) 2039{ 2040 struct drm_atomic_state *state = crtc_state->uapi.state; 2041 struct drm_connector_state *connector_state; 2042 struct drm_connector *connector; 2043 int i; 2044 2045 for_each_new_connector_in_state(state, connector, connector_state, i) { 2046 if (connector_state->crtc != crtc_state->uapi.crtc) 2047 continue; 2048 2049 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, 2050 crtc_state->sink_format)) 2051 return false; 2052 } 2053 2054 return true; 2055} 2056 2057static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2058{ 2059 struct drm_i915_private *dev_priv = 2060 to_i915(crtc_state->uapi.crtc->dev); 2061 const struct drm_display_mode *adjusted_mode = 2062 &crtc_state->hw.adjusted_mode; 2063 2064 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) 2065 return false; 2066 2067 /* Display Wa_1405510057:icl,ehl */ 2068 if (intel_hdmi_is_ycbcr420(crtc_state) && 2069 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2070 (adjusted_mode->crtc_hblank_end - 2071 adjusted_mode->crtc_hblank_start) % 8 == 2) 2072 return false; 2073 2074 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2075} 2076 2077static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2078 struct intel_crtc_state *crtc_state, 2079 int clock, bool respect_downstream_limits) 2080{ 2081 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2082 int bpc; 2083 2084 /* 2085 * pipe_bpp could already be below 8bpc due to FDI 2086 * bandwidth constraints. HDMI minimum is 8bpc however. 2087 */ 2088 bpc = max(crtc_state->pipe_bpp / 3, 8); 2089 2090 /* 2091 * We will never exceed downstream TMDS clock limits while 2092 * attempting deep color. If the user insists on forcing an 2093 * out of spec mode they will have to be satisfied with 8bpc. 2094 */ 2095 if (!respect_downstream_limits) 2096 bpc = 8; 2097 2098 for (; bpc >= 8; bpc -= 2) { 2099 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2100 crtc_state->sink_format); 2101 2102 if (hdmi_bpc_possible(crtc_state, bpc) && 2103 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2104 respect_downstream_limits, 2105 crtc_state->has_hdmi_sink) == MODE_OK) 2106 return bpc; 2107 } 2108 2109 return -EINVAL; 2110} 2111 2112static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2113 struct intel_crtc_state *crtc_state, 2114 bool respect_downstream_limits) 2115{ 2116 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2117 const struct drm_display_mode *adjusted_mode = 2118 &crtc_state->hw.adjusted_mode; 2119 int bpc, clock = adjusted_mode->crtc_clock; 2120 2121 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2122 clock *= 2; 2123 2124 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2125 respect_downstream_limits); 2126 if (bpc < 0) 2127 return bpc; 2128 2129 crtc_state->port_clock = 2130 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2131 2132 /* 2133 * pipe_bpp could already be below 8bpc due to 2134 * FDI bandwidth constraints. We shouldn't bump it 2135 * back up to the HDMI minimum 8bpc in that case. 2136 */ 2137 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2138 2139 drm_dbg_kms(&i915->drm, 2140 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2141 bpc, crtc_state->pipe_bpp); 2142 2143 return 0; 2144} 2145 2146bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2147 const struct drm_connector_state *conn_state) 2148{ 2149 const struct intel_digital_connector_state *intel_conn_state = 2150 to_intel_digital_connector_state(conn_state); 2151 const struct drm_display_mode *adjusted_mode = 2152 &crtc_state->hw.adjusted_mode; 2153 2154 /* 2155 * Our YCbCr output is always limited range. 2156 * crtc_state->limited_color_range only applies to RGB, 2157 * and it must never be set for YCbCr or we risk setting 2158 * some conflicting bits in TRANSCONF which will mess up 2159 * the colors on the monitor. 2160 */ 2161 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2162 return false; 2163 2164 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2165 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2166 return crtc_state->has_hdmi_sink && 2167 drm_default_rgb_quant_range(adjusted_mode) == 2168 HDMI_QUANTIZATION_RANGE_LIMITED; 2169 } else { 2170 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2171 } 2172} 2173 2174static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2175 const struct intel_crtc_state *crtc_state, 2176 const struct drm_connector_state *conn_state) 2177{ 2178 struct drm_connector *connector = conn_state->connector; 2179 const struct intel_digital_connector_state *intel_conn_state = 2180 to_intel_digital_connector_state(conn_state); 2181 2182 if (!crtc_state->has_hdmi_sink) 2183 return false; 2184 2185 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2186 return connector->display_info.has_audio; 2187 else 2188 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2189} 2190 2191static enum intel_output_format 2192intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2193 struct intel_connector *connector, 2194 bool ycbcr_420_output) 2195{ 2196 if (!crtc_state->has_hdmi_sink) 2197 return INTEL_OUTPUT_FORMAT_RGB; 2198 2199 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2200 return INTEL_OUTPUT_FORMAT_YCBCR420; 2201 else 2202 return INTEL_OUTPUT_FORMAT_RGB; 2203} 2204 2205static enum intel_output_format 2206intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2207{ 2208 return crtc_state->sink_format; 2209} 2210 2211static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2212 struct intel_crtc_state *crtc_state, 2213 const struct drm_connector_state *conn_state, 2214 bool respect_downstream_limits) 2215{ 2216 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2217 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2218 const struct drm_display_info *info = &connector->base.display_info; 2219 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2220 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2221 int ret; 2222 2223 crtc_state->sink_format = 2224 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2225 2226 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2227 drm_dbg_kms(&i915->drm, 2228 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2229 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2230 } 2231 2232 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2233 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2234 if (ret) { 2235 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2236 !crtc_state->has_hdmi_sink || 2237 !connector->base.ycbcr_420_allowed || 2238 !drm_mode_is_420_also(info, adjusted_mode)) 2239 return ret; 2240 2241 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2242 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2243 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2244 } 2245 2246 return ret; 2247} 2248 2249static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2250{ 2251 return crtc_state->uapi.encoder_mask && 2252 !is_power_of_2(crtc_state->uapi.encoder_mask); 2253} 2254 2255static bool source_supports_scrambling(struct intel_encoder *encoder) 2256{ 2257 /* 2258 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2259 * scrambling is supported. 2260 * But there seem to be cases where certain platforms that support 2261 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2262 * capped by VBT to less than 340MHz. 2263 * 2264 * In such cases when an HDMI2.0 sink is connected, it creates a 2265 * problem : the platform and the sink both support scrambling but the 2266 * HDMI 1.4 retimer chip doesn't. 2267 * 2268 * So go for scrambling, based on the max tmds clock taking into account, 2269 * restrictions coming from VBT. 2270 */ 2271 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2272} 2273 2274bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2275 const struct intel_crtc_state *crtc_state, 2276 const struct drm_connector_state *conn_state) 2277{ 2278 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2279 2280 return intel_has_hdmi_sink(hdmi, conn_state) && 2281 !intel_hdmi_is_cloned(crtc_state); 2282} 2283 2284int intel_hdmi_compute_config(struct intel_encoder *encoder, 2285 struct intel_crtc_state *pipe_config, 2286 struct drm_connector_state *conn_state) 2287{ 2288 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2289 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2290 struct drm_connector *connector = conn_state->connector; 2291 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2292 int ret; 2293 2294 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2295 return -EINVAL; 2296 2297 if (!connector->interlace_allowed && 2298 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2299 return -EINVAL; 2300 2301 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2302 2303 if (pipe_config->has_hdmi_sink) 2304 pipe_config->has_infoframe = true; 2305 2306 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2307 pipe_config->pixel_multiplier = 2; 2308 2309 pipe_config->has_audio = 2310 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2311 intel_audio_compute_config(encoder, pipe_config, conn_state); 2312 2313 /* 2314 * Try to respect downstream TMDS clock limits first, if 2315 * that fails assume the user might know something we don't. 2316 */ 2317 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2318 if (ret) 2319 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2320 if (ret) { 2321 drm_dbg_kms(&dev_priv->drm, 2322 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2323 pipe_config->hw.adjusted_mode.crtc_clock); 2324 return ret; 2325 } 2326 2327 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2328 ret = intel_panel_fitting(pipe_config, conn_state); 2329 if (ret) 2330 return ret; 2331 } 2332 2333 pipe_config->limited_color_range = 2334 intel_hdmi_limited_color_range(pipe_config, conn_state); 2335 2336 if (conn_state->picture_aspect_ratio) 2337 adjusted_mode->picture_aspect_ratio = 2338 conn_state->picture_aspect_ratio; 2339 2340 pipe_config->lane_count = 4; 2341 2342 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2343 if (scdc->scrambling.low_rates) 2344 pipe_config->hdmi_scrambling = true; 2345 2346 if (pipe_config->port_clock > 340000) { 2347 pipe_config->hdmi_scrambling = true; 2348 pipe_config->hdmi_high_tmds_clock_ratio = true; 2349 } 2350 } 2351 2352 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2353 conn_state); 2354 2355 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2356 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2357 return -EINVAL; 2358 } 2359 2360 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2361 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2362 return -EINVAL; 2363 } 2364 2365 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2366 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2367 return -EINVAL; 2368 } 2369 2370 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2371 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2372 return -EINVAL; 2373 } 2374 2375 return 0; 2376} 2377 2378void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2379{ 2380 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2381 2382 /* 2383 * Give a hand to buggy BIOSen which forget to turn 2384 * the TMDS output buffers back on after a reboot. 2385 */ 2386 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2387} 2388 2389static void 2390intel_hdmi_unset_edid(struct drm_connector *connector) 2391{ 2392 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2393 2394 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2395 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2396 2397 drm_edid_free(to_intel_connector(connector)->detect_edid); 2398 to_intel_connector(connector)->detect_edid = NULL; 2399} 2400 2401static void 2402intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2403{ 2404 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2405 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2406 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2407 struct i2c_adapter *adapter = 2408 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2409 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); 2410 2411 /* 2412 * Type 1 DVI adaptors are not required to implement any 2413 * registers, so we can't always detect their presence. 2414 * Ideally we should be able to check the state of the 2415 * CONFIG1 pin, but no such luck on our hardware. 2416 * 2417 * The only method left to us is to check the VBT to see 2418 * if the port is a dual mode capable DP port. 2419 */ 2420 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2421 if (!connector->force && 2422 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2423 drm_dbg_kms(&dev_priv->drm, 2424 "Assuming DP dual mode adaptor presence based on VBT\n"); 2425 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2426 } else { 2427 type = DRM_DP_DUAL_MODE_NONE; 2428 } 2429 } 2430 2431 if (type == DRM_DP_DUAL_MODE_NONE) 2432 return; 2433 2434 hdmi->dp_dual_mode.type = type; 2435 hdmi->dp_dual_mode.max_tmds_clock = 2436 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); 2437 2438 drm_dbg_kms(&dev_priv->drm, 2439 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2440 drm_dp_get_dual_mode_type_name(type), 2441 hdmi->dp_dual_mode.max_tmds_clock); 2442 2443 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2444 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && 2445 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2446 drm_dbg_kms(&dev_priv->drm, 2447 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2448 hdmi->dp_dual_mode.max_tmds_clock = 0; 2449 } 2450} 2451 2452static bool 2453intel_hdmi_set_edid(struct drm_connector *connector) 2454{ 2455 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2456 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2457 intel_wakeref_t wakeref; 2458 const struct drm_edid *drm_edid; 2459 const struct edid *edid; 2460 bool connected = false; 2461 struct i2c_adapter *i2c; 2462 2463 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2464 2465 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2466 2467 drm_edid = drm_edid_read_ddc(connector, i2c); 2468 2469 if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) { 2470 drm_dbg_kms(&dev_priv->drm, 2471 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2472 intel_gmbus_force_bit(i2c, true); 2473 drm_edid = drm_edid_read_ddc(connector, i2c); 2474 intel_gmbus_force_bit(i2c, false); 2475 } 2476 2477 /* Below we depend on display info having been updated */ 2478 drm_edid_connector_update(connector, drm_edid); 2479 2480 to_intel_connector(connector)->detect_edid = drm_edid; 2481 2482 /* FIXME: Get rid of drm_edid_raw() */ 2483 edid = drm_edid_raw(drm_edid); 2484 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2485 intel_hdmi_dp_dual_mode_detect(connector); 2486 2487 connected = true; 2488 } 2489 2490 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2491 2492 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2493 2494 return connected; 2495} 2496 2497static enum drm_connector_status 2498intel_hdmi_detect(struct drm_connector *connector, bool force) 2499{ 2500 enum drm_connector_status status = connector_status_disconnected; 2501 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2502 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2503 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2504 intel_wakeref_t wakeref; 2505 2506 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2507 connector->base.id, connector->name); 2508 2509 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2510 return connector_status_disconnected; 2511 2512 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2513 2514 if (DISPLAY_VER(dev_priv) >= 11 && 2515 !intel_digital_port_connected(encoder)) 2516 goto out; 2517 2518 intel_hdmi_unset_edid(connector); 2519 2520 if (intel_hdmi_set_edid(connector)) 2521 status = connector_status_connected; 2522 2523out: 2524 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2525 2526 if (status != connector_status_connected) 2527 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2528 2529 /* 2530 * Make sure the refs for power wells enabled during detect are 2531 * dropped to avoid a new detect cycle triggered by HPD polling. 2532 */ 2533 intel_display_power_flush_work(dev_priv); 2534 2535 return status; 2536} 2537 2538static void 2539intel_hdmi_force(struct drm_connector *connector) 2540{ 2541 struct drm_i915_private *i915 = to_i915(connector->dev); 2542 2543 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2544 connector->base.id, connector->name); 2545 2546 intel_hdmi_unset_edid(connector); 2547 2548 if (connector->status != connector_status_connected) 2549 return; 2550 2551 intel_hdmi_set_edid(connector); 2552} 2553 2554static int intel_hdmi_get_modes(struct drm_connector *connector) 2555{ 2556 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2557 return drm_edid_connector_add_modes(connector); 2558} 2559 2560static struct i2c_adapter * 2561intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2562{ 2563 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2564 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2565 2566 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2567} 2568 2569static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2570{ 2571#ifdef __linux__ 2572 struct drm_i915_private *i915 = to_i915(connector->dev); 2573 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2574 struct kobject *i2c_kobj = &adapter->dev.kobj; 2575 struct kobject *connector_kobj = &connector->kdev->kobj; 2576 int ret; 2577 2578 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2579 if (ret) 2580 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2581#endif 2582} 2583 2584static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2585{ 2586#ifdef __linux__ 2587 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2588 struct kobject *i2c_kobj = &adapter->dev.kobj; 2589 struct kobject *connector_kobj = &connector->kdev->kobj; 2590 2591 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2592#endif 2593} 2594 2595static int 2596intel_hdmi_connector_register(struct drm_connector *connector) 2597{ 2598 int ret; 2599 2600 ret = intel_connector_register(connector); 2601 if (ret) 2602 return ret; 2603 2604 intel_hdmi_create_i2c_symlink(connector); 2605 2606 return ret; 2607} 2608 2609static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2610{ 2611 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2612 2613 cec_notifier_conn_unregister(n); 2614 2615 intel_hdmi_remove_i2c_symlink(connector); 2616 intel_connector_unregister(connector); 2617} 2618 2619static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2620 .detect = intel_hdmi_detect, 2621 .force = intel_hdmi_force, 2622 .fill_modes = drm_helper_probe_single_connector_modes, 2623 .atomic_get_property = intel_digital_connector_atomic_get_property, 2624 .atomic_set_property = intel_digital_connector_atomic_set_property, 2625 .late_register = intel_hdmi_connector_register, 2626 .early_unregister = intel_hdmi_connector_unregister, 2627 .destroy = intel_connector_destroy, 2628 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2629 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2630}; 2631 2632static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, 2633 struct drm_atomic_state *state) 2634{ 2635 struct drm_i915_private *i915 = to_i915(state->dev); 2636 2637 if (HAS_DDI(i915)) 2638 return intel_digital_connector_atomic_check(connector, state); 2639 else 2640 return g4x_hdmi_connector_atomic_check(connector, state); 2641} 2642 2643static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2644 .get_modes = intel_hdmi_get_modes, 2645 .mode_valid = intel_hdmi_mode_valid, 2646 .atomic_check = intel_hdmi_connector_atomic_check, 2647}; 2648 2649static void 2650intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2651{ 2652 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2653 2654 intel_attach_force_audio_property(connector); 2655 intel_attach_broadcast_rgb_property(connector); 2656 intel_attach_aspect_ratio_property(connector); 2657 2658 intel_attach_hdmi_colorspace_property(connector); 2659 drm_connector_attach_content_type_property(connector); 2660 2661 if (DISPLAY_VER(dev_priv) >= 10) 2662 drm_connector_attach_hdr_output_metadata_property(connector); 2663 2664 if (!HAS_GMCH(dev_priv)) 2665 drm_connector_attach_max_bpc_property(connector, 8, 12); 2666} 2667 2668/* 2669 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2670 * @encoder: intel_encoder 2671 * @connector: drm_connector 2672 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2673 * or reset the high tmds clock ratio for scrambling 2674 * @scrambling: bool to Indicate if the function needs to set or reset 2675 * sink scrambling 2676 * 2677 * This function handles scrambling on HDMI 2.0 capable sinks. 2678 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2679 * it enables scrambling. This should be called before enabling the HDMI 2680 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2681 * detect a scrambled clock within 100 ms. 2682 * 2683 * Returns: 2684 * True on success, false on failure. 2685 */ 2686bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2687 struct drm_connector *connector, 2688 bool high_tmds_clock_ratio, 2689 bool scrambling) 2690{ 2691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2692 struct drm_scrambling *sink_scrambling = 2693 &connector->display_info.hdmi.scdc.scrambling; 2694 2695 if (!sink_scrambling->supported) 2696 return true; 2697 2698 drm_dbg_kms(&dev_priv->drm, 2699 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2700 connector->base.id, connector->name, 2701 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2702 2703 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2704 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && 2705 drm_scdc_set_scrambling(connector, scrambling); 2706} 2707 2708static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2709{ 2710 u8 ddc_pin; 2711 2712 switch (port) { 2713 case PORT_B: 2714 ddc_pin = GMBUS_PIN_DPB; 2715 break; 2716 case PORT_C: 2717 ddc_pin = GMBUS_PIN_DPC; 2718 break; 2719 case PORT_D: 2720 ddc_pin = GMBUS_PIN_DPD_CHV; 2721 break; 2722 default: 2723 MISSING_CASE(port); 2724 ddc_pin = GMBUS_PIN_DPB; 2725 break; 2726 } 2727 return ddc_pin; 2728} 2729 2730static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2731{ 2732 u8 ddc_pin; 2733 2734 switch (port) { 2735 case PORT_B: 2736 ddc_pin = GMBUS_PIN_1_BXT; 2737 break; 2738 case PORT_C: 2739 ddc_pin = GMBUS_PIN_2_BXT; 2740 break; 2741 default: 2742 MISSING_CASE(port); 2743 ddc_pin = GMBUS_PIN_1_BXT; 2744 break; 2745 } 2746 return ddc_pin; 2747} 2748 2749static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2750 enum port port) 2751{ 2752 u8 ddc_pin; 2753 2754 switch (port) { 2755 case PORT_B: 2756 ddc_pin = GMBUS_PIN_1_BXT; 2757 break; 2758 case PORT_C: 2759 ddc_pin = GMBUS_PIN_2_BXT; 2760 break; 2761 case PORT_D: 2762 ddc_pin = GMBUS_PIN_4_CNP; 2763 break; 2764 case PORT_F: 2765 ddc_pin = GMBUS_PIN_3_BXT; 2766 break; 2767 default: 2768 MISSING_CASE(port); 2769 ddc_pin = GMBUS_PIN_1_BXT; 2770 break; 2771 } 2772 return ddc_pin; 2773} 2774 2775static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2776{ 2777 enum phy phy = intel_port_to_phy(dev_priv, port); 2778 2779 if (intel_phy_is_combo(dev_priv, phy)) 2780 return GMBUS_PIN_1_BXT + port; 2781 else if (intel_phy_is_tc(dev_priv, phy)) 2782 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 2783 2784 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2785 return GMBUS_PIN_2_BXT; 2786} 2787 2788static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2789{ 2790 enum phy phy = intel_port_to_phy(dev_priv, port); 2791 u8 ddc_pin; 2792 2793 switch (phy) { 2794 case PHY_A: 2795 ddc_pin = GMBUS_PIN_1_BXT; 2796 break; 2797 case PHY_B: 2798 ddc_pin = GMBUS_PIN_2_BXT; 2799 break; 2800 case PHY_C: 2801 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2802 break; 2803 default: 2804 MISSING_CASE(phy); 2805 ddc_pin = GMBUS_PIN_1_BXT; 2806 break; 2807 } 2808 return ddc_pin; 2809} 2810 2811static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2812{ 2813 enum phy phy = intel_port_to_phy(dev_priv, port); 2814 2815 WARN_ON(port == PORT_C); 2816 2817 /* 2818 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2819 * final two outputs use type-c pins, even though they're actually 2820 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2821 * all outputs. 2822 */ 2823 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2824 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2825 2826 return GMBUS_PIN_1_BXT + phy; 2827} 2828 2829static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) 2830{ 2831 enum phy phy = intel_port_to_phy(i915, port); 2832 2833 drm_WARN_ON(&i915->drm, port == PORT_A); 2834 2835 /* 2836 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2837 * final two outputs use type-c pins, even though they're actually 2838 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2839 * all outputs. 2840 */ 2841 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2842 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2843 2844 return GMBUS_PIN_1_BXT + phy; 2845} 2846 2847static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2848{ 2849 return intel_port_to_phy(dev_priv, port) + 1; 2850} 2851 2852static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2853{ 2854 enum phy phy = intel_port_to_phy(dev_priv, port); 2855 2856 WARN_ON(port == PORT_B || port == PORT_C); 2857 2858 /* 2859 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2860 * except first combo output. 2861 */ 2862 if (phy == PHY_A) 2863 return GMBUS_PIN_1_BXT; 2864 2865 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2866} 2867 2868static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2869 enum port port) 2870{ 2871 u8 ddc_pin; 2872 2873 switch (port) { 2874 case PORT_B: 2875 ddc_pin = GMBUS_PIN_DPB; 2876 break; 2877 case PORT_C: 2878 ddc_pin = GMBUS_PIN_DPC; 2879 break; 2880 case PORT_D: 2881 ddc_pin = GMBUS_PIN_DPD; 2882 break; 2883 default: 2884 MISSING_CASE(port); 2885 ddc_pin = GMBUS_PIN_DPB; 2886 break; 2887 } 2888 return ddc_pin; 2889} 2890 2891static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2892{ 2893 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2894 enum port port = encoder->port; 2895 u8 ddc_pin; 2896 2897 if (IS_ALDERLAKE_S(dev_priv)) 2898 ddc_pin = adls_port_to_ddc_pin(dev_priv, port); 2899 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2900 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 2901 else if (IS_ROCKETLAKE(dev_priv)) 2902 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 2903 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2904 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); 2905 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && 2906 HAS_PCH_TGP(dev_priv)) 2907 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 2908 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2909 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 2910 else if (HAS_PCH_CNP(dev_priv)) 2911 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 2912 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2913 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 2914 else if (IS_CHERRYVIEW(dev_priv)) 2915 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 2916 else 2917 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 2918 2919 return ddc_pin; 2920} 2921 2922static struct intel_encoder * 2923get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2924{ 2925 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2926 struct intel_encoder *other; 2927 2928 for_each_intel_encoder(&i915->drm, other) { 2929 if (other == encoder) 2930 continue; 2931 2932 if (!intel_encoder_is_dig_port(other)) 2933 continue; 2934 2935 if (enc_to_dig_port(other)->hdmi.ddc_bus == ddc_pin) 2936 return other; 2937 } 2938 2939 return NULL; 2940} 2941 2942static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2943{ 2944 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2945 struct intel_encoder *other; 2946 const char *source; 2947 u8 ddc_pin; 2948 2949 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2950 source = "VBT"; 2951 2952 if (!ddc_pin) { 2953 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2954 source = "platform default"; 2955 } 2956 2957 if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) { 2958 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2959 encoder->base.base.id, encoder->base.name, ddc_pin); 2960 return 0; 2961 } 2962 2963 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2964 if (other) { 2965 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2966 encoder->base.base.id, encoder->base.name, ddc_pin, 2967 other->base.base.id, other->base.name); 2968 return 0; 2969 } 2970 2971 drm_dbg_kms(&i915->drm, 2972 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2973 encoder->base.base.id, encoder->base.name, 2974 ddc_pin, source); 2975 2976 return ddc_pin; 2977} 2978 2979void intel_infoframe_init(struct intel_digital_port *dig_port) 2980{ 2981 struct drm_i915_private *dev_priv = 2982 to_i915(dig_port->base.base.dev); 2983 2984 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2985 dig_port->write_infoframe = vlv_write_infoframe; 2986 dig_port->read_infoframe = vlv_read_infoframe; 2987 dig_port->set_infoframes = vlv_set_infoframes; 2988 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2989 } else if (IS_G4X(dev_priv)) { 2990 dig_port->write_infoframe = g4x_write_infoframe; 2991 dig_port->read_infoframe = g4x_read_infoframe; 2992 dig_port->set_infoframes = g4x_set_infoframes; 2993 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2994 } else if (HAS_DDI(dev_priv)) { 2995 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 2996 dig_port->write_infoframe = lspcon_write_infoframe; 2997 dig_port->read_infoframe = lspcon_read_infoframe; 2998 dig_port->set_infoframes = lspcon_set_infoframes; 2999 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3000 } else { 3001 dig_port->write_infoframe = hsw_write_infoframe; 3002 dig_port->read_infoframe = hsw_read_infoframe; 3003 dig_port->set_infoframes = hsw_set_infoframes; 3004 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3005 } 3006 } else if (HAS_PCH_IBX(dev_priv)) { 3007 dig_port->write_infoframe = ibx_write_infoframe; 3008 dig_port->read_infoframe = ibx_read_infoframe; 3009 dig_port->set_infoframes = ibx_set_infoframes; 3010 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3011 } else { 3012 dig_port->write_infoframe = cpt_write_infoframe; 3013 dig_port->read_infoframe = cpt_read_infoframe; 3014 dig_port->set_infoframes = cpt_set_infoframes; 3015 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3016 } 3017} 3018 3019void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3020 struct intel_connector *intel_connector) 3021{ 3022 struct drm_connector *connector = &intel_connector->base; 3023 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3024 struct intel_encoder *intel_encoder = &dig_port->base; 3025 struct drm_device *dev = intel_encoder->base.dev; 3026 struct drm_i915_private *dev_priv = to_i915(dev); 3027 struct i2c_adapter *ddc; 3028 enum port port = intel_encoder->port; 3029 struct cec_connector_info conn_info; 3030 3031 drm_dbg_kms(&dev_priv->drm, 3032 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3033 intel_encoder->base.base.id, intel_encoder->base.name); 3034 3035 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3036 return; 3037 3038 if (drm_WARN(dev, dig_port->max_lanes < 4, 3039 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3040 dig_port->max_lanes, intel_encoder->base.base.id, 3041 intel_encoder->base.name)) 3042 return; 3043 3044 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 3045 if (!intel_hdmi->ddc_bus) 3046 return; 3047 3048 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3049 3050 drm_connector_init_with_ddc(dev, connector, 3051 &intel_hdmi_connector_funcs, 3052 DRM_MODE_CONNECTOR_HDMIA, 3053 ddc); 3054 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3055 3056 if (DISPLAY_VER(dev_priv) < 12) 3057 connector->interlace_allowed = true; 3058 3059 connector->stereo_allowed = true; 3060 3061 if (DISPLAY_VER(dev_priv) >= 10) 3062 connector->ycbcr_420_allowed = true; 3063 3064 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3065 3066 if (HAS_DDI(dev_priv)) 3067 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3068 else 3069 intel_connector->get_hw_state = intel_connector_get_hw_state; 3070 3071 intel_hdmi_add_properties(intel_hdmi, connector); 3072 3073 intel_connector_attach_encoder(intel_connector, intel_encoder); 3074 intel_hdmi->attached_connector = intel_connector; 3075 3076 if (is_hdcp_supported(dev_priv, port)) { 3077 int ret = intel_hdcp_init(intel_connector, dig_port, 3078 &intel_hdmi_hdcp_shim); 3079 if (ret) 3080 drm_dbg_kms(&dev_priv->drm, 3081 "HDCP init failed, skipping.\n"); 3082 } 3083 3084 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3085 * 0xd. Failure to do so will result in spurious interrupts being 3086 * generated on the port when a cable is not attached. 3087 */ 3088 if (IS_G45(dev_priv)) { 3089 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 3090 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 3091 (temp & ~0xf) | 0xd); 3092 } 3093 3094 cec_fill_conn_info_from_drm(&conn_info, connector); 3095 3096 intel_hdmi->cec_notifier = 3097 cec_notifier_conn_register(dev->dev, port_identifier(port), 3098 &conn_info); 3099 if (!intel_hdmi->cec_notifier) 3100 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 3101} 3102 3103/* 3104 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3105 * @vactive: Vactive of a display mode 3106 * 3107 * @return: appropriate dsc slice height for a given mode. 3108 */ 3109int intel_hdmi_dsc_get_slice_height(int vactive) 3110{ 3111 int slice_height; 3112 3113 /* 3114 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3115 * Select smallest slice height >=96, that results in a valid PPS and 3116 * requires minimum padding lines required for final slice. 3117 * 3118 * Assumption : Vactive is even. 3119 */ 3120 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3121 if (vactive % slice_height == 0) 3122 return slice_height; 3123 3124 return 0; 3125} 3126 3127/* 3128 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3129 * and dsc decoder capabilities 3130 * 3131 * @crtc_state: intel crtc_state 3132 * @src_max_slices: maximum slices supported by the DSC encoder 3133 * @src_max_slice_width: maximum slice width supported by DSC encoder 3134 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3135 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3136 * 3137 * @return: num of dsc slices that can be supported by the dsc encoder 3138 * and decoder. 3139 */ 3140int 3141intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3142 int src_max_slices, int src_max_slice_width, 3143 int hdmi_max_slices, int hdmi_throughput) 3144{ 3145/* Pixel rates in KPixels/sec */ 3146#define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3147/* 3148 * Rates at which the source and sink are required to process pixels in each 3149 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3150 */ 3151#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3152#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3153 3154/* Spec limits the slice width to 2720 pixels */ 3155#define MAX_HDMI_SLICE_WIDTH 2720 3156 int kslice_adjust; 3157 int adjusted_clk_khz; 3158 int min_slices; 3159 int target_slices; 3160 int max_throughput; /* max clock freq. in khz per slice */ 3161 int max_slice_width; 3162 int slice_width; 3163 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3164 3165 if (!hdmi_throughput) 3166 return 0; 3167 3168 /* 3169 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3170 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3171 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3172 * dividing adjusted clock value by 10. 3173 */ 3174 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3175 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3176 kslice_adjust = 10; 3177 else 3178 kslice_adjust = 5; 3179 3180 /* 3181 * As per spec, the rate at which the source and the sink process 3182 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3183 * This depends upon the pixel clock rate and output formats 3184 * (kslice adjust). 3185 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3186 * at max 340MHz, otherwise they can be processed at max 400MHz. 3187 */ 3188 3189 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3190 3191 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3192 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3193 else 3194 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3195 3196 /* 3197 * Taking into account the sink's capability for maximum 3198 * clock per slice (in MHz) as read from HF-VSDB. 3199 */ 3200 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3201 3202 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3203 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3204 3205 /* 3206 * Keep on increasing the num of slices/line, starting from min_slices 3207 * per line till we get such a number, for which the slice_width is 3208 * just less than max_slice_width. The slices/line selected should be 3209 * less than or equal to the max horizontal slices that the combination 3210 * of PCON encoder and HDMI decoder can support. 3211 */ 3212 slice_width = max_slice_width; 3213 3214 do { 3215 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3216 target_slices = 1; 3217 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3218 target_slices = 2; 3219 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3220 target_slices = 4; 3221 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3222 target_slices = 8; 3223 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3224 target_slices = 12; 3225 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3226 target_slices = 16; 3227 else 3228 return 0; 3229 3230 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3231 if (slice_width >= max_slice_width) 3232 min_slices = target_slices + 1; 3233 } while (slice_width >= max_slice_width); 3234 3235 return target_slices; 3236} 3237 3238/* 3239 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3240 * source and sink capabilities. 3241 * 3242 * @src_fraction_bpp: fractional bpp supported by the source 3243 * @slice_width: dsc slice width supported by the source and sink 3244 * @num_slices: num of slices supported by the source and sink 3245 * @output_format: video output format 3246 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3247 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3248 * 3249 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3250 */ 3251int 3252intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3253 int output_format, bool hdmi_all_bpp, 3254 int hdmi_max_chunk_bytes) 3255{ 3256 int max_dsc_bpp, min_dsc_bpp; 3257 int target_bytes; 3258 bool bpp_found = false; 3259 int bpp_decrement_x16; 3260 int bpp_target; 3261 int bpp_target_x16; 3262 3263 /* 3264 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3265 * Start with the max bpp and keep on decrementing with 3266 * fractional bpp, if supported by PCON DSC encoder 3267 * 3268 * for each bpp we check if no of bytes can be supported by HDMI sink 3269 */ 3270 3271 /* Assuming: bpc as 8*/ 3272 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3273 min_dsc_bpp = 6; 3274 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3275 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3276 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3277 min_dsc_bpp = 8; 3278 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3279 } else { 3280 /* Assuming 4:2:2 encoding */ 3281 min_dsc_bpp = 7; 3282 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3283 } 3284 3285 /* 3286 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3287 * Section 7.7.34 : Source shall not enable compressed Video 3288 * Transport with bpp_target settings above 12 bpp unless 3289 * DSC_all_bpp is set to 1. 3290 */ 3291 if (!hdmi_all_bpp) 3292 max_dsc_bpp = min(max_dsc_bpp, 12); 3293 3294 /* 3295 * The Sink has a limit of compressed data in bytes for a scanline, 3296 * as described in max_chunk_bytes field in HFVSDB block of edid. 3297 * The no. of bytes depend on the target bits per pixel that the 3298 * source configures. So we start with the max_bpp and calculate 3299 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3300 * till we get the target_chunk_bytes just less than what the sink's 3301 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3302 * 3303 * The decrement is according to the fractional support from PCON DSC 3304 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3305 * 3306 * bpp_target_x16 = bpp_target * 16 3307 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3308 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3309 */ 3310 3311 bpp_target = max_dsc_bpp; 3312 3313 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3314 if (!src_fractional_bpp) 3315 src_fractional_bpp = 1; 3316 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3317 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3318 3319 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3320 int bpp; 3321 3322 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3323 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3324 if (target_bytes <= hdmi_max_chunk_bytes) { 3325 bpp_found = true; 3326 break; 3327 } 3328 bpp_target_x16 -= bpp_decrement_x16; 3329 } 3330 if (bpp_found) 3331 return bpp_target_x16; 3332 3333 return 0; 3334} 3335