Searched refs:inst (Results 1 - 25 of 454) sorted by relevance

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/openbsd-current/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h30 constexpr RxC DecodeCR_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; } argument
31 constexpr RxC DecodeCI_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; } argument
32 constexpr RxC DecodeCR_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; } argument
33 constexpr RxC DecodeCI_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; } argument
34 constexpr RxC DecodeCR_RS2(uint32_t inst) { argument
35 return RxC{(inst
38 DecodeCIW_RD(uint32_t inst) argument
39 DecodeCL_RD(uint32_t inst) argument
40 DecodeCA_RD(uint32_t inst) argument
41 DecodeCB_RD(uint32_t inst) argument
43 DecodeCL_RS1(uint32_t inst) argument
44 DecodeCS_RS1(uint32_t inst) argument
45 DecodeCA_RS1(uint32_t inst) argument
46 DecodeCB_RS1(uint32_t inst) argument
48 DecodeCSS_RS2(uint32_t inst) argument
49 DecodeCS_RS2(uint32_t inst) argument
50 DecodeCA_RS2(uint32_t inst) argument
52 DecodeC_LWSP(uint32_t inst) argument
62 DecodeC_LDSP(uint32_t inst) argument
72 DecodeC_SWSP(uint32_t inst) argument
78 DecodeC_SDSP(uint32_t inst) argument
84 DecodeC_LW(uint32_t inst) argument
91 DecodeC_LD(uint32_t inst) argument
97 DecodeC_SW(uint32_t inst) argument
104 DecodeC_SD(uint32_t inst) argument
110 DecodeC_J(uint32_t inst) argument
124 DecodeC_JR(uint32_t inst) argument
131 DecodeC_JALR(uint32_t inst) argument
138 BOffset(uint32_t inst) argument
146 DecodeC_BNEZ(uint32_t inst) argument
154 DecodeC_BEQZ(uint32_t inst) argument
162 DecodeC_LI(uint32_t inst) argument
170 DecodeC_LUI_ADDI16SP(uint32_t inst) argument
194 DecodeC_ADDI(uint32_t inst) argument
204 DecodeC_ADDIW(uint32_t inst) argument
214 DecodeC_ADDI4SPN(uint32_t inst) argument
228 DecodeC_SLLI(uint32_t inst) argument
236 DecodeC_SRLI(uint32_t inst) argument
244 DecodeC_SRAI(uint32_t inst) argument
252 DecodeC_ANDI(uint32_t inst) argument
260 DecodeC_MV(uint32_t inst) argument
268 DecodeC_ADD(uint32_t inst) argument
273 DecodeC_AND(uint32_t inst) argument
278 DecodeC_OR(uint32_t inst) argument
283 DecodeC_XOR(uint32_t inst) argument
288 DecodeC_SUB(uint32_t inst) argument
293 DecodeC_SUBW(uint32_t inst) argument
298 DecodeC_ADDW(uint32_t inst) argument
302 DecodeC_FLW(uint32_t inst) argument
309 DecodeC_FSW(uint32_t inst) argument
316 DecodeC_FLWSP(uint32_t inst) argument
324 DecodeC_FSWSP(uint32_t inst) argument
330 DecodeC_FLDSP(uint32_t inst) argument
338 DecodeC_FSDSP(uint32_t inst) argument
344 DecodeC_FLD(uint32_t inst) argument
350 DecodeC_FSD(uint32_t inst) argument
[all...]
H A DEmulateInstructionRISCV.cpp70 constexpr uint32_t DecodeJImm(uint32_t inst) {
71 return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 11)) // imm[20]
72 | (inst & 0xff000) // imm[19:12]
73 | ((inst >> 9) & 0x800) // imm[11]
74 | ((inst >> 20) & 0x7fe); // imm[10:1]
77 constexpr uint32_t DecodeIImm(uint32_t inst) { argument
78 return int64_t(int32_t(inst)) >> 20; // imm[11:0]
81 constexpr uint32_t DecodeBImm(uint32_t inst) { argument
82 return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 19)) // imm[12]
83 | ((inst
88 DecodeSImm(uint32_t inst) argument
93 DecodeUImm(uint32_t inst) argument
[all...]
/openbsd-current/gnu/llvm/lldb/source/Plugins/Instruction/LoongArch/
H A DEmulateInstructionLoongArch.h63 bool TestExecute(uint32_t inst);
74 Opcode *GetOpcodeForInstruction(uint32_t inst);
76 bool EmulateBEQZ(uint32_t inst);
77 bool EmulateBNEZ(uint32_t inst);
78 bool EmulateBCEQZ(uint32_t inst);
79 bool EmulateBCNEZ(uint32_t inst);
80 bool EmulateJIRL(uint32_t inst);
81 bool EmulateB(uint32_t inst);
82 bool EmulateBL(uint32_t inst);
83 bool EmulateBEQ(uint32_t inst);
[all...]
H A DEmulateInstructionLoongArch.cpp36 EmulateInstructionLoongArch::GetOpcodeForInstruction(uint32_t inst) { argument
70 if ((g_opcodes[i].mask & inst) == g_opcodes[i].value)
75 bool EmulateInstructionLoongArch::TestExecute(uint32_t inst) { argument
76 Opcode *opcode_data = GetOpcodeForInstruction(inst);
80 if (!(this->*opcode_data->callback)(inst))
87 uint32_t inst = m_opcode.GetOpcode32(); local
91 Opcode *opcode_data = GetOpcodeForInstruction(inst);
103 if (!(this->*opcode_data->callback)(inst))
128 uint32_t inst = (uint32_t)ReadMemoryUnsigned(ctx, m_addr, 4, 0, &success); local
129 m_opcode.SetOpcode32(inst, GetByteOrde
216 EmulateBEQZ(uint32_t inst) argument
220 EmulateBNEZ(uint32_t inst) argument
224 EmulateBCEQZ(uint32_t inst) argument
228 EmulateBCNEZ(uint32_t inst) argument
232 EmulateJIRL(uint32_t inst) argument
236 EmulateB(uint32_t inst) argument
240 EmulateBL(uint32_t inst) argument
244 EmulateBEQ(uint32_t inst) argument
248 EmulateBNE(uint32_t inst) argument
252 EmulateBLT(uint32_t inst) argument
256 EmulateBGE(uint32_t inst) argument
260 EmulateBLTU(uint32_t inst) argument
264 EmulateBGEU(uint32_t inst) argument
268 EmulateNonJMP(uint32_t inst) argument
273 EmulateBEQZ64(uint32_t inst) argument
293 EmulateBNEZ64(uint32_t inst) argument
313 EmulateBCEQZ64(uint32_t inst) argument
335 EmulateBCNEZ64(uint32_t inst) argument
357 EmulateJIRL64(uint32_t inst) argument
376 EmulateB64(uint32_t inst) argument
389 EmulateBL64(uint32_t inst) argument
405 EmulateBEQ64(uint32_t inst) argument
428 EmulateBNE64(uint32_t inst) argument
451 EmulateBLT64(uint32_t inst) argument
476 EmulateBGE64(uint32_t inst) argument
501 EmulateBLTU64(uint32_t inst) argument
524 EmulateBGEU64(uint32_t inst) argument
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.h34 #define MPC_REG_LIST_DCN3_2(inst) \
35 MPC_REG_LIST_DCN3_0(inst),\
36 SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
37 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
38 SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
39 SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
40 SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
41 SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
42 SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
43 SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
[all...]
H A Ddcn32_resource.h691 #define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst) \
693 SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \
694 SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \
695 SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \
696 SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \
697 SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \
698 SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \
699 SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \
700 SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \
701 SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \
[all...]
H A Ddcn32_mmhubbub.h32 #define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \
33 SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
34 SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
35 SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
36 SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
37 SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
38 SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
39 SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
40 SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
41 SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all...]
H A Ddcn32_dpp.h33 uint32_t inst,
/openbsd-current/sys/arch/m88k/m88k/
H A Ddb_sstep.c91 branch_taken(u_int inst, vaddr_t pc, db_regs_t *regs) argument
100 switch (inst >> (32 - 5)) {
104 inst = (inst & 0x03ffffff) << 2;
106 if (inst & 0x08000000)
107 inst |= 0xf0000000;
108 return (pc + inst);
114 inst = (inst & 0x0000ffff) << 2;
116 if (inst
146 u_int inst; local
[all...]
H A Ddb_disasm.c323 oimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
325 int32_t Linst = inst & 0xffff;
326 u_int32_t H6inst = inst >> 26;
327 u_int32_t rs1 = (inst >> 16) & 0x1f;
328 u_int32_t rd = (inst >> 21) & 0x1f;
348 ctrlregs(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
350 u_int32_t dir = (inst >> 14) & 0x03;
351 u_int32_t sfu = (inst >> 11) & 0x07;
352 u_int32_t creg = (inst >> 5) & 0x3f;
353 u_int32_t rd = (inst >> 2
382 sindou(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
467 jump(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
483 instset(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
515 obranch(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
532 brcond(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
563 otrap(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
586 obit(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
603 bitman(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
616 immem(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
671 nimmem(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
745 lognim(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
762 onimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
795 pinst(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr) argument
1045 m88k_print_instruction(int cpu, u_int iadr, u_int32_t inst) argument
[all...]
/openbsd-current/gnu/llvm/lldb/examples/python/
H A Dgdb_disassemble.py14 for inst in instructions:
15 inst_addr = inst.addr.load_addr
17 comment = inst.comment
19 print("<%s + %-4u> 0x%x %8s %s ; %s" % (name, inst_offset, inst_addr, inst.mnemonic, inst.operands, comment))
21 print("<%s + %-4u> 0x%x %8s %s" % (name, inst_offset, inst_addr, inst.mnemonic, inst.operands))
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.h32 #define OPTC_COMMON_REG_LIST_DCN3_14(inst) \
33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
[all...]
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dsoc15_common.h28 #define GET_INST(ip, inst) \
30 adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst)
36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \
[all...]
H A Damdgpu_amdkfd_gfx_v9.h26 uint32_t sh_mem_bases, uint32_t inst);
28 unsigned int vmid, uint32_t inst);
30 uint32_t inst);
34 struct mm_struct *mm, uint32_t inst);
37 uint32_t doorbell_off, uint32_t inst);
40 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
43 uint32_t queue_id, uint32_t inst);
47 uint32_t queue_id, uint32_t inst);
50 uint32_t sq_cmd, uint32_t inst);
56 int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst);
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.h31 #define TG_COMMON_REG_LIST_DCN201(inst) \
32 TG_COMMON_REG_LIST_DCN(inst),\
33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
40 SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/gas/config/
H A Dtc-arm.c293 static struct arm_it inst; variable in typeref:struct:arm_it
713 inst.error = _("immediate expression requires a # prefix");
738 if (inst.error == NULL)
739 inst.error = _("bad expression");
750 inst.error = _("bad segment");
766 inst.error = _("invalid constant");
1016 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
1026 inst.error = _("bad range in register list");
1057 inst.error = _("missing `}'");
1073 inst
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.h31 #define V_TOTAL_REGS_DCN30_SRI(inst)
33 #define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \
34 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
35 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
36 SRI(OTG_VREADY_PARAM, OTG, inst),\
37 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
41 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
[all...]
H A Ddcn30_mmhubbub.h34 #define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \
35 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
36 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
37 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
38 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
39 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
40 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
42 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.h31 #define OPTC_COMMON_REG_LIST_DCN3_1(inst) \
32 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
33 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
34 SRI(OTG_VREADY_PARAM, OTG, inst),\
35 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
36 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
40 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.h33 #define MPC_REG_LIST_DCN2_0(inst)\
34 MPC_COMMON_REG_LIST_DCN1_0(inst),\
35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
[all...]
/openbsd-current/gnu/usr.bin/binutils/opcodes/
H A Dmcore-dis.c95 unsigned short inst; local
110 inst = (ibytes[0] << 8) | ibytes[1];
112 inst = (ibytes[1] << 8) | ibytes[0];
118 if (op->inst == (inst & imsk[op->opclass]))
122 fprintf (stream, ".short 0x%04x", inst);
125 const char *name = grname[inst & 0x0F];
135 fprintf (stream, "\t%d", inst & 0x3);
145 fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
154 fprintf (stream, "\t%s, %s", name, grname[(inst >>
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/
H A Dmcore-dis.c95 unsigned short inst; local
110 inst = (ibytes[0] << 8) | ibytes[1];
112 inst = (ibytes[1] << 8) | ibytes[0];
118 if (op->inst == (inst & imsk[op->opclass]))
122 fprintf (stream, ".short 0x%04x", inst);
125 const char *name = grname[inst & 0x0F];
135 fprintf (stream, "\t%d", inst & 0x3);
145 fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
154 fprintf (stream, "\t%s, %s", name, grname[(inst >>
[all...]
/openbsd-current/gnu/llvm/lldb/include/lldb/Core/
H A DOpcode.h43 Opcode(uint8_t inst, lldb::ByteOrder order) argument
45 m_data.inst8 = inst;
48 Opcode(uint16_t inst, lldb::ByteOrder order) argument
50 m_data.inst16 = inst;
53 Opcode(uint32_t inst, lldb::ByteOrder order) argument
55 m_data.inst32 = inst;
58 Opcode(uint64_t inst, lldb::ByteOrder order) argument
60 m_data.inst64 = inst;
153 void SetOpcode8(uint8_t inst, lldb::ByteOrder order) { argument
155 m_data.inst8 = inst;
159 SetOpcode16(uint16_t inst, lldb::ByteOrder order) argument
165 SetOpcode16_2(uint32_t inst, lldb::ByteOrder order) argument
171 SetOpcode32(uint32_t inst, lldb::ByteOrder order) argument
177 SetOpcode64(uint64_t inst, lldb::ByteOrder order) argument
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h51 #define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
52 SRI(WB_ENABLE, CNV, inst),\
53 SRI(WB_EC_CONFIG, CNV, inst),\
54 SRI(CNV_MODE, CNV, inst),\
55 SRI(WB_SOFT_RESET, CNV, inst),\
56 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
57 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
58 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
59 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
60 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
[all...]
/openbsd-current/sys/arch/alpha/alpha/
H A Dfp_complete.c146 alpha_instruction inst; local
149 inst.bits = bits;
152 alpha_shadow.uop |= 1UL << inst.generic_format.opcode;
237 alpha_instruction inst; local
239 inst.bits = inst_bits;
247 switch(inst.float_format.function) {
250 sts(inst.float_detail.fb, &sfb, p);
252 ldt(inst.float_detail.fc, &tfc, p);
255 if(inst.float_detail.src == 2) {
256 stt(inst
274 alpha_instruction inst; local
288 alpha_instruction inst; local
325 alpha_instruction inst; local
504 alpha_instruction inst; local
571 alpha_instruction inst; local
619 alpha_instruction inst; local
[all...]

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