dc/dcn20/dcn20_mpc.h

33 #define MPC_REG_LIST_DCN2_0(inst)\
34 	MPC_COMMON_REG_LIST_DCN1_0(inst),\
35 	SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 	SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 	SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 	SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 	SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 	SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 	SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 	SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
43 	SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
44 	SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
45 	SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
46 	SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
47 	SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
48 	SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
49 	SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
50 	SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
51 	SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
52 	SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
53 	SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
54 	SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
55 	SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
56 	SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
57 	SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
58 	SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
59 	SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
60 	SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
61 	SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
62 	SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
63 	SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
64 	SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
65 	SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
66 	SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
67 	SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
68 	SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
69 	SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
70 	SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
72 #define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
73 	MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
74 	SRII(CSC_MODE, MPC_OUT, inst),\
75 	SRII(CSC_C11_C12_A, MPC_OUT, inst),\
76 	SRII(CSC_C33_C34_A, MPC_OUT, inst),\
77 	SRII(CSC_C11_C12_B, MPC_OUT, inst),\
78 	SRII(CSC_C33_C34_B, MPC_OUT, inst),\
79 	SRII(DENORM_CONTROL, MPC_OUT, inst),\
80 	SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
81 	SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)