1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef __DC_OPTC_DCN30_H__ 27#define __DC_OPTC_DCN30_H__ 28 29#include "dcn20/dcn20_optc.h" 30 31#define V_TOTAL_REGS_DCN30_SRI(inst) 32 33#define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \ 34 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 35 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 36 SRI(OTG_VREADY_PARAM, OTG, inst),\ 37 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 38 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 39 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ 40 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 41 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\ 42 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 43 SRI(OTG_H_TOTAL, OTG, inst),\ 44 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 45 SRI(OTG_H_SYNC_A, OTG, inst),\ 46 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ 47 SRI(OTG_H_TIMING_CNTL, OTG, inst),\ 48 SRI(OTG_V_TOTAL, OTG, inst),\ 49 SRI(OTG_V_BLANK_START_END, OTG, inst),\ 50 SRI(OTG_V_SYNC_A, OTG, inst),\ 51 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ 52 SRI(OTG_CONTROL, OTG, inst),\ 53 SRI(OTG_STEREO_CONTROL, OTG, inst),\ 54 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ 55 SRI(OTG_STEREO_STATUS, OTG, inst),\ 56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\ 57 SRI(OTG_V_TOTAL_MIN, OTG, inst),\ 58 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ 59 V_TOTAL_REGS_DCN30_SRI(inst)\ 60 SRI(OTG_TRIGA_CNTL, OTG, inst),\ 61 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ 62 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ 63 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ 64 SRI(OTG_STATUS, OTG, inst),\ 65 SRI(OTG_STATUS_POSITION, OTG, inst),\ 66 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ 67 SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\ 68 SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\ 69 SRI(OTG_M_CONST_DTO0, OTG, inst),\ 70 SRI(OTG_M_CONST_DTO1, OTG, inst),\ 71 SRI(OTG_CLOCK_CONTROL, OTG, inst),\ 72 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ 73 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ 74 SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ 75 SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ 76 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ 77 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ 78 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ 79 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ 80 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ 81 SRI(CONTROL, VTG, inst),\ 82 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ 83 SRI(OTG_GSL_CONTROL, OTG, inst),\ 84 SRI(OTG_CRC_CNTL, OTG, inst),\ 85 SRI(OTG_CRC_CNTL2, OTG, inst),\ 86 SRI(OTG_CRC0_DATA_RG, OTG, inst),\ 87 SRI(OTG_CRC0_DATA_B, OTG, inst),\ 88 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ 89 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ 90 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ 91 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ 92 SR(GSL_SOURCE_SELECT),\ 93 SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\ 94 SRI(OTG_DRR_CONTROL, OTG, inst) 95 96 97#define OPTC_COMMON_REG_LIST_DCN3_0(inst) \ 98 OPTC_COMMON_REG_LIST_DCN3_BASE(inst),\ 99 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ 100 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 101 SRI(OTG_GSL_WINDOW_X, OTG, inst),\ 102 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\ 103 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\ 104 SRI(OTG_DSC_START_POSITION, OTG, inst),\ 105 SRI(OTG_CRC_CNTL2, OTG, inst),\ 106 SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\ 107 SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\ 108 SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\ 109 SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ 110 SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ 111 SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ 112 SR(DWB_SOURCE_SELECT) 113 114#define DCN30_VTOTAL_REGS_SF(mask_sh) 115 116#define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh)\ 117 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 118 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 119 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 120 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 121 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 122 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 123 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\ 124 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\ 125 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ 126 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\ 127 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\ 128 SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 129 SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\ 130 SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\ 131 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 132 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 133 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 134 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 135 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 136 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 137 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 138 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 139 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 140 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 141 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 142 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 143 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 144 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\ 145 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 146 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 147 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 148 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 149 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ 150 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 151 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 152 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 153 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 154 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 155 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 156 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 157 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 158 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 159 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 160 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 161 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 162 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 163 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 164 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ 165 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 166 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ 167 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ 168 DCN30_VTOTAL_REGS_SF(mask_sh)\ 169 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 170 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 171 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 172 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 173 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 174 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 175 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 176 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ 177 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ 178 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ 179 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ 180 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 181 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 182 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 183 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 184 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 185 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 186 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 187 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 188 SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_BLUE_CB, mask_sh),\ 189 SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_GREEN_Y, mask_sh),\ 190 SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_RED_CR, mask_sh),\ 191 SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, mask_sh),\ 192 SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, mask_sh),\ 193 SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_RED_CR_EXT, mask_sh),\ 194 SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\ 195 SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\ 196 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 197 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 198 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 199 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 200 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 201 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 202 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 203 SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ 204 SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ 205 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 206 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 207 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 208 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 209 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 210 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 211 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 212 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 213 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 214 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 215 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 216 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 217 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 218 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 219 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 220 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 221 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 222 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 223 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 224 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 225 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 226 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 227 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\ 228 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ 229 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ 230 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ 231 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 232 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 233 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 234 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 235 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 236 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 237 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 238 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 239 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 240 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 241 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ 242 SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ 243 SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ 244 SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ 245 SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ 246 SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ 247 SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) 248 249#define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh)\ 250 OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\ 251 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ 252 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ 253 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ 254 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ 255 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ 256 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 257 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 258 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 259 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ 260 SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ 261 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ 262 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ 263 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\ 264 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ 265 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ 266 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ 267 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ 268 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ 269 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ 270 SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ 271 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ 272 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ 273 SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ 274 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ 275 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ 276 SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ 277 SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ 278 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ 279 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ 280 SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ 281 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ 282 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ 283 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 284 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh) 285 286#define OPTC_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ 287 OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\ 288 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ 289 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ 290 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ 291 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ 292 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ 293 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 294 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 295 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 296 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ 297 SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ 298 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ 299 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ 300 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\ 301 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ 302 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ 303 SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ 304 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ 305 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ 306 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\ 307 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\ 308 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ 309 SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ 310 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ 311 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ 312 SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ 313 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ 314 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ 315 SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ 316 SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ 317 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ 318 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ 319 SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ 320 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ 321 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ 322 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh) 323 324void dcn30_timing_generator_init(struct optc *optc1); 325 326void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest); 327 328void optc3_lock(struct timing_generator *optc); 329 330void optc3_lock_doublebuffer_enable(struct timing_generator *optc); 331 332void optc3_lock_doublebuffer_disable(struct timing_generator *optc); 333 334void optc3_set_drr_trigger_window(struct timing_generator *optc, 335 uint32_t window_start, uint32_t window_end); 336 337void optc3_triplebuffer_lock(struct timing_generator *optc); 338 339void optc3_program_blank_color(struct timing_generator *optc, 340 const struct tg_color *blank_color); 341 342void optc3_set_vtotal_change_limit(struct timing_generator *optc, 343 uint32_t limit); 344 345void optc3_set_dsc_config(struct timing_generator *optc, 346 enum optc_dsc_mode dsc_mode, 347 uint32_t dsc_bytes_per_pixel, 348 uint32_t dsc_slice_width); 349 350void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); 351 352void optc3_set_odm_bypass(struct timing_generator *optc, 353 const struct dc_crtc_timing *dc_crtc_timing); 354void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 355 struct dc_crtc_timing *timing); 356void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc); 357void optc3_tg_init(struct timing_generator *optc); 358void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); 359#endif /* __DC_OPTC_DCN30_H__ */ 360