Searched refs:WR (Results 1 - 15 of 15) sorted by relevance

/openbsd-current/usr.bin/tail/
H A Dread.c92 WR(t + 1, len);
100 WR(t + 1, len);
104 WR(sp, tlen);
109 WR(t + 1, len);
111 WR(sp, tlen);
115 WR(p, len);
117 WR(sp, len);
209 WR(lines[cnt - 1].l, lines[cnt - 1].len);
212 WR(lines[cnt - 1].l, lines[cnt - 1].len);
216 WR(line
[all...]
H A Dextern.h35 #define WR(p, size) \ macro
H A Dreverse.c247 WR(p + 1, llen);
253 WR(tr->l, tr->len);
265 WR(tl->l, tl->len);
269 WR(tl->l, tl->len);
/openbsd-current/gnu/llvm/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp126 WriteRef &WR = RegisterMappings[RegID].first; local
127 if (WR.getWriteState() == &WS)
128 WR.notifyExecuted(CurrentCycle);
364 WriteRef &WR = RegisterMappings[RegID].first; local
365 if (WR.getWriteState() == &WS)
366 WR.commit();
497 unsigned RegisterFile::getElapsedCyclesFromWriteBack(const WriteRef &WR) const {
498 assert(WR.hasKnownWriteBackCycle() && "Write hasn't been committed yet!");
499 return CurrentCycle - WR.getWriteBackCycle();
519 const WriteRef &WR
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/openbsd-current/gnu/llvm/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h295 unsigned getElapsedCyclesFromWriteBack(const WriteRef &WR) const;
/openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/
H A Dmt-opc.c689 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (XMODE), ',', '#', OP (MASK1), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
701 { { MNEM, ' ', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
707 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
713 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
719 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
/openbsd-current/gnu/llvm/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp891 for (Record *WR : ProcModel.WriteResDefs) {
892 if (!WR->isSubClassOf("WriteRes"))
894 if (AliasDef == WR->getValueAsDef("WriteType")
895 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
897 PrintFatalError(WR->getLoc(), "Resources are defined for both "
901 ResDef = WR;
H A DCodeGenSchedule.cpp1907 for (Record *WR : WRDefs) {
1908 Record *ModelDef = WR->getValueAsDef("SchedModel");
1909 addWriteRes(WR, getProcModel(ModelDef).Index);
/openbsd-current/gnu/llvm/llvm/lib/Object/
H A DWindowsResource.cpp327 Error WindowsResourceParser::parse(WindowsResource *WR, argument
329 auto EntryOrErr = WR->getHeadEntry();
347 InputFilenames.push_back(std::string(WR->getFileName()));
356 Entry, InputFilenames[Node->Origin], WR->getFileName()));
/openbsd-current/gnu/llvm/llvm/include/llvm/Object/
H A DWindowsResource.h157 Error parse(WindowsResource *WR, std::vector<std::string> &Duplicates);
/openbsd-current/gnu/llvm/clang/lib/StaticAnalyzer/Core/
H A DSValBuilder.cpp1071 const auto WR = RTy.getBitWidth(); local
1075 if (((WT > WR) && (UR || !UT)) || ((WT == WR) && (UT == UR)))
/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp794 uint16_t WR = W0;
796 assert(WR == 64 && WP == 8);
798 RegisterCell RC(WR);
/openbsd-current/gnu/llvm/llvm/lib/Analysis/
H A DMemorySSA.cpp865 UpwardsWalkResult WR = walkToPhiOrClobber(Paths[Paused]); local
866 if (WR.IsKnownClobber)
867 Clobbers.push_back({WR.Result, Paused});
870 DefChainEnd = WR.Result;
/openbsd-current/gnu/usr.bin/perl/utils/
H A Dh2ph.PL521 s/^\s*\((\w),/("$1",/ if $id =~ /^_IO[WR]*$/i; # cheat
/openbsd-current/gnu/usr.bin/binutils-2.17/gas/config/
H A Dtc-arm.c8730 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8781 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),

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