Searched refs:IH_CNTL (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_si_ih.c40 u32 ih_cntl = RREG32(IH_CNTL);
45 WREG32(IH_CNTL, ih_cntl);
53 u32 ih_cntl = RREG32(IH_CNTL);
58 WREG32(IH_CNTL, ih_cntl);
96 WREG32(IH_CNTL, ih_cntl);
H A Damdgpu_iceland_ih.c70 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
90 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
152 /* Default settings for IH_CNTL (disabled at first) */
154 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
157 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
H A Damdgpu_cz_ih.c70 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
90 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
152 /* Default settings for IH_CNTL (disabled at first) */
154 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
157 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
H A Dsid.h672 #define IH_CNTL 0xF86 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_r600.c3628 u32 ih_cntl = RREG32(IH_CNTL);
3633 WREG32(IH_CNTL, ih_cntl);
3641 u32 ih_cntl = RREG32(IH_CNTL);
3646 WREG32(IH_CNTL, ih_cntl);
3763 /* Default settings for IH_CNTL (disabled at first) */
3768 WREG32(IH_CNTL, ih_cntl);
H A Dradeon_si.c5929 u32 ih_cntl = RREG32(IH_CNTL);
5934 WREG32(IH_CNTL, ih_cntl);
5942 u32 ih_cntl = RREG32(IH_CNTL);
5947 WREG32(IH_CNTL, ih_cntl);
6038 /* Default settings for IH_CNTL (disabled at first) */
6043 WREG32(IH_CNTL, ih_cntl);
H A Dcikd.h818 #define IH_CNTL 0x3e18 macro
H A Dsid.h668 #define IH_CNTL 0x3e18 macro
H A Dradeon_cik.c6842 u32 ih_cntl = RREG32(IH_CNTL);
6847 WREG32(IH_CNTL, ih_cntl);
6862 u32 ih_cntl = RREG32(IH_CNTL);
6867 WREG32(IH_CNTL, ih_cntl);
7016 /* Default settings for IH_CNTL (disabled at first) */
7021 WREG32(IH_CNTL, ih_cntl);
H A Devergreend.h1237 #define IH_CNTL 0x3e18 macro
H A Dr600d.h676 #define IH_CNTL 0x3e18 macro

Completed in 415 milliseconds