1/* $NetBSD: amdgpu_cz_ih.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3/* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: amdgpu_cz_ih.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $"); 28 29#include <linux/pci.h> 30 31#include "amdgpu.h" 32#include "amdgpu_ih.h" 33#include "vid.h" 34 35#include "oss/oss_3_0_1_d.h" 36#include "oss/oss_3_0_1_sh_mask.h" 37 38#include "bif/bif_5_1_d.h" 39#include "bif/bif_5_1_sh_mask.h" 40 41/* 42 * Interrupts 43 * Starting with r6xx, interrupts are handled via a ring buffer. 44 * Ring buffers are areas of GPU accessible memory that the GPU 45 * writes interrupt vectors into and the host reads vectors out of. 46 * There is a rptr (read pointer) that determines where the 47 * host is currently reading, and a wptr (write pointer) 48 * which determines where the GPU has written. When the 49 * pointers are equal, the ring is idle. When the GPU 50 * writes vectors to the ring buffer, it increments the 51 * wptr. When there is an interrupt, the host then starts 52 * fetching commands and processing them until the pointers are 53 * equal again at which point it updates the rptr. 54 */ 55 56static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev); 57 58/** 59 * cz_ih_enable_interrupts - Enable the interrupt ring buffer 60 * 61 * @adev: amdgpu_device pointer 62 * 63 * Enable the interrupt ring buffer (VI). 64 */ 65static void cz_ih_enable_interrupts(struct amdgpu_device *adev) 66{ 67 u32 ih_cntl = RREG32(mmIH_CNTL); 68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 69 70 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); 71 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 72 WREG32(mmIH_CNTL, ih_cntl); 73 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 74 adev->irq.ih.enabled = true; 75} 76 77/** 78 * cz_ih_disable_interrupts - Disable the interrupt ring buffer 79 * 80 * @adev: amdgpu_device pointer 81 * 82 * Disable the interrupt ring buffer (VI). 83 */ 84static void cz_ih_disable_interrupts(struct amdgpu_device *adev) 85{ 86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 87 u32 ih_cntl = RREG32(mmIH_CNTL); 88 89 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 90 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); 91 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 92 WREG32(mmIH_CNTL, ih_cntl); 93 /* set rptr, wptr to 0 */ 94 WREG32(mmIH_RB_RPTR, 0); 95 WREG32(mmIH_RB_WPTR, 0); 96 adev->irq.ih.enabled = false; 97 adev->irq.ih.rptr = 0; 98} 99 100/** 101 * cz_ih_irq_init - init and enable the interrupt ring 102 * 103 * @adev: amdgpu_device pointer 104 * 105 * Allocate a ring buffer for the interrupt controller, 106 * enable the RLC, disable interrupts, enable the IH 107 * ring buffer and enable it (VI). 108 * Called at device load and reume. 109 * Returns 0 for success, errors for failure. 110 */ 111static int cz_ih_irq_init(struct amdgpu_device *adev) 112{ 113 struct amdgpu_ih_ring *ih = &adev->irq.ih; 114 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 115 int rb_bufsz; 116 117 /* disable irqs */ 118 cz_ih_disable_interrupts(adev); 119 120 /* setup interrupt control */ 121 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 122 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 123 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 124 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 125 */ 126 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 127 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 128 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 129 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 130 131 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 132 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 133 134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 135 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 136 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 138 139 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 140 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 141 142 /* set the writeback address whether it's enabled or not */ 143 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 144 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 145 146 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 147 148 /* set rptr, wptr to 0 */ 149 WREG32(mmIH_RB_RPTR, 0); 150 WREG32(mmIH_RB_WPTR, 0); 151 152 /* Default settings for IH_CNTL (disabled at first) */ 153 ih_cntl = RREG32(mmIH_CNTL); 154 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); 155 156 if (adev->irq.msi_enabled) 157 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); 158 WREG32(mmIH_CNTL, ih_cntl); 159 160 pci_set_master(adev->pdev); 161 162 /* enable interrupts */ 163 cz_ih_enable_interrupts(adev); 164 165 return 0; 166} 167 168/** 169 * cz_ih_irq_disable - disable interrupts 170 * 171 * @adev: amdgpu_device pointer 172 * 173 * Disable interrupts on the hw (VI). 174 */ 175static void cz_ih_irq_disable(struct amdgpu_device *adev) 176{ 177 cz_ih_disable_interrupts(adev); 178 179 /* Wait and acknowledge irq */ 180 mdelay(1); 181} 182 183/** 184 * cz_ih_get_wptr - get the IH ring buffer wptr 185 * 186 * @adev: amdgpu_device pointer 187 * 188 * Get the IH ring buffer wptr from either the register 189 * or the writeback memory buffer (VI). Also check for 190 * ring buffer overflow and deal with it. 191 * Used by cz_irq_process(VI). 192 * Returns the value of the wptr. 193 */ 194static u32 cz_ih_get_wptr(struct amdgpu_device *adev, 195 struct amdgpu_ih_ring *ih) 196{ 197 u32 wptr, tmp; 198 199 wptr = le32_to_cpu(*ih->wptr_cpu); 200 201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 202 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 203 /* When a ring buffer overflow happen start parsing interrupt 204 * from the last not overwritten vector (wptr + 16). Hopefully 205 * this should allow us to catchup. 206 */ 207 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 208 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 209 ih->rptr = (wptr + 16) & ih->ptr_mask; 210 tmp = RREG32(mmIH_RB_CNTL); 211 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 212 WREG32(mmIH_RB_CNTL, tmp); 213 } 214 return (wptr & ih->ptr_mask); 215} 216 217/** 218 * cz_ih_decode_iv - decode an interrupt vector 219 * 220 * @adev: amdgpu_device pointer 221 * 222 * Decodes the interrupt vector at the current rptr 223 * position and also advance the position. 224 */ 225static void cz_ih_decode_iv(struct amdgpu_device *adev, 226 struct amdgpu_ih_ring *ih, 227 struct amdgpu_iv_entry *entry) 228{ 229 /* wptr/rptr are in bytes! */ 230 u32 ring_index = ih->rptr >> 2; 231 uint32_t dw[4]; 232 233 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 234 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 235 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 236 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 237 238 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 239 entry->src_id = dw[0] & 0xff; 240 entry->src_data[0] = dw[1] & 0xfffffff; 241 entry->ring_id = dw[2] & 0xff; 242 entry->vmid = (dw[2] >> 8) & 0xff; 243 entry->pasid = (dw[2] >> 16) & 0xffff; 244 245 /* wptr/rptr are in bytes! */ 246 ih->rptr += 16; 247} 248 249/** 250 * cz_ih_set_rptr - set the IH ring buffer rptr 251 * 252 * @adev: amdgpu_device pointer 253 * 254 * Set the IH ring buffer rptr. 255 */ 256static void cz_ih_set_rptr(struct amdgpu_device *adev, 257 struct amdgpu_ih_ring *ih) 258{ 259 WREG32(mmIH_RB_RPTR, ih->rptr); 260} 261 262static int cz_ih_early_init(void *handle) 263{ 264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 265 int ret; 266 267 ret = amdgpu_irq_add_domain(adev); 268 if (ret) 269 return ret; 270 271 cz_ih_set_interrupt_funcs(adev); 272 273 return 0; 274} 275 276static int cz_ih_sw_init(void *handle) 277{ 278 int r; 279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 280 281 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 282 if (r) 283 return r; 284 285 r = amdgpu_irq_init(adev); 286 287 return r; 288} 289 290static int cz_ih_sw_fini(void *handle) 291{ 292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 293 294 amdgpu_irq_fini(adev); 295 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 296 amdgpu_irq_remove_domain(adev); 297 298 return 0; 299} 300 301static int cz_ih_hw_init(void *handle) 302{ 303 int r; 304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 305 306 r = cz_ih_irq_init(adev); 307 if (r) 308 return r; 309 310 return 0; 311} 312 313static int cz_ih_hw_fini(void *handle) 314{ 315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 316 317 cz_ih_irq_disable(adev); 318 319 return 0; 320} 321 322static int cz_ih_suspend(void *handle) 323{ 324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 325 326 return cz_ih_hw_fini(adev); 327} 328 329static int cz_ih_resume(void *handle) 330{ 331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 332 333 return cz_ih_hw_init(adev); 334} 335 336static bool cz_ih_is_idle(void *handle) 337{ 338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 339 u32 tmp = RREG32(mmSRBM_STATUS); 340 341 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 342 return false; 343 344 return true; 345} 346 347static int cz_ih_wait_for_idle(void *handle) 348{ 349 unsigned i; 350 u32 tmp; 351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 352 353 for (i = 0; i < adev->usec_timeout; i++) { 354 /* read MC_STATUS */ 355 tmp = RREG32(mmSRBM_STATUS); 356 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 357 return 0; 358 udelay(1); 359 } 360 return -ETIMEDOUT; 361} 362 363static int cz_ih_soft_reset(void *handle) 364{ 365 u32 srbm_soft_reset = 0; 366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 367 u32 tmp = RREG32(mmSRBM_STATUS); 368 369 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 370 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 371 SOFT_RESET_IH, 1); 372 373 if (srbm_soft_reset) { 374 tmp = RREG32(mmSRBM_SOFT_RESET); 375 tmp |= srbm_soft_reset; 376 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 377 WREG32(mmSRBM_SOFT_RESET, tmp); 378 tmp = RREG32(mmSRBM_SOFT_RESET); 379 380 udelay(50); 381 382 tmp &= ~srbm_soft_reset; 383 WREG32(mmSRBM_SOFT_RESET, tmp); 384 tmp = RREG32(mmSRBM_SOFT_RESET); 385 386 /* Wait a little for things to settle down */ 387 udelay(50); 388 } 389 390 return 0; 391} 392 393static int cz_ih_set_clockgating_state(void *handle, 394 enum amd_clockgating_state state) 395{ 396 // TODO 397 return 0; 398} 399 400static int cz_ih_set_powergating_state(void *handle, 401 enum amd_powergating_state state) 402{ 403 // TODO 404 return 0; 405} 406 407static const struct amd_ip_funcs cz_ih_ip_funcs = { 408 .name = "cz_ih", 409 .early_init = cz_ih_early_init, 410 .late_init = NULL, 411 .sw_init = cz_ih_sw_init, 412 .sw_fini = cz_ih_sw_fini, 413 .hw_init = cz_ih_hw_init, 414 .hw_fini = cz_ih_hw_fini, 415 .suspend = cz_ih_suspend, 416 .resume = cz_ih_resume, 417 .is_idle = cz_ih_is_idle, 418 .wait_for_idle = cz_ih_wait_for_idle, 419 .soft_reset = cz_ih_soft_reset, 420 .set_clockgating_state = cz_ih_set_clockgating_state, 421 .set_powergating_state = cz_ih_set_powergating_state, 422}; 423 424static const struct amdgpu_ih_funcs cz_ih_funcs = { 425 .get_wptr = cz_ih_get_wptr, 426 .decode_iv = cz_ih_decode_iv, 427 .set_rptr = cz_ih_set_rptr 428}; 429 430static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev) 431{ 432 adev->irq.ih_funcs = &cz_ih_funcs; 433} 434 435const struct amdgpu_ip_block_version cz_ih_ip_block = 436{ 437 .type = AMD_IP_BLOCK_TYPE_IH, 438 .major = 3, 439 .minor = 0, 440 .rev = 0, 441 .funcs = &cz_ih_ip_funcs, 442}; 443