/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/ |
H A D | mac89x0.c | 163 writereg(struct net_device *dev, int portno, int value) function 315 writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ); 323 writereg(dev, PP_CS8900_ISAINT, 0); 325 writereg(dev, PP_CS8920_ISAINT, 0); 329 writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); 332 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); 336 writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); 340 writereg(dev, PP_RxCFG, lp->curr_rx_cfg); 342 writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | 345 writereg(de [all...] |
H A D | declance.c | 297 static inline void writereg(volatile unsigned short *regptr, short value) function 314 writereg(&ll->rap, LE_CSR1); 315 writereg(&ll->rdp, (leptr & 0xFFFF)); 316 writereg(&ll->rap, LE_CSR2); 317 writereg(&ll->rdp, leptr >> 16); 318 writereg(&ll->rap, LE_CSR3); 319 writereg(&ll->rdp, lp->busmaster_regval); 322 writereg(&ll->rap, LE_CSR0); 524 writereg(&ll->rap, LE_CSR0); 525 writereg( [all...] |
H A D | cs89x0.c | 439 writereg(struct net_device *dev, u16 regno, u16 value) function 467 writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD); 913 writereg(dev, PP_CS8900_ISADMA, dma-5); 915 writereg(dev, PP_CS8920_ISADMA, dma); 1039 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); 1079 writereg(dev, PP_SelfCTL, selfcontrol); 1106 writereg(dev, PP_LineCTL, lp->linectl &~ AUI_ONLY); 1125 writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900); 1142 writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK); 1171 writereg(de [all...] |
H A D | ni65.c | 150 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} macro 152 #define writedatareg(val) { writereg(val,CSR0); } 253 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ 262 writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */ 506 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ 550 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); 561 writereg(0,CSR3); /* busmaster/no word-swap */ 563 writereg(pib & 0xffff,CSR1); 564 writereg(pib >> 16,CSR2); 566 writereg(CSR0_INI [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/ |
H A D | gxt4500.c | 138 #define writereg(par, reg, val) writel((val), (par)->regs + (reg)) macro 387 writereg(par, DTG_CONTROL, ctrlreg); 399 writereg(par, PLL_C, tmp); 400 writereg(par, PLL_M, mdivtab[par->pll_m - 1]); 401 writereg(par, PLL_N, ndivtab[par->pll_n - 2]); 404 writereg(par, PLL_POSTDIV, tmp | 0x9); 407 writereg(par, PLL_POSTDIV, tmp); 411 writereg(par, CURSOR_MODE, CURSOR_MODE_OFF); 414 writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16)); 416 writereg(pa [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/isdn/hisax/ |
H A D | asuscom.c | 64 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 88 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); 112 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset|0x80, value); 137 writereg(cs->hw.asus.adr, 147 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.asus.adr, \ 186 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); 187 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); 188 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0xFF); 189 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0x0); 190 writereg(c [all...] |
H A D | mic.c | 52 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 76 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); 101 writereg(cs->hw.mic.adr, 111 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \ 150 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); 151 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); 152 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF); 153 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0); 154 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); 155 writereg(c [all...] |
H A D | sedlbauer.c | 140 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 164 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); 188 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset|0x80, value); 213 writereg(cs->hw.sedl.adr, 237 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); 251 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.sedl.adr, \ 298 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); 299 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); 300 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); 301 writereg(c [all...] |
H A D | avm_a1.c | 36 writereg(unsigned int adr, u_char off, u_char data) function 65 writereg(cs->hw.avm.isac, offset, value); 89 writereg(cs->hw.avm.hscx[hscx], offset, value); 97 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data) 128 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); 129 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); 130 writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); 131 writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); 132 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); 133 writereg(c [all...] |
H A D | ix1_micro.c | 61 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 85 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); 110 writereg(cs->hw.ix1.hscx_ale, 116 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \ 155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); 156 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); 157 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); 158 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); 159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); 160 writereg(c [all...] |
H A D | niccy.c | 63 static inline void writereg(unsigned int ale, unsigned int adr, u_char off, function 86 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); 108 writereg(cs->hw.niccy.hscx_ale, 114 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \ 163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); 164 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 166 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); 167 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); 168 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); 169 writereg(c [all...] |
H A D | s0box.c | 23 writereg(unsigned int padr, signed int addr, u_char off, u_char val) { function 105 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); 129 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); 137 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data) 176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); 177 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); 178 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF); 179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0); 180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); 181 writereg(c [all...] |
H A D | saphir.c | 53 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 77 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); 102 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, 108 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \ 152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); 153 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); 154 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); 155 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); 156 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); 157 writereg(c [all...] |
H A D | bkm_a8.c | 64 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 90 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); 115 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); 123 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 133 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \ 189 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); 190 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); 393 writereg(pci_ioaddr5, pci_ioaddr5 + 4, 395 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c, 397 writereg(pci_ioaddr [all...] |
H A D | teles3.c | 36 writereg(unsigned int adr, u_char off, u_char data) function 65 writereg(cs->hw.teles3.isac, offset, value); 89 writereg(cs->hw.teles3.hscx[hscx], offset, value); 97 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data) 136 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); 137 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); 138 writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); 139 writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); 140 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); 141 writereg(c [all...] |
H A D | elsa.c | 161 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 185 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); 209 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset|0x80, value); 234 writereg(cs->hw.elsa.ale, 273 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.elsa.ale, \ 334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); 335 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); 336 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF); 356 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); 357 writereg(c [all...] |
H A D | bkm_a4t.c | 53 writereg(unsigned int ale, unsigned long adr, u_char off, u_char data) function 69 writereg(ale, adr, off, *data++); 84 writereg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset, value); 108 writereg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)), value); 117 #define WRITEJADE(cs, nr, reg, data) writereg(cs->hw.ax.jade_ale,\
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H A D | diva.c | 102 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 142 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); 166 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset|0x80, value); 191 writereg(cs->hw.diva.hscx_adr, 280 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \ 311 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); 312 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); 313 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); 314 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); 315 writereg(c [all...] |
H A D | teleint.c | 66 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function 115 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); 177 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0xFF); 178 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0x0);
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H A D | gazel.c | 52 writereg(unsigned int adr, u_short off, u_char data) function 130 writereg(cs->hw.gazel.isac, off2, value); 225 writereg(cs->hw.gazel.hscx[hscx], off2, value); 355 writereg(addr, 0, 0); 357 writereg(addr, 0, 1);
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/media/video/ |
H A D | zr36016.c | 110 if (ptr->codec->master_data->writereg) { 111 ptr->codec->master_data->writereg(ptr->codec, reg, value); 129 if ((ptr->codec->master_data->writereg) && 131 ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F); // ADDR 153 if (ptr->codec->master_data->writereg) { 154 ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F); // ADDR 155 ptr->codec->master_data->writereg(ptr->codec, ZR016_IDATA, value & 0x0FF); // DATA
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H A D | videocodec.h | 83 writereg -> ref. to write-fn to register (setup by master, used by slave) 336 void (*writereg) (struct videocodec * codec, 332 void (*writereg) (struct videocodec * codec, member in struct:videocodec_master
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H A D | zoran_card.c | 1238 m->writereg = zr36060_write; 1243 m->writereg = zr36050_write; 1248 m->writereg = zr36016_write;
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H A D | zr36050.c | 106 if (ptr->codec->master_data->writereg) 107 ptr->codec->master_data->writereg(ptr->codec, reg, value);
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H A D | zr36060.c | 108 if (ptr->codec->master_data->writereg) 109 ptr->codec->master_data->writereg(ptr->codec, reg, value);
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