1/* 2 * Frame buffer device for IBM GXT4500P and GXT6000P display adaptors 3 * 4 * Copyright (C) 2006 Paul Mackerras, IBM Corp. <paulus@samba.org> 5 */ 6 7#include <linux/kernel.h> 8#include <linux/module.h> 9#include <linux/fb.h> 10#include <linux/console.h> 11#include <linux/pci.h> 12#include <linux/pci_ids.h> 13#include <linux/delay.h> 14#include <linux/string.h> 15 16#define PCI_DEVICE_ID_IBM_GXT4500P 0x21c 17#define PCI_DEVICE_ID_IBM_GXT6000P 0x170 18 19/* GXT4500P registers */ 20 21/* Registers in PCI config space */ 22#define CFG_ENDIAN0 0x40 23 24/* Misc control/status registers */ 25#define STATUS 0x1000 26#define CTRL_REG0 0x1004 27#define CR0_HALT_DMA 0x4 28#define CR0_RASTER_RESET 0x8 29#define CR0_GEOM_RESET 0x10 30#define CR0_MEM_CTRLER_RESET 0x20 31 32/* Framebuffer control registers */ 33#define FB_AB_CTRL 0x1100 34#define FB_CD_CTRL 0x1104 35#define FB_WID_CTRL 0x1108 36#define FB_Z_CTRL 0x110c 37#define FB_VGA_CTRL 0x1110 38#define REFRESH_AB_CTRL 0x1114 39#define REFRESH_CD_CTRL 0x1118 40#define FB_OVL_CTRL 0x111c 41#define FB_CTRL_TYPE 0x80000000 42#define FB_CTRL_WIDTH_MASK 0x007f0000 43#define FB_CTRL_WIDTH_SHIFT 16 44#define FB_CTRL_START_SEG_MASK 0x00003fff 45 46#define REFRESH_START 0x1098 47#define REFRESH_SIZE 0x109c 48 49/* "Direct" framebuffer access registers */ 50#define DFA_FB_A 0x11e0 51#define DFA_FB_B 0x11e4 52#define DFA_FB_C 0x11e8 53#define DFA_FB_D 0x11ec 54#define DFA_FB_ENABLE 0x80000000 55#define DFA_FB_BASE_MASK 0x03f00000 56#define DFA_FB_STRIDE_1k 0x00000000 57#define DFA_FB_STRIDE_2k 0x00000010 58#define DFA_FB_STRIDE_4k 0x00000020 59#define DFA_PIX_8BIT 0x00000000 60#define DFA_PIX_16BIT_565 0x00000001 61#define DFA_PIX_16BIT_1555 0x00000002 62#define DFA_PIX_24BIT 0x00000004 63#define DFA_PIX_32BIT 0x00000005 64 65/* maps DFA_PIX_* to pixel size in bytes */ 66static const unsigned char pixsize[] = { 67 1, 2, 2, 2, 4, 4 68}; 69 70/* Display timing generator registers */ 71#define DTG_CONTROL 0x1900 72#define DTG_CTL_SCREEN_REFRESH 2 73#define DTG_CTL_ENABLE 1 74#define DTG_HORIZ_EXTENT 0x1904 75#define DTG_HORIZ_DISPLAY 0x1908 76#define DTG_HSYNC_START 0x190c 77#define DTG_HSYNC_END 0x1910 78#define DTG_HSYNC_END_COMP 0x1914 79#define DTG_VERT_EXTENT 0x1918 80#define DTG_VERT_DISPLAY 0x191c 81#define DTG_VSYNC_START 0x1920 82#define DTG_VSYNC_END 0x1924 83#define DTG_VERT_SHORT 0x1928 84 85/* PLL/RAMDAC registers */ 86#define DISP_CTL 0x402c 87#define DISP_CTL_OFF 2 88#define SYNC_CTL 0x4034 89#define SYNC_CTL_SYNC_ON_RGB 1 90#define SYNC_CTL_SYNC_OFF 2 91#define SYNC_CTL_HSYNC_INV 8 92#define SYNC_CTL_VSYNC_INV 0x10 93#define SYNC_CTL_HSYNC_OFF 0x20 94#define SYNC_CTL_VSYNC_OFF 0x40 95 96#define PLL_M 0x4040 97#define PLL_N 0x4044 98#define PLL_POSTDIV 0x4048 99#define PLL_C 0x404c 100 101/* Hardware cursor */ 102#define CURSOR_X 0x4078 103#define CURSOR_Y 0x407c 104#define CURSOR_HOTSPOT 0x4080 105#define CURSOR_MODE 0x4084 106#define CURSOR_MODE_OFF 0 107#define CURSOR_MODE_4BPP 1 108#define CURSOR_PIXMAP 0x5000 109#define CURSOR_CMAP 0x7400 110 111/* Window attribute table */ 112#define WAT_FMT 0x4100 113#define WAT_FMT_24BIT 0 114#define WAT_FMT_16BIT_565 1 115#define WAT_FMT_16BIT_1555 2 116#define WAT_FMT_32BIT 3 /* 0 vs. 3 is a guess */ 117#define WAT_FMT_8BIT_332 9 118#define WAT_FMT_8BIT 0xa 119#define WAT_FMT_NO_CMAP 4 /* ORd in to other values */ 120#define WAT_CMAP_OFFSET 0x4104 /* 4-bit value gets << 6 */ 121#define WAT_CTRL 0x4108 122#define WAT_CTRL_SEL_B 1 /* select B buffer if 1 */ 123#define WAT_CTRL_NO_INC 2 124#define WAT_GAMMA_CTRL 0x410c 125#define WAT_GAMMA_DISABLE 1 /* disables gamma cmap */ 126#define WAT_OVL_CTRL 0x430c /* controls overlay */ 127 128/* Indexed by DFA_PIX_* values */ 129static const unsigned char watfmt[] = { 130 WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0, 131 WAT_FMT_24BIT, WAT_FMT_32BIT 132}; 133 134/* Colormap array; 1k entries of 4 bytes each */ 135#define CMAP 0x6000 136 137#define readreg(par, reg) readl((par)->regs + (reg)) 138#define writereg(par, reg, val) writel((val), (par)->regs + (reg)) 139 140struct gxt4500_par { 141 void __iomem *regs; 142 143 int pixfmt; /* pixel format, see DFA_PIX_* values */ 144 145 /* PLL parameters */ 146 int refclk_ps; /* ref clock period in picoseconds */ 147 int pll_m; /* ref clock divisor */ 148 int pll_n; /* VCO divisor */ 149 int pll_pd1; /* first post-divisor */ 150 int pll_pd2; /* second post-divisor */ 151 152 u32 pseudo_palette[16]; /* used in color blits */ 153}; 154 155/* mode requested by user */ 156static char *mode_option; 157 158/* default mode: 1280x1024 @ 60 Hz, 8 bpp */ 159static const struct fb_videomode defaultmode __devinitdata = { 160 .refresh = 60, 161 .xres = 1280, 162 .yres = 1024, 163 .pixclock = 9295, 164 .left_margin = 248, 165 .right_margin = 48, 166 .upper_margin = 38, 167 .lower_margin = 1, 168 .hsync_len = 112, 169 .vsync_len = 3, 170 .vmode = FB_VMODE_NONINTERLACED 171}; 172 173/* List of supported cards */ 174enum gxt_cards { 175 GXT4500P, 176 GXT6000P 177}; 178 179/* Card-specific information */ 180static const struct cardinfo { 181 int refclk_ps; /* period of PLL reference clock in ps */ 182 const char *cardname; 183} cardinfo[] = { 184 [GXT4500P] = { .refclk_ps = 9259, .cardname = "IBM GXT4500P" }, 185 [GXT6000P] = { .refclk_ps = 40000, .cardname = "IBM GXT6000P" }, 186}; 187 188/* 189 * The refclk and VCO dividers appear to use a linear feedback shift 190 * register, which gets reloaded when it reaches a terminal value, at 191 * which point the divider output is toggled. Thus one can obtain 192 * whatever divisor is required by putting the appropriate value into 193 * the reload register. For a divisor of N, one puts the value from 194 * the LFSR sequence that comes N-1 places before the terminal value 195 * into the reload register. 196 */ 197 198static const unsigned char mdivtab[] = { 199/* 1 */ 0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a, 200/* 10 */ 0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11, 201/* 20 */ 0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d, 202/* 30 */ 0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02, 203/* 40 */ 0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e, 204/* 50 */ 0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e, 205/* 60 */ 0x1f, 0x0f, 0x07, 0x03, 0x01, 206}; 207 208static const unsigned char ndivtab[] = { 209/* 2 */ 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e, 210/* 10 */ 0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e, 211/* 20 */ 0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf, 212/* 30 */ 0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc, 213/* 40 */ 0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8, 214/* 50 */ 0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6, 215/* 60 */ 0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62, 216/* 70 */ 0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57, 217/* 80 */ 0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94, 218/* 90 */ 0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79, 219/* 100 */ 0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24, 220/* 110 */ 0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45, 221/* 120 */ 0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d, 222/* 130 */ 0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e, 223/* 140 */ 0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98, 224/* 150 */ 0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2, 225/* 160 */ 0x69, 226}; 227 228static int calc_pll(int period_ps, struct gxt4500_par *par) 229{ 230 int m, n, pdiv1, pdiv2, postdiv; 231 int pll_period, best_error, t, intf; 232 233 /* only deal with range 5MHz - 300MHz */ 234 if (period_ps < 3333 || period_ps > 200000) 235 return -1; 236 237 best_error = 1000000; 238 for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) { 239 for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) { 240 postdiv = pdiv1 * pdiv2; 241 pll_period = (period_ps + postdiv - 1) / postdiv; 242 /* keep pll in range 350..600 MHz */ 243 if (pll_period < 1666 || pll_period > 2857) 244 continue; 245 for (m = 1; m <= 64; ++m) { 246 intf = m * par->refclk_ps; 247 if (intf > 500000) 248 break; 249 n = intf * postdiv / period_ps; 250 if (n < 3 || n > 160) 251 continue; 252 t = par->refclk_ps * m * postdiv / n; 253 t -= period_ps; 254 if (t >= 0 && t < best_error) { 255 par->pll_m = m; 256 par->pll_n = n; 257 par->pll_pd1 = pdiv1; 258 par->pll_pd2 = pdiv2; 259 best_error = t; 260 } 261 } 262 } 263 } 264 if (best_error == 1000000) 265 return -1; 266 return 0; 267} 268 269static int calc_pixclock(struct gxt4500_par *par) 270{ 271 return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2 272 / par->pll_n; 273} 274 275static int gxt4500_var_to_par(struct fb_var_screeninfo *var, 276 struct gxt4500_par *par) 277{ 278 if (var->xres + var->xoffset > var->xres_virtual || 279 var->yres + var->yoffset > var->yres_virtual || 280 var->xres_virtual > 4096) 281 return -EINVAL; 282 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 283 return -EINVAL; 284 285 if (calc_pll(var->pixclock, par) < 0) 286 return -EINVAL; 287 288 switch (var->bits_per_pixel) { 289 case 32: 290 if (var->transp.length) 291 par->pixfmt = DFA_PIX_32BIT; 292 else 293 par->pixfmt = DFA_PIX_24BIT; 294 break; 295 case 24: 296 par->pixfmt = DFA_PIX_24BIT; 297 break; 298 case 16: 299 if (var->green.length == 5) 300 par->pixfmt = DFA_PIX_16BIT_1555; 301 else 302 par->pixfmt = DFA_PIX_16BIT_565; 303 break; 304 case 8: 305 par->pixfmt = DFA_PIX_8BIT; 306 break; 307 default: 308 return -EINVAL; 309 } 310 311 return 0; 312} 313 314static const struct fb_bitfield eightbits = {0, 8}; 315static const struct fb_bitfield nobits = {0, 0}; 316 317static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var, 318 int pixfmt) 319{ 320 var->bits_per_pixel = pixsize[pixfmt] * 8; 321 var->red = eightbits; 322 var->green = eightbits; 323 var->blue = eightbits; 324 var->transp = nobits; 325 326 switch (pixfmt) { 327 case DFA_PIX_16BIT_565: 328 var->red.length = 5; 329 var->green.length = 6; 330 var->blue.length = 5; 331 break; 332 case DFA_PIX_16BIT_1555: 333 var->red.length = 5; 334 var->green.length = 5; 335 var->blue.length = 5; 336 var->transp.length = 1; 337 break; 338 case DFA_PIX_32BIT: 339 var->transp.length = 8; 340 break; 341 } 342 if (pixfmt != DFA_PIX_8BIT) { 343 var->green.offset = var->red.length; 344 var->blue.offset = var->green.offset + var->green.length; 345 if (var->transp.length) 346 var->transp.offset = 347 var->blue.offset + var->blue.length; 348 } 349} 350 351static int gxt4500_check_var(struct fb_var_screeninfo *var, 352 struct fb_info *info) 353{ 354 struct gxt4500_par par; 355 int err; 356 357 par = *(struct gxt4500_par *)info->par; 358 err = gxt4500_var_to_par(var, &par); 359 if (!err) { 360 var->pixclock = calc_pixclock(&par); 361 gxt4500_unpack_pixfmt(var, par.pixfmt); 362 } 363 return err; 364} 365 366static int gxt4500_set_par(struct fb_info *info) 367{ 368 struct gxt4500_par *par = info->par; 369 struct fb_var_screeninfo *var = &info->var; 370 int err; 371 u32 ctrlreg, tmp; 372 unsigned int dfa_ctl, pixfmt, stride; 373 unsigned int wid_tiles, i; 374 unsigned int prefetch_pix, htot; 375 struct gxt4500_par save_par; 376 377 save_par = *par; 378 err = gxt4500_var_to_par(var, par); 379 if (err) { 380 *par = save_par; 381 return err; 382 } 383 384 /* turn off DTG for now */ 385 ctrlreg = readreg(par, DTG_CONTROL); 386 ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH); 387 writereg(par, DTG_CONTROL, ctrlreg); 388 389 /* set PLL registers */ 390 tmp = readreg(par, PLL_C) & ~0x7f; 391 if (par->pll_n < 38) 392 tmp |= 0x29; 393 if (par->pll_n < 69) 394 tmp |= 0x35; 395 else if (par->pll_n < 100) 396 tmp |= 0x76; 397 else 398 tmp |= 0x7e; 399 writereg(par, PLL_C, tmp); 400 writereg(par, PLL_M, mdivtab[par->pll_m - 1]); 401 writereg(par, PLL_N, ndivtab[par->pll_n - 2]); 402 tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1); 403 if (par->pll_pd1 == 8 || par->pll_pd2 == 8) { 404 writereg(par, PLL_POSTDIV, tmp | 0x9); 405 udelay(1); 406 } 407 writereg(par, PLL_POSTDIV, tmp); 408 msleep(20); 409 410 /* turn off hardware cursor */ 411 writereg(par, CURSOR_MODE, CURSOR_MODE_OFF); 412 413 /* reset raster engine */ 414 writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16)); 415 udelay(10); 416 writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16); 417 418 /* set display timing generator registers */ 419 htot = var->xres + var->left_margin + var->right_margin + 420 var->hsync_len; 421 writereg(par, DTG_HORIZ_EXTENT, htot - 1); 422 writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1); 423 writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1); 424 writereg(par, DTG_HSYNC_END, 425 var->xres + var->right_margin + var->hsync_len - 1); 426 writereg(par, DTG_HSYNC_END_COMP, 427 var->xres + var->right_margin + var->hsync_len - 1); 428 writereg(par, DTG_VERT_EXTENT, 429 var->yres + var->upper_margin + var->lower_margin + 430 var->vsync_len - 1); 431 writereg(par, DTG_VERT_DISPLAY, var->yres - 1); 432 writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1); 433 writereg(par, DTG_VSYNC_END, 434 var->yres + var->lower_margin + var->vsync_len - 1); 435 prefetch_pix = 3300000 / var->pixclock; 436 if (prefetch_pix >= htot) 437 prefetch_pix = htot - 1; 438 writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1); 439 ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH; 440 writereg(par, DTG_CONTROL, ctrlreg); 441 442 /* calculate stride in DFA aperture */ 443 if (var->xres_virtual > 2048) { 444 stride = 4096; 445 dfa_ctl = DFA_FB_STRIDE_4k; 446 } else if (var->xres_virtual > 1024) { 447 stride = 2048; 448 dfa_ctl = DFA_FB_STRIDE_2k; 449 } else { 450 stride = 1024; 451 dfa_ctl = DFA_FB_STRIDE_1k; 452 } 453 454 /* Set up framebuffer definition */ 455 wid_tiles = (var->xres_virtual + 63) >> 6; 456 457 writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 458 writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 459 writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 460 writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); 461 writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset); 462 writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres); 463 464 /* Set up framebuffer access by CPU */ 465 466 pixfmt = par->pixfmt; 467 dfa_ctl |= DFA_FB_ENABLE | pixfmt; 468 writereg(par, DFA_FB_A, dfa_ctl); 469 470 /* 471 * Set up window attribute table. 472 * We set all WAT entries the same so it doesn't matter what the 473 * window ID (WID) plane contains. 474 */ 475 for (i = 0; i < 32; ++i) { 476 writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]); 477 writereg(par, WAT_CMAP_OFFSET + (i << 4), 0); 478 writereg(par, WAT_CTRL + (i << 4), 0); 479 writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE); 480 } 481 482 /* Set sync polarity etc. */ 483 ctrlreg = readreg(par, SYNC_CTL) & 484 ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV | 485 SYNC_CTL_VSYNC_INV); 486 if (var->sync & FB_SYNC_ON_GREEN) 487 ctrlreg |= SYNC_CTL_SYNC_ON_RGB; 488 if (!(var->sync & FB_SYNC_HOR_HIGH_ACT)) 489 ctrlreg |= SYNC_CTL_HSYNC_INV; 490 if (!(var->sync & FB_SYNC_VERT_HIGH_ACT)) 491 ctrlreg |= SYNC_CTL_VSYNC_INV; 492 writereg(par, SYNC_CTL, ctrlreg); 493 494 info->fix.line_length = stride * pixsize[pixfmt]; 495 info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR: 496 FB_VISUAL_DIRECTCOLOR; 497 498 return 0; 499} 500 501static int gxt4500_setcolreg(unsigned int reg, unsigned int red, 502 unsigned int green, unsigned int blue, 503 unsigned int transp, struct fb_info *info) 504{ 505 u32 cmap_entry; 506 struct gxt4500_par *par = info->par; 507 508 if (reg > 1023) 509 return 1; 510 cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) | 511 (green & 0xff00) | (blue >> 8); 512 writereg(par, CMAP + reg * 4, cmap_entry); 513 514 if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) { 515 u32 *pal = info->pseudo_palette; 516 u32 val = reg; 517 switch (par->pixfmt) { 518 case DFA_PIX_16BIT_565: 519 val |= (reg << 11) | (reg << 6); 520 break; 521 case DFA_PIX_16BIT_1555: 522 val |= (reg << 10) | (reg << 5); 523 break; 524 case DFA_PIX_32BIT: 525 val |= (reg << 24); 526 /* fall through */ 527 case DFA_PIX_24BIT: 528 val |= (reg << 16) | (reg << 8); 529 break; 530 } 531 pal[reg] = val; 532 } 533 534 return 0; 535} 536 537static int gxt4500_pan_display(struct fb_var_screeninfo *var, 538 struct fb_info *info) 539{ 540 struct gxt4500_par *par = info->par; 541 542 if (var->xoffset & 7) 543 return -EINVAL; 544 if (var->xoffset + var->xres > var->xres_virtual || 545 var->yoffset + var->yres > var->yres_virtual) 546 return -EINVAL; 547 548 writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset); 549 return 0; 550} 551 552static int gxt4500_blank(int blank, struct fb_info *info) 553{ 554 struct gxt4500_par *par = info->par; 555 int ctrl, dctl; 556 557 ctrl = readreg(par, SYNC_CTL); 558 ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF); 559 dctl = readreg(par, DISP_CTL); 560 dctl |= DISP_CTL_OFF; 561 switch (blank) { 562 case FB_BLANK_UNBLANK: 563 dctl &= ~DISP_CTL_OFF; 564 break; 565 case FB_BLANK_POWERDOWN: 566 ctrl |= SYNC_CTL_SYNC_OFF; 567 break; 568 case FB_BLANK_HSYNC_SUSPEND: 569 ctrl |= SYNC_CTL_HSYNC_OFF; 570 break; 571 case FB_BLANK_VSYNC_SUSPEND: 572 ctrl |= SYNC_CTL_VSYNC_OFF; 573 break; 574 default: ; 575 } 576 writereg(par, SYNC_CTL, ctrl); 577 writereg(par, DISP_CTL, dctl); 578 579 return 0; 580} 581 582static const struct fb_fix_screeninfo gxt4500_fix __devinitdata = { 583 .id = "IBM GXT4500P", 584 .type = FB_TYPE_PACKED_PIXELS, 585 .visual = FB_VISUAL_PSEUDOCOLOR, 586 .xpanstep = 8, 587 .ypanstep = 1, 588 .mmio_len = 0x20000, 589}; 590 591static struct fb_ops gxt4500_ops = { 592 .owner = THIS_MODULE, 593 .fb_check_var = gxt4500_check_var, 594 .fb_set_par = gxt4500_set_par, 595 .fb_setcolreg = gxt4500_setcolreg, 596 .fb_pan_display = gxt4500_pan_display, 597 .fb_blank = gxt4500_blank, 598 .fb_fillrect = cfb_fillrect, 599 .fb_copyarea = cfb_copyarea, 600 .fb_imageblit = cfb_imageblit, 601}; 602 603/* PCI functions */ 604static int __devinit gxt4500_probe(struct pci_dev *pdev, 605 const struct pci_device_id *ent) 606{ 607 int err; 608 unsigned long reg_phys, fb_phys; 609 struct gxt4500_par *par; 610 struct fb_info *info; 611 struct fb_var_screeninfo var; 612 enum gxt_cards cardtype; 613 614 err = pci_enable_device(pdev); 615 if (err) { 616 dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n", 617 err); 618 return err; 619 } 620 621 reg_phys = pci_resource_start(pdev, 0); 622 if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0), 623 "gxt4500 regs")) { 624 dev_err(&pdev->dev, "gxt4500: cannot get registers\n"); 625 goto err_nodev; 626 } 627 628 fb_phys = pci_resource_start(pdev, 1); 629 if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1), 630 "gxt4500 FB")) { 631 dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n"); 632 goto err_free_regs; 633 } 634 635 info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev); 636 if (!info) { 637 dev_err(&pdev->dev, "gxt4500: cannot alloc FB info record"); 638 goto err_free_fb; 639 } 640 par = info->par; 641 cardtype = ent->driver_data; 642 par->refclk_ps = cardinfo[cardtype].refclk_ps; 643 info->fix = gxt4500_fix; 644 strlcpy(info->fix.id, cardinfo[cardtype].cardname, 645 sizeof(info->fix.id)); 646 info->pseudo_palette = par->pseudo_palette; 647 648 info->fix.mmio_start = reg_phys; 649 par->regs = ioremap(reg_phys, pci_resource_len(pdev, 0)); 650 if (!par->regs) { 651 dev_err(&pdev->dev, "gxt4500: cannot map registers\n"); 652 goto err_free_all; 653 } 654 655 info->fix.smem_start = fb_phys; 656 info->fix.smem_len = pci_resource_len(pdev, 1); 657 info->screen_base = ioremap(fb_phys, pci_resource_len(pdev, 1)); 658 if (!info->screen_base) { 659 dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n"); 660 goto err_unmap_regs; 661 } 662 663 pci_set_drvdata(pdev, info); 664 665 /* Set byte-swapping for DFA aperture for all pixel sizes */ 666 pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300); 667 668 info->fbops = &gxt4500_ops; 669 info->flags = FBINFO_FLAG_DEFAULT; 670 671 err = fb_alloc_cmap(&info->cmap, 256, 0); 672 if (err) { 673 dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n"); 674 goto err_unmap_all; 675 } 676 677 gxt4500_blank(FB_BLANK_UNBLANK, info); 678 679 if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) { 680 dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n"); 681 goto err_free_cmap; 682 } 683 info->var = var; 684 if (gxt4500_set_par(info)) { 685 printk(KERN_ERR "gxt4500: cannot set video mode\n"); 686 goto err_free_cmap; 687 } 688 689 if (register_framebuffer(info) < 0) { 690 dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n"); 691 goto err_free_cmap; 692 } 693 printk(KERN_INFO "fb%d: %s frame buffer device\n", 694 info->node, info->fix.id); 695 696 return 0; 697 698 err_free_cmap: 699 fb_dealloc_cmap(&info->cmap); 700 err_unmap_all: 701 iounmap(info->screen_base); 702 err_unmap_regs: 703 iounmap(par->regs); 704 err_free_all: 705 framebuffer_release(info); 706 err_free_fb: 707 release_mem_region(fb_phys, pci_resource_len(pdev, 1)); 708 err_free_regs: 709 release_mem_region(reg_phys, pci_resource_len(pdev, 0)); 710 err_nodev: 711 return -ENODEV; 712} 713 714static void __devexit gxt4500_remove(struct pci_dev *pdev) 715{ 716 struct fb_info *info = pci_get_drvdata(pdev); 717 struct gxt4500_par *par; 718 719 if (!info) 720 return; 721 par = info->par; 722 unregister_framebuffer(info); 723 fb_dealloc_cmap(&info->cmap); 724 iounmap(par->regs); 725 iounmap(info->screen_base); 726 release_mem_region(pci_resource_start(pdev, 0), 727 pci_resource_len(pdev, 0)); 728 release_mem_region(pci_resource_start(pdev, 1), 729 pci_resource_len(pdev, 1)); 730 framebuffer_release(info); 731} 732 733/* supported chipsets */ 734static const struct pci_device_id gxt4500_pci_tbl[] = { 735 { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P), 736 .driver_data = GXT4500P }, 737 { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P), 738 .driver_data = GXT6000P }, 739 { 0 } 740}; 741 742MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl); 743 744static struct pci_driver gxt4500_driver = { 745 .name = "gxt4500", 746 .id_table = gxt4500_pci_tbl, 747 .probe = gxt4500_probe, 748 .remove = __devexit_p(gxt4500_remove), 749}; 750 751static int __devinit gxt4500_init(void) 752{ 753#ifndef MODULE 754 if (fb_get_options("gxt4500", &mode_option)) 755 return -ENODEV; 756#endif 757 758 return pci_register_driver(&gxt4500_driver); 759} 760module_init(gxt4500_init); 761 762static void __exit gxt4500_exit(void) 763{ 764 pci_unregister_driver(&gxt4500_driver); 765} 766module_exit(gxt4500_exit); 767 768MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>"); 769MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6000P"); 770MODULE_LICENSE("GPL"); 771module_param(mode_option, charp, 0); 772MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\""); 773