Lines Matching refs:writereg
150 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);}
152 #define writedatareg(val) { writereg(val,CSR0); }
253 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */
262 writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */
506 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */
550 writereg(CSR0_CLRALL|CSR0_STOP,CSR0);
561 writereg(0,CSR3); /* busmaster/no word-swap */
563 writereg(pib & 0xffff,CSR1);
564 writereg(pib >> 16,CSR2);
566 writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */