Searched refs:timing (Results 1 - 25 of 60) sorted by relevance

123

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ide/pci/
H A Dtriflex.c48 u16 timing = 0; local
57 timing = 0x0103;
60 timing = 0x0203;
63 timing = 0x0808;
68 timing = 0x0f0f;
71 timing = 0x0202;
74 timing = 0x0204;
77 timing = 0x0404;
80 timing = 0x0508;
83 timing
[all...]
H A Dvia82cxxx.c42 #include "ide-timing.h"
117 * via_set_speed - write timing registers
120 * @timing: IDE timing data to use
122 * via_set_speed writes timing values to the chipset registers
125 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) argument
133 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
138 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
141 ((FIT(timing
[all...]
H A Damd74xx.c28 #include "ide-timing.h"
207 * amd_set_speed() writes timing values to the chipset registers
210 static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing) argument
215 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
219 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
222 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
225 case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing
[all...]
H A Dit821x.c41 * timing and policy set up. Each HDD in raid mode also has a serial
83 The high byte is the 66Mhz timing */
108 * @timing: timing info
110 * Program the PIO/MWDMA timing for this channel according to the
114 static void it821x_program(ide_drive_t *drive, u16 timing) argument
121 /* Program PIO/MWDMA timing bits */
123 conf = timing >> 8;
125 conf = timing & 0xFF;
132 * @timing
138 it821x_program_udma(ide_drive_t *drive, u16 timing) argument
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/
H A Dgbefb.c39 struct gbe_timing_info timing; member in struct:gbefb_par
401 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) argument
407 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
409 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
417 timing->pll_m = 4;
418 timing->pll_n = 1;
419 timing->pll_p = 0;
446 struct gbe_timing_info *timing)
457 /* Determine valid resolution and timing
493 /* set video timing informatio
445 compute_gbe_timing(struct fb_var_screeninfo *var, struct gbe_timing_info *timing) argument
521 gbe_set_timing_info(struct gbe_timing_info *timing) argument
895 struct gbe_timing_info timing; local
[all...]
H A Dsgivwfb.c229 struct dbe_timing_info *timing; local
261 /* determine valid resolution and timing */
284 timing = &dbeVTimings[min_mode];
285 printk(KERN_INFO "sgivwfb: granted dot-clock=%d KHz\n", timing->cfreq);
339 /* set video timing information */
340 var->pixclock = KHZ2PICOS(timing->cfreq);
341 var->left_margin = timing->htotal - timing->hsync_end;
342 var->right_margin = timing->hsync_start - timing
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/media/video/
H A Dbt819.c84 struct timing { struct
94 static struct timing timing_data[] = {
217 struct timing *timing = &timing_data[decoder->norm]; local
220 (((timing->vdelay >> 8) & 0x03) << 6) | (((timing->
223 (((timing->hdelay >> 8) & 0x03) << 2) | ((timing->
226 init[0x04 * 2 - 1] = timing->vdelay & 0xff;
227 init[0x05 * 2 - 1] = timing
317 struct timing *timing = NULL; local
[all...]
H A Dzoran.h151 #define BUZ_MAX_WIDTH (zr->timing->Wa)
152 #define BUZ_MAX_HEIGHT (zr->timing->Ha)
409 struct tvnorm *timing; member in struct:zoran
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pcmcia/
H A Dsa11xx_base.c81 struct soc_pcmcia_timing timing; local
86 soc_common_pcmcia_get_timing(skt, &timing);
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
147 struct soc_pcmcia_timing timing; local
152 soc_common_pcmcia_get_timing(skt, &timing);
154 p+=sprintf(p, "I/O : %u (%u)\n", timing.io,
157 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
160 p+=sprintf(p, "common : %u (%u)\n", timing
[all...]
H A Dpxa2xx_base.c118 struct soc_pcmcia_timing timing; local
121 soc_common_pcmcia_get_timing(skt, &timing);
123 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
124 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
125 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
182 /* Provide our PXA2xx specific timing routines. */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ata/
H A Dpata_qdi.c34 unsigned long timing; member in struct:qdi_data
57 u8 timing; local
59 /* Get the timing data in cycles */
69 timing = (recovery << 4) | active | 0x08;
71 qdi->clock[adev->devno] = timing;
73 outb(timing, qdi->timing);
81 u8 timing; local
83 /* Get the timing data in cycles */
93 timing
[all...]
H A Dpata_cmd640.c54 struct cmd640_reg *timing = ap->private_data; local
68 /* The second channel has shared timings and the setup timing is
100 /* Load setup timing */
116 timing->reg58[adev->devno] = (t.active << 4) | t.recover;
134 struct cmd640_reg *timing = ap->private_data; local
136 if (ap->port_no != 0 && adev->devno != timing->last) {
137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]);
138 timing->last = adev->devno;
154 struct cmd640_reg *timing; local
160 timing
[all...]
H A Dpata_cs5530.c70 /* Now load the right timing register */
78 * cs5530_set_dmamode - DMA timing setup
90 u32 tuning, timing = 0; local
98 timing = 0x00921250;break;
100 timing = 0x00911140;break;
102 timing = 0x00911030;break;
104 timing = 0x00077771;break;
106 timing = 0x00012121;break;
108 timing = 0x00002020;break;
113 timing |
[all...]
H A Dpata_triflex.c79 * triflex_load_timing - timing configuration
93 u32 timing = 0; local
105 timing = 0x0103;break;
107 timing = 0x0203;break;
109 timing = 0x0808;break;
113 timing = 0x0F0F;break;
115 timing = 0x0202;break;
117 timing = 0x0204;break;
119 timing = 0x0404;break;
121 timing
[all...]
H A Dpata_sis.c305 t1 &= 0xC0C00FFF; /* Mask out timing */
332 u16 timing; local
337 pci_read_config_word(pdev, drive_pci, &timing);
340 /* bits 3-0 hold recovery timing bits 8-10 active timing and
342 timing &= ~ 0x870F;
343 timing |= mwdma_bits[speed];
344 pci_write_config_word(pdev, drive_pci, timing);
348 timing &= ~0x6000;
349 timing |
371 u16 timing; local
409 u8 timing; local
444 u8 timing; local
[all...]
H A Dpata_sl82c105.c16 * timing parameters.
73 * sl82c105_configure_piomode - set chip PIO timing
78 * Called to do the PIO mode setup. Our timing registers are shared
90 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local
92 pci_write_config_word(pdev, timing, pio_timing[pio]);
94 pci_read_config_word(pdev, timing, &dummy);
102 * Called to do the PIO mode setup. Our timing registers are shared
103 * but we want to set the PIO timing by default.
127 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local
130 pci_write_config_word(pdev, timing, dma_timin
[all...]
H A Dpata_via.c229 /* Calculate the timing values we require */
232 /* We share 8bit timing so we must merge the constraints */
496 u32 timing; local
545 pci_read_config_dword(pdev, 0x50, &timing);
546 timing |= 0x80008;
547 pci_write_config_dword(pdev, 0x50, timing);
562 pci_read_config_dword(pdev, 0x50, &timing);
563 timing &= ~0x80008;
564 pci_write_config_dword(pdev, 0x50, timing);
586 u32 timing; local
[all...]
H A Dpata_winbond.c68 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); local
72 /* Get the timing data in cycles */
80 timing = (active << 4) | recovery;
81 winbond_writecfg(winbond->config, timing, reg);
83 /* Load the setup timing */
91 winbond_writecfg(winbond->config, timing + 1, reg);
192 reg |= 0xF0; /* programmable timing */
H A Dpata_mpc52xx.c147 struct mpc52xx_ata_timings *timing = &priv->timings[dev]; local
162 timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
163 timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
172 struct mpc52xx_ata_timings *timing = &priv->timings[device]; local
174 out_be32(&regs->pio1, timing->pio1);
175 out_be32(&regs->pio2, timing->pio2);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ide/legacy/
H A Dht6560b.c93 * Perhaps I should explain something about these timing values:
108 * You can obtain optimized timing values by running Holtek IDESETUP.COM
109 * for DOS. DOS drivers get their timing values from command line, where
132 u8 select, timing; local
137 timing = HT_TIMING(drive);
139 if (select != current_select || timing != current_timing) {
141 current_timing = timing;
150 * Set timing for this drive:
152 outb(timing, IDE_SELECT_REG);
155 printk("ht6560b: %s: select=%#x timing
281 u8 timing; local
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/mtd/nand/
H A Dcafe_nand.c84 static int timing[3]; variable
85 module_param_array(timing, int, &numtimings, 0644);
679 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
684 timing[0], timing[1], timing[2]);
686 timing[0] = cafe_readl(cafe, NAND_TIMING1);
687 timing[1] = cafe_readl(cafe, NAND_TIMING2);
688 timing[2] = cafe_readl(cafe, NAND_TIMING3);
690 if (timing[
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ide/ppc/
H A Dmpc8xx.c425 ulong timing, mask, reg; local
438 timing = PCMCIA_SHT(hold_time[pio] )
443 printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
445 pcmp->pcmc_por0 = reg | timing;
448 pcmp->pcmc_por1 = reg | timing;
451 pcmp->pcmc_por2 = reg | timing;
454 pcmp->pcmc_por3 = reg | timing;
457 pcmp->pcmc_por4 = reg | timing;
460 pcmp->pcmc_por5 = reg | timing;
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/libxml2-2.7.2/
H A Dxmllint.c178 static int timing = 0; variable
395 * Internal timing routines to remove the necessity to have *
429 * startTimer: call where you want to start timing
438 * endTimer: call where you want to stop timing and to print out a
439 * message about the timing performed; format is a printf
498 * We don't have a gettimeofday or time.h, so we just don't do timing
511 * We cannot do anything because we don't have a timing function
1860 if ((timing) && (!repeat)) {
1870 if ((timing) && (!repeat)) {
1875 if ((timing)
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/mmc/core/
H A Dcore.h55 void mmc_set_timing(struct mmc_host *host, unsigned int timing);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/mmc/
H A Dhost.h43 unsigned char timing; /* timing specification used */ member in struct:mmc_ios
91 #define MMC_CAP_MMC_HIGHSPEED (1 << 3) /* Can do MMC high-speed timing */
92 #define MMC_CAP_SD_HIGHSPEED (1 << 4) /* Can do SD high-speed timing */

Completed in 170 milliseconds

123