1/* 2 * pata_via.c - VIA PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Documentation 7 * Most chipset documentation available under NDA only 8 * 9 * VIA version guide 10 * VIA VT82C561 - early design, uses ata_generic currently 11 * VIA VT82C576 - MWDMA, 33Mhz 12 * VIA VT82C586 - MWDMA, 33Mhz 13 * VIA VT82C586a - Added UDMA to 33Mhz 14 * VIA VT82C586b - UDMA33 15 * VIA VT82C596a - Nonfunctional UDMA66 16 * VIA VT82C596b - Working UDMA66 17 * VIA VT82C686 - Nonfunctional UDMA66 18 * VIA VT82C686a - Working UDMA66 19 * VIA VT82C686b - Updated to UDMA100 20 * VIA VT8231 - UDMA100 21 * VIA VT8233 - UDMA100 22 * VIA VT8233a - UDMA133 23 * VIA VT8233c - UDMA100 24 * VIA VT8235 - UDMA133 25 * VIA VT8237 - UDMA133 26 * VIA VT8237S - UDMA133 27 * VIA VT8251 - UDMA133 28 * 29 * Most registers remain compatible across chips. Others start reserved 30 * and acquire sensible semantics if set to 1 (eg cable detect). A few 31 * exceptions exist, notably around the FIFO settings. 32 * 33 * One additional quirk of the VIA design is that like ALi they use few 34 * PCI IDs for a lot of chips. 35 * 36 * Based heavily on: 37 * 38 * Version 3.38 39 * 40 * VIA IDE driver for Linux. Supported southbridges: 41 * 42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 44 * vt8235, vt8237 45 * 46 * Copyright (c) 2000-2002 Vojtech Pavlik 47 * 48 * Based on the work of: 49 * Michel Aubry 50 * Jeff Garzik 51 * Andre Hedrick 52 53 */ 54 55#include <linux/kernel.h> 56#include <linux/module.h> 57#include <linux/pci.h> 58#include <linux/init.h> 59#include <linux/blkdev.h> 60#include <linux/delay.h> 61#include <scsi/scsi_host.h> 62#include <linux/libata.h> 63#include <linux/dmi.h> 64 65#define DRV_NAME "pata_via" 66#define DRV_VERSION "0.3.1" 67 68/* 69 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx 70 * driver. 71 */ 72 73enum { 74 VIA_UDMA = 0x007, 75 VIA_UDMA_NONE = 0x000, 76 VIA_UDMA_33 = 0x001, 77 VIA_UDMA_66 = 0x002, 78 VIA_UDMA_100 = 0x003, 79 VIA_UDMA_133 = 0x004, 80 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ 81 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ 82 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ 83 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ 84 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ 85 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ 86 VIA_NO_ENABLES = 0x400, /* Has no enablebits */ 87}; 88 89/* 90 * VIA SouthBridge chips. 91 */ 92 93static const struct via_isa_bridge { 94 const char *name; 95 u16 id; 96 u8 rev_min; 97 u8 rev_max; 98 u16 flags; 99} via_isa_bridges[] = { 100 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 101 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 102 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 103 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES}, 104 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 105 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 106 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 107 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 108 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, 109 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, 110 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, 111 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, 112 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, 113 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 114 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, 115 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, 117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, 118 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, 119 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, 120 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, 122 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 123 { NULL } 124}; 125 126 127/* 128 * Cable special cases 129 */ 130 131static struct dmi_system_id cable_dmi_table[] = { 132 { 133 .ident = "Acer Ferrari 3400", 134 .matches = { 135 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), 136 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), 137 }, 138 }, 139 { } 140}; 141 142static int via_cable_override(struct pci_dev *pdev) 143{ 144 /* Systems by DMI */ 145 if (dmi_check_system(cable_dmi_table)) 146 return 1; 147 return 0; 148} 149 150 151/** 152 * via_cable_detect - cable detection 153 * @ap: ATA port 154 * 155 * Perform cable detection. Actually for the VIA case the BIOS 156 * already did this for us. We read the values provided by the 157 * BIOS. If you are using an 8235 in a non-PC configuration you 158 * may need to update this code. 159 * 160 * Hotplug also impacts on this. 161 */ 162 163static int via_cable_detect(struct ata_port *ap) { 164 const struct via_isa_bridge *config = ap->host->private_data; 165 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 166 u32 ata66; 167 168 if (via_cable_override(pdev)) 169 return ATA_CBL_PATA40_SHORT; 170 171 /* Early chips are 40 wire */ 172 if ((config->flags & VIA_UDMA) < VIA_UDMA_66) 173 return ATA_CBL_PATA40; 174 /* UDMA 66 chips have only drive side logic */ 175 else if((config->flags & VIA_UDMA) < VIA_UDMA_100) 176 return ATA_CBL_PATA_UNK; 177 /* UDMA 100 or later */ 178 pci_read_config_dword(pdev, 0x50, &ata66); 179 /* Check both the drive cable reporting bits, we might not have 180 two drives */ 181 if (ata66 & (0x10100000 >> (16 * ap->port_no))) 182 return ATA_CBL_PATA80; 183 return ATA_CBL_PATA40; 184} 185 186static int via_pre_reset(struct ata_port *ap, unsigned long deadline) 187{ 188 const struct via_isa_bridge *config = ap->host->private_data; 189 190 if (!(config->flags & VIA_NO_ENABLES)) { 191 static const struct pci_bits via_enable_bits[] = { 192 { 0x40, 1, 0x02, 0x02 }, 193 { 0x40, 1, 0x01, 0x01 } 194 }; 195 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 196 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) 197 return -ENOENT; 198 } 199 200 return ata_std_prereset(ap, deadline); 201} 202 203 204/** 205 * via_error_handler - reset for VIA chips 206 * @ap: ATA port 207 * 208 * Handle the reset callback for the later chips with cable detect 209 */ 210 211static void via_error_handler(struct ata_port *ap) 212{ 213 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 214} 215 216 217static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) 218{ 219 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 220 struct ata_device *peer = ata_dev_pair(adev); 221 struct ata_timing t, p; 222 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ 223 unsigned long T = 1000000000 / via_clock; 224 unsigned long UT = T/tdiv; 225 int ut; 226 int offset = 3 - (2*ap->port_no) - adev->devno; 227 228 229 /* Calculate the timing values we require */ 230 ata_timing_compute(adev, mode, &t, T, UT); 231 232 /* We share 8bit timing so we must merge the constraints */ 233 if (peer) { 234 if (peer->pio_mode) { 235 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); 236 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); 237 } 238 } 239 240 /* Address setup is programmable but breaks on UDMA133 setups */ 241 if (set_ast) { 242 u8 setup; /* 2 bits per drive */ 243 int shift = 2 * offset; 244 245 pci_read_config_byte(pdev, 0x4C, &setup); 246 setup &= ~(3 << shift); 247 setup |= FIT(t.setup, 1, 4) << shift; 248 pci_write_config_byte(pdev, 0x4C, setup); 249 } 250 251 /* Load the PIO mode bits */ 252 pci_write_config_byte(pdev, 0x4F - ap->port_no, 253 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1)); 254 pci_write_config_byte(pdev, 0x48 + offset, 255 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1)); 256 257 /* Load the UDMA bits according to type */ 258 switch(udma_type) { 259 default: 260 /* BUG() ? */ 261 /* fall through */ 262 case 33: 263 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03; 264 break; 265 case 66: 266 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f; 267 break; 268 case 100: 269 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; 270 break; 271 case 133: 272 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; 273 break; 274 } 275 /* Set UDMA unless device is not UDMA capable */ 276 if (udma_type) 277 pci_write_config_byte(pdev, 0x50 + offset, ut); 278} 279 280static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) 281{ 282 const struct via_isa_bridge *config = ap->host->private_data; 283 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 284 int mode = config->flags & VIA_UDMA; 285 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 286 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 287 288 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); 289} 290 291static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 292{ 293 const struct via_isa_bridge *config = ap->host->private_data; 294 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 295 int mode = config->flags & VIA_UDMA; 296 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 297 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 298 299 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); 300} 301 302static struct scsi_host_template via_sht = { 303 .module = THIS_MODULE, 304 .name = DRV_NAME, 305 .ioctl = ata_scsi_ioctl, 306 .queuecommand = ata_scsi_queuecmd, 307 .can_queue = ATA_DEF_QUEUE, 308 .this_id = ATA_SHT_THIS_ID, 309 .sg_tablesize = LIBATA_MAX_PRD, 310 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 311 .emulated = ATA_SHT_EMULATED, 312 .use_clustering = ATA_SHT_USE_CLUSTERING, 313 .proc_name = DRV_NAME, 314 .dma_boundary = ATA_DMA_BOUNDARY, 315 .slave_configure = ata_scsi_slave_config, 316 .slave_destroy = ata_scsi_slave_destroy, 317 .bios_param = ata_std_bios_param, 318}; 319 320static struct ata_port_operations via_port_ops = { 321 .port_disable = ata_port_disable, 322 .set_piomode = via_set_piomode, 323 .set_dmamode = via_set_dmamode, 324 .mode_filter = ata_pci_default_filter, 325 326 .tf_load = ata_tf_load, 327 .tf_read = ata_tf_read, 328 .check_status = ata_check_status, 329 .exec_command = ata_exec_command, 330 .dev_select = ata_std_dev_select, 331 332 .freeze = ata_bmdma_freeze, 333 .thaw = ata_bmdma_thaw, 334 .error_handler = via_error_handler, 335 .post_internal_cmd = ata_bmdma_post_internal_cmd, 336 .cable_detect = via_cable_detect, 337 338 .bmdma_setup = ata_bmdma_setup, 339 .bmdma_start = ata_bmdma_start, 340 .bmdma_stop = ata_bmdma_stop, 341 .bmdma_status = ata_bmdma_status, 342 343 .qc_prep = ata_qc_prep, 344 .qc_issue = ata_qc_issue_prot, 345 346 .data_xfer = ata_data_xfer, 347 348 .irq_handler = ata_interrupt, 349 .irq_clear = ata_bmdma_irq_clear, 350 .irq_on = ata_irq_on, 351 .irq_ack = ata_irq_ack, 352 353 .port_start = ata_port_start, 354}; 355 356static struct ata_port_operations via_port_ops_noirq = { 357 .port_disable = ata_port_disable, 358 .set_piomode = via_set_piomode, 359 .set_dmamode = via_set_dmamode, 360 .mode_filter = ata_pci_default_filter, 361 362 .tf_load = ata_tf_load, 363 .tf_read = ata_tf_read, 364 .check_status = ata_check_status, 365 .exec_command = ata_exec_command, 366 .dev_select = ata_std_dev_select, 367 368 .freeze = ata_bmdma_freeze, 369 .thaw = ata_bmdma_thaw, 370 .error_handler = via_error_handler, 371 .post_internal_cmd = ata_bmdma_post_internal_cmd, 372 .cable_detect = via_cable_detect, 373 374 .bmdma_setup = ata_bmdma_setup, 375 .bmdma_start = ata_bmdma_start, 376 .bmdma_stop = ata_bmdma_stop, 377 .bmdma_status = ata_bmdma_status, 378 379 .qc_prep = ata_qc_prep, 380 .qc_issue = ata_qc_issue_prot, 381 382 .data_xfer = ata_data_xfer_noirq, 383 384 .irq_handler = ata_interrupt, 385 .irq_clear = ata_bmdma_irq_clear, 386 .irq_on = ata_irq_on, 387 .irq_ack = ata_irq_ack, 388 389 .port_start = ata_port_start, 390}; 391 392/** 393 * via_config_fifo - set up the FIFO 394 * @pdev: PCI device 395 * @flags: configuration flags 396 * 397 * Set the FIFO properties for this device if neccessary. Used both on 398 * set up and on and the resume path 399 */ 400 401static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) 402{ 403 u8 enable; 404 405 /* 0x40 low bits indicate enabled channels */ 406 pci_read_config_byte(pdev, 0x40 , &enable); 407 enable &= 3; 408 409 if (flags & VIA_SET_FIFO) { 410 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; 411 u8 fifo; 412 413 pci_read_config_byte(pdev, 0x43, &fifo); 414 415 /* Clear PREQ# until DDACK# for errata */ 416 if (flags & VIA_BAD_PREQ) 417 fifo &= 0x7F; 418 else 419 fifo &= 0x9f; 420 /* Turn on FIFO for enabled channels */ 421 fifo |= fifo_setting[enable]; 422 pci_write_config_byte(pdev, 0x43, fifo); 423 } 424} 425 426/** 427 * via_init_one - discovery callback 428 * @pdev: PCI device 429 * @id: PCI table info 430 * 431 * A VIA IDE interface has been discovered. Figure out what revision 432 * and perform configuration work before handing it to the ATA layer 433 */ 434 435static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 436{ 437 /* Early VIA without UDMA support */ 438 static const struct ata_port_info via_mwdma_info = { 439 .sht = &via_sht, 440 .flags = ATA_FLAG_SLAVE_POSS, 441 .pio_mask = 0x1f, 442 .mwdma_mask = 0x07, 443 .port_ops = &via_port_ops 444 }; 445 /* Ditto with IRQ masking required */ 446 static const struct ata_port_info via_mwdma_info_borked = { 447 .sht = &via_sht, 448 .flags = ATA_FLAG_SLAVE_POSS, 449 .pio_mask = 0x1f, 450 .mwdma_mask = 0x07, 451 .port_ops = &via_port_ops_noirq, 452 }; 453 /* VIA UDMA 33 devices (and borked 66) */ 454 static const struct ata_port_info via_udma33_info = { 455 .sht = &via_sht, 456 .flags = ATA_FLAG_SLAVE_POSS, 457 .pio_mask = 0x1f, 458 .mwdma_mask = 0x07, 459 .udma_mask = 0x7, 460 .port_ops = &via_port_ops 461 }; 462 /* VIA UDMA 66 devices */ 463 static const struct ata_port_info via_udma66_info = { 464 .sht = &via_sht, 465 .flags = ATA_FLAG_SLAVE_POSS, 466 .pio_mask = 0x1f, 467 .mwdma_mask = 0x07, 468 .udma_mask = 0x1f, 469 .port_ops = &via_port_ops 470 }; 471 /* VIA UDMA 100 devices */ 472 static const struct ata_port_info via_udma100_info = { 473 .sht = &via_sht, 474 .flags = ATA_FLAG_SLAVE_POSS, 475 .pio_mask = 0x1f, 476 .mwdma_mask = 0x07, 477 .udma_mask = 0x3f, 478 .port_ops = &via_port_ops 479 }; 480 /* UDMA133 with bad AST (All current 133) */ 481 static const struct ata_port_info via_udma133_info = { 482 .sht = &via_sht, 483 .flags = ATA_FLAG_SLAVE_POSS, 484 .pio_mask = 0x1f, 485 .mwdma_mask = 0x07, 486 .udma_mask = 0x7f, 487 .port_ops = &via_port_ops 488 }; 489 struct ata_port_info type; 490 const struct ata_port_info *ppi[] = { &type, NULL }; 491 struct pci_dev *isa = NULL; 492 const struct via_isa_bridge *config; 493 static int printed_version; 494 u8 t; 495 u8 enable; 496 u32 timing; 497 498 if (!printed_version++) 499 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 500 501 /* To find out how the IDE will behave and what features we 502 actually have to look at the bridge not the IDE controller */ 503 for (config = via_isa_bridges; config->id; config++) 504 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 505 !!(config->flags & VIA_BAD_ID), 506 config->id, NULL))) { 507 508 pci_read_config_byte(isa, PCI_REVISION_ID, &t); 509 if (t >= config->rev_min && 510 t <= config->rev_max) 511 break; 512 pci_dev_put(isa); 513 } 514 515 if (!config->id) { 516 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n"); 517 return -ENODEV; 518 } 519 pci_dev_put(isa); 520 521 /* 0x40 low bits indicate enabled channels */ 522 pci_read_config_byte(pdev, 0x40 , &enable); 523 enable &= 3; 524 if (enable == 0) { 525 return -ENODEV; 526 } 527 528 /* Initialise the FIFO for the enabled channels. */ 529 via_config_fifo(pdev, config->flags); 530 531 /* Clock set up */ 532 switch(config->flags & VIA_UDMA) { 533 case VIA_UDMA_NONE: 534 if (config->flags & VIA_NO_UNMASK) 535 type = via_mwdma_info_borked; 536 else 537 type = via_mwdma_info; 538 break; 539 case VIA_UDMA_33: 540 type = via_udma33_info; 541 break; 542 case VIA_UDMA_66: 543 type = via_udma66_info; 544 /* The 66 MHz devices require we enable the clock */ 545 pci_read_config_dword(pdev, 0x50, &timing); 546 timing |= 0x80008; 547 pci_write_config_dword(pdev, 0x50, timing); 548 break; 549 case VIA_UDMA_100: 550 type = via_udma100_info; 551 break; 552 case VIA_UDMA_133: 553 type = via_udma133_info; 554 break; 555 default: 556 WARN_ON(1); 557 return -ENODEV; 558 } 559 560 if (config->flags & VIA_BAD_CLK66) { 561 /* Disable the 66MHz clock on problem devices */ 562 pci_read_config_dword(pdev, 0x50, &timing); 563 timing &= ~0x80008; 564 pci_write_config_dword(pdev, 0x50, timing); 565 } 566 567 /* We have established the device type, now fire it up */ 568 type.private_data = (void *)config; 569 570 return ata_pci_init_one(pdev, ppi); 571} 572 573#ifdef CONFIG_PM 574/** 575 * via_reinit_one - reinit after resume 576 * @pdev; PCI device 577 * 578 * Called when the VIA PATA device is resumed. We must then 579 * reconfigure the fifo and other setup we may have altered. In 580 * addition the kernel needs to have the resume methods on PCI 581 * quirk supported. 582 */ 583 584static int via_reinit_one(struct pci_dev *pdev) 585{ 586 u32 timing; 587 struct ata_host *host = dev_get_drvdata(&pdev->dev); 588 const struct via_isa_bridge *config = host->private_data; 589 590 via_config_fifo(pdev, config->flags); 591 592 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { 593 /* The 66 MHz devices require we enable the clock */ 594 pci_read_config_dword(pdev, 0x50, &timing); 595 timing |= 0x80008; 596 pci_write_config_dword(pdev, 0x50, timing); 597 } 598 if (config->flags & VIA_BAD_CLK66) { 599 /* Disable the 66MHz clock on problem devices */ 600 pci_read_config_dword(pdev, 0x50, &timing); 601 timing &= ~0x80008; 602 pci_write_config_dword(pdev, 0x50, timing); 603 } 604 return ata_pci_device_resume(pdev); 605} 606#endif 607 608static const struct pci_device_id via[] = { 609 { PCI_VDEVICE(VIA, 0x0571), }, 610 { PCI_VDEVICE(VIA, 0x0581), }, 611 { PCI_VDEVICE(VIA, 0x1571), }, 612 { PCI_VDEVICE(VIA, 0x3164), }, 613 { PCI_VDEVICE(VIA, 0x5324), }, 614 615 { }, 616}; 617 618static struct pci_driver via_pci_driver = { 619 .name = DRV_NAME, 620 .id_table = via, 621 .probe = via_init_one, 622 .remove = ata_pci_remove_one, 623#ifdef CONFIG_PM 624 .suspend = ata_pci_device_suspend, 625 .resume = via_reinit_one, 626#endif 627}; 628 629static int __init via_init(void) 630{ 631 return pci_register_driver(&via_pci_driver); 632} 633 634static void __exit via_exit(void) 635{ 636 pci_unregister_driver(&via_pci_driver); 637} 638 639MODULE_AUTHOR("Alan Cox"); 640MODULE_DESCRIPTION("low-level driver for VIA PATA"); 641MODULE_LICENSE("GPL"); 642MODULE_DEVICE_TABLE(pci, via); 643MODULE_VERSION(DRV_VERSION); 644 645module_init(via_init); 646module_exit(via_exit); 647