1 2/* 3 * linux/drivers/ide/pci/it821x.c Version 0.16 Jul 3 2007 4 * 5 * Copyright (C) 2004 Red Hat <alan@redhat.com> 6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 7 * 8 * May be copied or modified under the terms of the GNU General Public License 9 * Based in part on the ITE vendor provided SCSI driver. 10 * 11 * Documentation available from 12 * http://www.ite.com.tw/pc/IT8212F_V04.pdf 13 * Some other documents are NDA. 14 * 15 * The ITE8212 isn't exactly a standard IDE controller. It has two 16 * modes. In pass through mode then it is an IDE controller. In its smart 17 * mode its actually quite a capable hardware raid controller disguised 18 * as an IDE controller. Smart mode only understands DMA read/write and 19 * identify, none of the fancier commands apply. The IT8211 is identical 20 * in other respects but lacks the raid mode. 21 * 22 * Errata: 23 * o Rev 0x10 also requires master/slave hold the same DMA timings and 24 * cannot do ATAPI MWDMA. 25 * o The identify data for raid volumes lacks CHS info (technically ok) 26 * but also fails to set the LBA28 and other bits. We fix these in 27 * the IDE probe quirk code. 28 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode 29 * raid then the controller firmware dies 30 * o Smart mode without RAID doesn't clear all the necessary identify 31 * bits to reduce the command set to the one used 32 * 33 * This has a few impacts on the driver 34 * - In pass through mode we do all the work you would expect 35 * - In smart mode the clocking set up is done by the controller generally 36 * but we must watch the other limits and filter. 37 * - There are a few extra vendor commands that actually talk to the 38 * controller but only work PIO with no IRQ. 39 * 40 * Vendor areas of the identify block in smart mode are used for the 41 * timing and policy set up. Each HDD in raid mode also has a serial 42 * block on the disk. The hardware extra commands are get/set chip status, 43 * rebuild, get rebuild status. 44 * 45 * In Linux the driver supports pass through mode as if the device was 46 * just another IDE controller. If the smart mode is running then 47 * volumes are managed by the controller firmware and each IDE "disk" 48 * is a raid volume. Even more cute - the controller can do automated 49 * hotplug and rebuild. 50 * 51 * The pass through controller itself is a little demented. It has a 52 * flaw that it has a single set of PIO/MWDMA timings per channel so 53 * non UDMA devices restrict each others performance. It also has a 54 * single clock source per channel so mixed UDMA100/133 performance 55 * isn't perfect and we have to pick a clock. Thankfully none of this 56 * matters in smart mode. ATAPI DMA is not currently supported. 57 * 58 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. 59 * 60 * TODO 61 * - ATAPI UDMA is ok but not MWDMA it seems 62 * - RAID configuration ioctls 63 * - Move to libata once it grows up 64 */ 65 66#include <linux/types.h> 67#include <linux/module.h> 68#include <linux/pci.h> 69#include <linux/delay.h> 70#include <linux/hdreg.h> 71#include <linux/ide.h> 72#include <linux/init.h> 73 74#include <asm/io.h> 75 76struct it821x_dev 77{ 78 unsigned int smart:1, /* Are we in smart raid mode */ 79 timing10:1; /* Rev 0x10 */ 80 u8 clock_mode; /* 0, ATA_50 or ATA_66 */ 81 u8 want[2][2]; /* Mode/Pri log for master slave */ 82 /* We need these for switching the clock when DMA goes on/off 83 The high byte is the 66Mhz timing */ 84 u16 pio[2]; /* Cached PIO values */ 85 u16 mwdma[2]; /* Cached MWDMA values */ 86 u16 udma[2]; /* Cached UDMA values (per drive) */ 87}; 88 89#define ATA_66 0 90#define ATA_50 1 91#define ATA_ANY 2 92 93#define UDMA_OFF 0 94#define MWDMA_OFF 0 95 96/* 97 * We allow users to force the card into non raid mode without 98 * flashing the alternative BIOS. This is also neccessary right now 99 * for embedded platforms that cannot run a PC BIOS but are using this 100 * device. 101 */ 102 103static int it8212_noraid; 104 105/** 106 * it821x_program - program the PIO/MWDMA registers 107 * @drive: drive to tune 108 * @timing: timing info 109 * 110 * Program the PIO/MWDMA timing for this channel according to the 111 * current clock. 112 */ 113 114static void it821x_program(ide_drive_t *drive, u16 timing) 115{ 116 ide_hwif_t *hwif = drive->hwif; 117 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 118 int channel = hwif->channel; 119 u8 conf; 120 121 /* Program PIO/MWDMA timing bits */ 122 if(itdev->clock_mode == ATA_66) 123 conf = timing >> 8; 124 else 125 conf = timing & 0xFF; 126 pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf); 127} 128 129/** 130 * it821x_program_udma - program the UDMA registers 131 * @drive: drive to tune 132 * @timing: timing info 133 * 134 * Program the UDMA timing for this drive according to the 135 * current clock. 136 */ 137 138static void it821x_program_udma(ide_drive_t *drive, u16 timing) 139{ 140 ide_hwif_t *hwif = drive->hwif; 141 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 142 int channel = hwif->channel; 143 int unit = drive->select.b.unit; 144 u8 conf; 145 146 /* Program UDMA timing bits */ 147 if(itdev->clock_mode == ATA_66) 148 conf = timing >> 8; 149 else 150 conf = timing & 0xFF; 151 if(itdev->timing10 == 0) 152 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf); 153 else { 154 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf); 155 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf); 156 } 157} 158 159/** 160 * it821x_clock_strategy 161 * @drive: drive to set up 162 * 163 * Select between the 50 and 66Mhz base clocks to get the best 164 * results for this interface. 165 */ 166 167static void it821x_clock_strategy(ide_drive_t *drive) 168{ 169 ide_hwif_t *hwif = drive->hwif; 170 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 171 172 u8 unit = drive->select.b.unit; 173 ide_drive_t *pair = &hwif->drives[1-unit]; 174 175 int clock, altclock; 176 u8 v; 177 int sel = 0; 178 179 if(itdev->want[0][0] > itdev->want[1][0]) { 180 clock = itdev->want[0][1]; 181 altclock = itdev->want[1][1]; 182 } else { 183 clock = itdev->want[1][1]; 184 altclock = itdev->want[0][1]; 185 } 186 187 /* 188 * if both clocks can be used for the mode with the higher priority 189 * use the clock needed by the mode with the lower priority 190 */ 191 if (clock == ATA_ANY) 192 clock = altclock; 193 194 /* Nobody cares - keep the same clock */ 195 if(clock == ATA_ANY) 196 return; 197 /* No change */ 198 if(clock == itdev->clock_mode) 199 return; 200 201 /* Load this into the controller ? */ 202 if(clock == ATA_66) 203 itdev->clock_mode = ATA_66; 204 else { 205 itdev->clock_mode = ATA_50; 206 sel = 1; 207 } 208 pci_read_config_byte(hwif->pci_dev, 0x50, &v); 209 v &= ~(1 << (1 + hwif->channel)); 210 v |= sel << (1 + hwif->channel); 211 pci_write_config_byte(hwif->pci_dev, 0x50, v); 212 213 /* 214 * Reprogram the UDMA/PIO of the pair drive for the switch 215 * MWDMA will be dealt with by the dma switcher 216 */ 217 if(pair && itdev->udma[1-unit] != UDMA_OFF) { 218 it821x_program_udma(pair, itdev->udma[1-unit]); 219 it821x_program(pair, itdev->pio[1-unit]); 220 } 221 /* 222 * Reprogram the UDMA/PIO of our drive for the switch. 223 * MWDMA will be dealt with by the dma switcher 224 */ 225 if(itdev->udma[unit] != UDMA_OFF) { 226 it821x_program_udma(drive, itdev->udma[unit]); 227 it821x_program(drive, itdev->pio[unit]); 228 } 229} 230 231/** 232 * it821x_tunepio - tune a drive 233 * @drive: drive to tune 234 * @pio: the desired PIO mode 235 * 236 * Try to tune the drive/host to the desired PIO mode taking into 237 * the consideration the maximum PIO mode supported by the other 238 * device on the cable. 239 */ 240 241static int it821x_tunepio(ide_drive_t *drive, u8 set_pio) 242{ 243 ide_hwif_t *hwif = drive->hwif; 244 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 245 int unit = drive->select.b.unit; 246 ide_drive_t *pair = &hwif->drives[1 - unit]; 247 248 /* Spec says 89 ref driver uses 88 */ 249 static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; 250 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; 251 252 /* 253 * Compute the best PIO mode we can for a given device. We must 254 * pick a speed that does not cause problems with the other device 255 * on the cable. 256 */ 257 if (pair) { 258 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4, NULL); 259 /* trim PIO to the slowest of the master/slave */ 260 if (pair_pio < set_pio) 261 set_pio = pair_pio; 262 } 263 264 if (itdev->smart) 265 return 0; 266 267 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ 268 itdev->want[unit][1] = pio_want[set_pio]; 269 itdev->want[unit][0] = 1; /* PIO is lowest priority */ 270 itdev->pio[unit] = pio[set_pio]; 271 it821x_clock_strategy(drive); 272 it821x_program(drive, itdev->pio[unit]); 273 274 return ide_config_drive_speed(drive, XFER_PIO_0 + set_pio); 275} 276 277static void it821x_tuneproc(ide_drive_t *drive, u8 pio) 278{ 279 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 280 (void)it821x_tunepio(drive, pio); 281} 282 283/** 284 * it821x_tune_mwdma - tune a channel for MWDMA 285 * @drive: drive to set up 286 * @mode_wanted: the target operating mode 287 * 288 * Load the timing settings for this device mode into the 289 * controller when doing MWDMA in pass through mode. The caller 290 * must manage the whole lack of per device MWDMA/PIO timings and 291 * the shared MWDMA/PIO timing register. 292 */ 293 294static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted) 295{ 296 ide_hwif_t *hwif = drive->hwif; 297 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); 298 int unit = drive->select.b.unit; 299 int channel = hwif->channel; 300 u8 conf; 301 302 static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; 303 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; 304 305 itdev->want[unit][1] = mwdma_want[mode_wanted]; 306 itdev->want[unit][0] = 2; /* MWDMA is low priority */ 307 itdev->mwdma[unit] = dma[mode_wanted]; 308 itdev->udma[unit] = UDMA_OFF; 309 310 /* UDMA bits off - Revision 0x10 do them in pairs */ 311 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 312 if(itdev->timing10) 313 conf |= channel ? 0x60: 0x18; 314 else 315 conf |= 1 << (3 + 2 * channel + unit); 316 pci_write_config_byte(hwif->pci_dev, 0x50, conf); 317 318 it821x_clock_strategy(drive); 319 /* it821x_program(drive, itdev->mwdma[unit]); */ 320} 321 322/** 323 * it821x_tune_udma - tune a channel for UDMA 324 * @drive: drive to set up 325 * @mode_wanted: the target operating mode 326 * 327 * Load the timing settings for this device mode into the 328 * controller when doing UDMA modes in pass through. 329 */ 330 331static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted) 332{ 333 ide_hwif_t *hwif = drive->hwif; 334 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 335 int unit = drive->select.b.unit; 336 int channel = hwif->channel; 337 u8 conf; 338 339 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; 340 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; 341 342 itdev->want[unit][1] = udma_want[mode_wanted]; 343 itdev->want[unit][0] = 3; /* UDMA is high priority */ 344 itdev->mwdma[unit] = MWDMA_OFF; 345 itdev->udma[unit] = udma[mode_wanted]; 346 if(mode_wanted >= 5) 347 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ 348 349 /* UDMA on. Again revision 0x10 must do the pair */ 350 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 351 if(itdev->timing10) 352 conf &= channel ? 0x9F: 0xE7; 353 else 354 conf &= ~ (1 << (3 + 2 * channel + unit)); 355 pci_write_config_byte(hwif->pci_dev, 0x50, conf); 356 357 it821x_clock_strategy(drive); 358 it821x_program_udma(drive, itdev->udma[unit]); 359 360} 361 362 363static void it821x_dma_start(ide_drive_t *drive) 364{ 365 ide_hwif_t *hwif = drive->hwif; 366 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 367 int unit = drive->select.b.unit; 368 if(itdev->mwdma[unit] != MWDMA_OFF) 369 it821x_program(drive, itdev->mwdma[unit]); 370 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) 371 it821x_program_udma(drive, itdev->udma[unit]); 372 ide_dma_start(drive); 373} 374 375/** 376 * it821x_dma_write - DMA hook 377 * @drive: drive for DMA stop 378 * 379 * The IT821x has a single timing register for MWDMA and for PIO 380 * operations. As we flip back and forth we have to reload the 381 * clock. 382 */ 383 384static int it821x_dma_end(ide_drive_t *drive) 385{ 386 ide_hwif_t *hwif = drive->hwif; 387 int unit = drive->select.b.unit; 388 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 389 int ret = __ide_dma_end(drive); 390 if(itdev->mwdma[unit] != MWDMA_OFF) 391 it821x_program(drive, itdev->pio[unit]); 392 return ret; 393} 394 395 396/** 397 * it821x_tune_chipset - set controller timings 398 * @drive: Drive to set up 399 * @xferspeed: speed we want to achieve 400 * 401 * Tune the ITE chipset for the desired mode. If we can't achieve 402 * the desired mode then tune for a lower one, but ultimately 403 * make the thing work. 404 */ 405 406static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed) 407{ 408 409 ide_hwif_t *hwif = drive->hwif; 410 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 411 u8 speed = ide_rate_filter(drive, xferspeed); 412 413 switch (speed) { 414 case XFER_PIO_4: 415 case XFER_PIO_3: 416 case XFER_PIO_2: 417 case XFER_PIO_1: 418 case XFER_PIO_0: 419 return it821x_tunepio(drive, speed - XFER_PIO_0); 420 } 421 422 if (itdev->smart == 0) { 423 switch (speed) { 424 /* MWDMA tuning is really hard because our MWDMA and PIO 425 timings are kept in the same place. We can switch in the 426 host dma on/off callbacks */ 427 case XFER_MW_DMA_2: 428 case XFER_MW_DMA_1: 429 case XFER_MW_DMA_0: 430 it821x_tune_mwdma(drive, (speed - XFER_MW_DMA_0)); 431 break; 432 case XFER_UDMA_6: 433 case XFER_UDMA_5: 434 case XFER_UDMA_4: 435 case XFER_UDMA_3: 436 case XFER_UDMA_2: 437 case XFER_UDMA_1: 438 case XFER_UDMA_0: 439 it821x_tune_udma(drive, (speed - XFER_UDMA_0)); 440 break; 441 default: 442 return 1; 443 } 444 445 return ide_config_drive_speed(drive, speed); 446 } 447 448 /* don't touch anything in the smart mode */ 449 return 0; 450} 451 452/** 453 * it821x_configure_drive_for_dma - set up for DMA transfers 454 * @drive: drive we are going to set up 455 * 456 * Set up the drive for DMA, tune the controller and drive as 457 * required. If the drive isn't suitable for DMA or we hit 458 * other problems then we will drop down to PIO and set up 459 * PIO appropriately 460 */ 461 462static int it821x_config_drive_for_dma (ide_drive_t *drive) 463{ 464 if (ide_tune_dma(drive)) 465 return 0; 466 467 it821x_tuneproc(drive, 255); 468 469 return -1; 470} 471 472/** 473 * ata66_it821x - check for 80 pin cable 474 * @hwif: interface to check 475 * 476 * Check for the presence of an ATA66 capable cable on the 477 * interface. Problematic as it seems some cards don't have 478 * the needed logic onboard. 479 */ 480 481static unsigned int __devinit ata66_it821x(ide_hwif_t *hwif) 482{ 483 /* The reference driver also only does disk side */ 484 return 1; 485} 486 487 488static void __devinit it821x_fixups(ide_hwif_t *hwif) 489{ 490 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 491 int i; 492 493 if(!itdev->smart) { 494 /* 495 * If we are in pass through mode then not much 496 * needs to be done, but we do bother to clear the 497 * IRQ mask as we may well be in PIO (eg rev 0x10) 498 * for now and we know unmasking is safe on this chipset. 499 */ 500 for (i = 0; i < 2; i++) { 501 ide_drive_t *drive = &hwif->drives[i]; 502 if(drive->present) 503 drive->unmask = 1; 504 } 505 return; 506 } 507 /* 508 * Perform fixups on smart mode. We need to "lose" some 509 * capabilities the firmware lacks but does not filter, and 510 * also patch up some capability bits that it forgets to set 511 * in RAID mode. 512 */ 513 514 for(i = 0; i < 2; i++) { 515 ide_drive_t *drive = &hwif->drives[i]; 516 struct hd_driveid *id; 517 u16 *idbits; 518 519 if(!drive->present) 520 continue; 521 id = drive->id; 522 idbits = (u16 *)drive->id; 523 524 /* Check for RAID v native */ 525 if(strstr(id->model, "Integrated Technology Express")) { 526 /* In raid mode the ident block is slightly buggy 527 We need to set the bits so that the IDE layer knows 528 LBA28. LBA48 and DMA ar valid */ 529 id->capability |= 3; /* LBA28, DMA */ 530 id->command_set_2 |= 0x0400; /* LBA48 valid */ 531 id->cfs_enable_2 |= 0x0400; /* LBA48 on */ 532 /* Reporting logic */ 533 printk(KERN_INFO "%s: IT8212 %sRAID %d volume", 534 drive->name, 535 idbits[147] ? "Bootable ":"", 536 idbits[129]); 537 if(idbits[129] != 1) 538 printk("(%dK stripe)", idbits[146]); 539 printk(".\n"); 540 } else { 541 /* Non RAID volume. Fixups to stop the core code 542 doing unsupported things */ 543 id->field_valid &= 3; 544 id->queue_depth = 0; 545 id->command_set_1 = 0; 546 id->command_set_2 &= 0xC400; 547 id->cfsse &= 0xC000; 548 id->cfs_enable_1 = 0; 549 id->cfs_enable_2 &= 0xC400; 550 id->csf_default &= 0xC000; 551 id->word127 = 0; 552 id->dlf = 0; 553 id->csfo = 0; 554 id->cfa_power = 0; 555 printk(KERN_INFO "%s: Performing identify fixups.\n", 556 drive->name); 557 } 558 559 /* 560 * Set MWDMA0 mode as enabled/support - just to tell 561 * IDE core that DMA is supported (it821x hardware 562 * takes care of DMA mode programming). 563 */ 564 if (id->capability & 1) { 565 id->dma_mword |= 0x0101; 566 drive->current_speed = XFER_MW_DMA_0; 567 } 568 } 569 570} 571 572/** 573 * init_hwif_it821x - set up hwif structs 574 * @hwif: interface to set up 575 * 576 * We do the basic set up of the interface structure. The IT8212 577 * requires several custom handlers so we override the default 578 * ide DMA handlers appropriately 579 */ 580 581static void __devinit init_hwif_it821x(ide_hwif_t *hwif) 582{ 583 struct it821x_dev *idev = kzalloc(sizeof(struct it821x_dev), GFP_KERNEL); 584 u8 conf; 585 586 if(idev == NULL) { 587 printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n"); 588 goto fallback; 589 } 590 ide_set_hwifdata(hwif, idev); 591 592 hwif->atapi_dma = 1; 593 594 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 595 if(conf & 1) { 596 idev->smart = 1; 597 hwif->atapi_dma = 0; 598 /* Long I/O's although allowed in LBA48 space cause the 599 onboard firmware to enter the twighlight zone */ 600 hwif->rqsize = 256; 601 } 602 603 /* Pull the current clocks from 0x50 also */ 604 if (conf & (1 << (1 + hwif->channel))) 605 idev->clock_mode = ATA_50; 606 else 607 idev->clock_mode = ATA_66; 608 609 idev->want[0][1] = ATA_ANY; 610 idev->want[1][1] = ATA_ANY; 611 612 /* 613 * Not in the docs but according to the reference driver 614 * this is neccessary. 615 */ 616 617 pci_read_config_byte(hwif->pci_dev, 0x08, &conf); 618 if(conf == 0x10) { 619 idev->timing10 = 1; 620 hwif->atapi_dma = 0; 621 if(!idev->smart) 622 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n"); 623 } 624 625 hwif->speedproc = &it821x_tune_chipset; 626 hwif->tuneproc = &it821x_tuneproc; 627 628 /* MWDMA/PIO clock switching for pass through mode */ 629 if(!idev->smart) { 630 hwif->dma_start = &it821x_dma_start; 631 hwif->ide_dma_end = &it821x_dma_end; 632 } 633 634 hwif->drives[0].autotune = 1; 635 hwif->drives[1].autotune = 1; 636 637 if (!hwif->dma_base) 638 goto fallback; 639 640 hwif->ultra_mask = 0x7f; 641 hwif->mwdma_mask = 0x07; 642 643 hwif->ide_dma_check = &it821x_config_drive_for_dma; 644 if (!(hwif->udma_four)) 645 hwif->udma_four = ata66_it821x(hwif); 646 647 /* 648 * The BIOS often doesn't set up DMA on this controller 649 * so we always do it. 650 */ 651 652 hwif->autodma = 1; 653 hwif->drives[0].autodma = hwif->autodma; 654 hwif->drives[1].autodma = hwif->autodma; 655 return; 656fallback: 657 hwif->autodma = 0; 658 return; 659} 660 661static void __devinit it8212_disable_raid(struct pci_dev *dev) 662{ 663 /* Reset local CPU, and set BIOS not ready */ 664 pci_write_config_byte(dev, 0x5E, 0x01); 665 666 /* Set to bypass mode, and reset PCI bus */ 667 pci_write_config_byte(dev, 0x50, 0x00); 668 pci_write_config_word(dev, PCI_COMMAND, 669 PCI_COMMAND_PARITY | PCI_COMMAND_IO | 670 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 671 pci_write_config_word(dev, 0x40, 0xA0F3); 672 673 pci_write_config_dword(dev,0x4C, 0x02040204); 674 pci_write_config_byte(dev, 0x42, 0x36); 675 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); 676} 677 678static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name) 679{ 680 u8 conf; 681 static char *mode[2] = { "pass through", "smart" }; 682 683 /* Force the card into bypass mode if so requested */ 684 if (it8212_noraid) { 685 printk(KERN_INFO "it8212: forcing bypass mode.\n"); 686 it8212_disable_raid(dev); 687 } 688 pci_read_config_byte(dev, 0x50, &conf); 689 printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]); 690 return 0; 691} 692 693 694#define DECLARE_ITE_DEV(name_str) \ 695 { \ 696 .name = name_str, \ 697 .init_chipset = init_chipset_it821x, \ 698 .init_hwif = init_hwif_it821x, \ 699 .channels = 2, \ 700 .autodma = AUTODMA, \ 701 .bootable = ON_BOARD, \ 702 .fixup = it821x_fixups \ 703 } 704 705static ide_pci_device_t it821x_chipsets[] __devinitdata = { 706 /* 0 */ DECLARE_ITE_DEV("IT8212"), 707}; 708 709/** 710 * it821x_init_one - pci layer discovery entry 711 * @dev: PCI device 712 * @id: ident table entry 713 * 714 * Called by the PCI code when it finds an ITE821x controller. 715 * We then use the IDE PCI generic helper to do most of the work. 716 */ 717 718static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 719{ 720 ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]); 721 return 0; 722} 723 724static struct pci_device_id it821x_pci_tbl[] = { 725 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 726 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 727 { 0, }, 728}; 729 730MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); 731 732static struct pci_driver driver = { 733 .name = "ITE821x IDE", 734 .id_table = it821x_pci_tbl, 735 .probe = it821x_init_one, 736}; 737 738static int __init it821x_ide_init(void) 739{ 740 return ide_pci_register_driver(&driver); 741} 742 743module_init(it821x_ide_init); 744 745module_param_named(noraid, it8212_noraid, int, S_IRUGO); 746MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode"); 747 748MODULE_AUTHOR("Alan Cox"); 749MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); 750MODULE_LICENSE("GPL"); 751