Searched refs:membase (Results 1 - 25 of 152) sorted by relevance

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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A Dbfin_serial_5xx.h19 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25 #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A Dbfin_serial_5xx.h19 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25 #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A Dbfin_serial_5xx.h19 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25 #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/serial/
H A Dnetx-serial.c125 val = readl(port->membase + UART_CR);
126 writel(val & ~CR_TIE, port->membase + UART_CR);
132 val = readl(port->membase + UART_CR);
133 writel(val & ~CR_RIE, port->membase + UART_CR);
139 val = readl(port->membase + UART_CR);
140 writel(val | CR_MSIE, port->membase + UART_CR);
148 writel(port->x_char, port->membase + UART_DR);
162 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
168 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
177 readl(port->membase
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H A Dimx.c249 temp = readl(sport->port.membase + UCR1);
250 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
261 temp = readl(sport->port.membase + UCR2);
262 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
279 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
282 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
302 temp = readl(sport->port.membase + UCR1);
303 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
305 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
312 unsigned int val = readl(sport->port.membase
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H A Damba-pl011.c82 writew(uap->im, uap->port.membase + UART011_IMSC);
90 writew(uap->im, uap->port.membase + UART011_IMSC);
99 writew(uap->im, uap->port.membase + UART011_IMSC);
107 writew(uap->im, uap->port.membase + UART011_IMSC);
115 status = readw(uap->port.membase + UART01x_FR);
117 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
154 status = readw(uap->port.membase + UART01x_FR);
167 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
179 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
197 status = readw(uap->port.membase
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H A Duartlite.c64 ch = readb(port->membase + ULITE_RX);
109 writeb(port->x_char, port->membase + ULITE_TX);
118 writeb(xmit->buf[xmit->tail], port->membase + ULITE_TX);
135 int stat = readb(port->membase + ULITE_STATUS);
151 ret = readb(port->membase + ULITE_STATUS);
174 ulite_transmit(port, readb(port->membase + ULITE_STATUS));
204 port->membase + ULITE_CONTROL);
205 writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
212 writeb(0, port->membase + ULITE_CONTROL);
213 readb(port->membase
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H A Damba-pl010.c85 cr = readb(uap->port.membase + UART010_CR);
87 writel(cr, uap->port.membase + UART010_CR);
95 cr = readb(uap->port.membase + UART010_CR);
97 writel(cr, uap->port.membase + UART010_CR);
105 cr = readb(uap->port.membase + UART010_CR);
107 writel(cr, uap->port.membase + UART010_CR);
115 cr = readb(uap->port.membase + UART010_CR);
117 writel(cr, uap->port.membase + UART010_CR);
125 status = readb(uap->port.membase + UART01x_FR);
127 ch = readb(uap->port.membase
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H A Datmel_serial.c77 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
78 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
79 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
80 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
81 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
82 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
83 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
84 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
85 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
86 #define UART_GET_BRGR(port) __raw_readl((port)->membase
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/atm/
H A Didt77252.h354 void __iomem *membase; /* SAR's memory base address */ member in struct:idt77252_dev
440 #define SAR_REG_DR0 (card->membase + 0x00)
441 #define SAR_REG_DR1 (card->membase + 0x04)
442 #define SAR_REG_DR2 (card->membase + 0x08)
443 #define SAR_REG_DR3 (card->membase + 0x0C)
444 #define SAR_REG_CMD (card->membase + 0x10)
445 #define SAR_REG_CFG (card->membase + 0x14)
446 #define SAR_REG_STAT (card->membase + 0x18)
447 #define SAR_REG_RSQB (card->membase + 0x1C)
448 #define SAR_REG_RSQT (card->membase
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/input/keyboard/
H A Dlocomokbd.c89 static inline void locomokbd_charge_all(unsigned long membase) argument
91 locomo_writel(0x00FF, membase + LOCOMO_KSC);
94 static inline void locomokbd_activate_all(unsigned long membase) argument
98 locomo_writel(0, membase + LOCOMO_KSC);
99 r = locomo_readl(membase + LOCOMO_KIC);
101 locomo_writel(r, membase + LOCOMO_KIC);
104 static inline void locomokbd_activate_col(unsigned long membase, int col) argument
111 locomo_writel(nbset, membase + LOCOMO_KSC);
114 static inline void locomokbd_reset_col(unsigned long membase, int col) argument
119 locomo_writel(nbset, membase
134 unsigned long membase = locomokbd->base; local
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-sh/
H A Dsci.h25 void __iomem *membase; /* io cookie */ member in struct:plat_sci_port
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/isdn/hisax/
H A Dtelespci.c184 return (readisac(cs->hw.teles0.membase, offset));
190 writeisac(cs->hw.teles0.membase, offset, value);
196 read_fifo_isac(cs->hw.teles0.membase, data, size);
202 write_fifo_isac(cs->hw.teles0.membase, data, size);
208 return (readhscx(cs->hw.teles0.membase, hscx, offset));
214 writehscx(cs->hw.teles0.membase, hscx, offset, value);
221 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
222 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
223 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
224 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, n
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H A Dteles0.c102 return (readisac(cs->hw.teles0.membase, offset));
108 writeisac(cs->hw.teles0.membase, offset, value);
114 read_fifo_isac(cs->hw.teles0.membase, data, size);
120 write_fifo_isac(cs->hw.teles0.membase, data, size);
126 return (readhscx(cs->hw.teles0.membase, hscx, offset));
132 writehscx(cs->hw.teles0.membase, hscx, offset, value);
139 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
140 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
141 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
142 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, n
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-omap2/
H A Dserial.c35 .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE),
43 .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE),
51 .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE),
67 return (unsigned int)__raw_readb(up->membase + offset);
74 __raw_writeb(value, (unsigned long)(p->membase + offset));
111 p->membase = 0;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/
H A Dserial_8250.h22 void __iomem *membase; /* ioremap cookie or NULL */ member in struct:plat_serial8250_port
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-davinci/
H A Dserial.c42 return (unsigned int)__raw_readb(up->membase + offset);
49 __raw_writeb(value, p->membase + offset);
54 .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE),
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/isdn/hardware/avm/
H A Dt1pci.c73 card->membase = p->membase;
83 card->mbase = ioremap(card->membase, 64);
86 card->membase);
134 card->port, card->irq, card->membase);
183 cinfo->card ? cinfo->card->membase : 0
204 param.membase = pci_resource_start(dev, 0);
207 param.port, param.irq, param.membase);
212 param.port, param.irq, param.membase);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/kernel/
H A Disa.c25 .procname = "membase",
68 register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) argument
70 isa_membase = membase;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/serial/jsm/
H A Djsm_driver.c99 brd->membase = pci_resource_start(pdev, 0);
102 if (brd->membase & 1)
103 brd->membase &= ~3;
105 brd->membase &= ~15;
113 brd->re_map_membase = ioremap(brd->membase, 0x1000);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/mips/emma2rh/markeins/
H A Dplatform.c114 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
121 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
128 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dcpci405.c82 port.membase = (void*)UART0_IO_BASE;
85 port.membase = (void*)UART1_IO_BASE;
98 port.membase = (void*)UART1_IO_BASE;
101 port.membase = (void*)UART0_IO_BASE;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/
H A Ddigi1.h97 unsigned char *membase; /* DPR Address */ member in struct:digi_info
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-h720x/
H A Dcpu-h7202.c51 .membase = (void*)SERIAL0_VIRT,
60 .membase = (void*)SERIAL1_VIRT,
70 .membase = (void*)SERIAL2_VIRT,
79 .membase = (void*)SERIAL3_VIRT,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-ns9xxx/
H A Dboard-a9m9750dev.c114 .membase = (unsigned char*)FPGA_UARTA_BASE,
123 .membase = (unsigned char*)FPGA_UARTB_BASE,
132 .membase = (unsigned char*)FPGA_UARTC_BASE,
141 .membase = (unsigned char*)FPGA_UARTD_BASE,

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