Lines Matching refs:membase
125 val = readl(port->membase + UART_CR);
126 writel(val & ~CR_TIE, port->membase + UART_CR);
132 val = readl(port->membase + UART_CR);
133 writel(val & ~CR_RIE, port->membase + UART_CR);
139 val = readl(port->membase + UART_CR);
140 writel(val | CR_MSIE, port->membase + UART_CR);
148 writel(port->x_char, port->membase + UART_DR);
162 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
168 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
177 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
179 if (!(readl(port->membase + UART_FR) & FR_TXFF))
185 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
208 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
209 rx = readl(port->membase + UART_DR);
212 status = readl(port->membase + UART_SR);
214 writel(0, port->membase + UART_SR);
256 status = readl(port->membase + UART_IIR) & IIR_MASK;
263 if (readl(port->membase + UART_FR) & FR_CTS)
268 writel(0, port->membase + UART_IIR);
269 status = readl(port->membase + UART_IIR) & IIR_MASK;
280 if (readl(port->membase + UART_FR) & FR_CTS)
291 val = readl(port->membase + UART_RTS_CR);
292 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
301 line_cr = readl(port->membase + UART_LINE_CR);
306 writel(line_cr, port->membase + UART_LINE_CR);
322 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
323 port->membase + UART_LINE_CR);
326 port->membase + UART_CR);
334 writel(0, port->membase + UART_CR) ;
385 old_cr = readl(port->membase + UART_CR);
389 port->membase + UART_CR);
392 while (readl(port->membase + UART_FR) & FR_BUSY);
395 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
402 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
403 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
404 writel(line_cr, port->membase + UART_LINE_CR);
406 writel(rts_cr, port->membase + UART_RTS_CR);
430 writel(old_cr, port->membase + UART_CR);
492 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
505 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
518 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
532 while (readl(port->membase + UART_FR) & FR_BUSY);
533 writel(ch, port->membase + UART_DR);
542 cr_save = readl(port->membase + UART_CR);
543 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
547 while (readl(port->membase + UART_FR) & FR_BUSY);
548 writel(cr_save, port->membase + UART_CR);
557 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
558 readl(port->membase + UART_BAUDDIV_LSB);
565 line_cr = readl(port->membase + UART_LINE_CR);
589 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
617 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
688 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);