Searched refs:mcr (Results 1 - 25 of 152) sorted by relevance

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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sh/drivers/pci/
H A Dfixups-lboxre2.c19 unsigned long bcr1, mcr; local
31 mcr = inl(SH7751_MCR);
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
33 pci_write_reg(mcr, SH4_PCIMCR);
H A Dfixups-rts7751r2d.c20 unsigned long bcr1, mcr; local
33 mcr = inl(SH7751_MCR);
34 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
35 pci_write_reg(mcr, SH4_PCIMCR);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mm/
H A Dproc-arm940.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
101 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
105 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
154 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
159 mcr p1
[all...]
H A Dcache-v6.S33 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
34 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
36 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
98 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
105 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
108 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
124 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
126 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
133 mcr p1
[all...]
H A Dtlb-v6.S38 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
47 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
56 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
85 mcr p1
[all...]
H A Dproc-arm920.S83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
140 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
166 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
201 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p1
[all...]
H A Dproc-arm922.S85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
142 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
203 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
204 mcr p1
[all...]
H A Dproc-arm1020e.S89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
177 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
216 mcr p1
[all...]
H A Dproc-arm1020.S89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
148 mcr p15, 0, ip, c7, c10, 4 @ drain WB
178 mcr p1
[all...]
H A Dproc-arm925.S53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c7, c10, 4 @ drain WB
78 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
97 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
99 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
121 mcr p1
[all...]
H A Dproc-arm946.S53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
69 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
96 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
100 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
130 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
133 mcr p1
[all...]
H A Dproc-arm1022.S78 mcr p15, 0, r0, c1, c0, 0 @ disable caches
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
135 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
165 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
205 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
208 mcr p1
[all...]
H A Dproc-arm1026.S78 mcr p15, 0, r0, c1, c0, 0 @ disable caches
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
199 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcr p1
[all...]
H A Dproc-arm740.S45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
56 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
69 mcr p15, 0, r0, c6, c3 @ disable area 3~7
70 mcr p15, 0, r0, c6, c4
71 mcr p15, 0, r0, c6, c5
72 mcr p15, 0, r0, c6, c6
73 mcr p1
[all...]
H A Dproc-v6.S52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
108 mcr p15, 0, r1, c13, c0, 1 @ set context ID
160 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
201 mcr p15, 0, r0, c1, c0, 1
206 mcr p1
[all...]
H A Dproc-arm926.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
87 mcr p15, 0, ip, c7, c10, 4 @ drain WB
89 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
108 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
132 mcr p1
[all...]
H A Dtlb-v4wb.S38 mcr p15, 0, r3, c7, c10, 4 @ drain WB
43 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
60 mcr p15, 0, r3, c7, c10, 4 @ drain WB
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dtlb-v4wbi.S37 mcr p15, 0, r3, c7, c10, 4 @ drain WB
43 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
51 mcr p15, 0, r3, c7, c10, 4 @ drain WB
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dproc-sa1100.S44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
62 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
66 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
82 mcr p15, 0, ip, c7, c10, 4 @ drain WB
84 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
89 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
116 mcr p1
[all...]
H A Dproc-sa110.S40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
52 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
56 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
72 mcr p15, 0, ip, c7, c10, 4 @ drain WB
74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
79 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
96 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
102 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
106 mcr p1
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/openssl-0.9.8e/test/
H A Dtests.com70 $ mcr 'texe_dir''evptest' evptests.txt
73 $ mcr 'texe_dir''destest'
76 $ mcr 'texe_dir''ideatest'
79 $ mcr 'texe_dir''shatest'
80 $ mcr 'texe_dir''sha1test'
83 $ mcr 'texe_dir''mdc2test'
86 $ mcr 'texe_dir''md5test'
89 $ mcr 'texe_dir''md4test'
92 $ mcr 'texe_dir''hmactest'
95 $ mcr 'texe_di
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/openssl/test/
H A Dtests.com67 $ mcr 'texe_dir''evptest' evptests.txt
70 $ mcr 'texe_dir''destest'
73 $ mcr 'texe_dir''ideatest'
76 $ mcr 'texe_dir''shatest'
77 $ mcr 'texe_dir''sha1test'
80 $ mcr 'texe_dir''mdc2test'
83 $ mcr 'texe_dir''md5test'
86 $ mcr 'texe_dir''md4test'
89 $ mcr 'texe_dir''hmactest'
92 $ mcr 'texe_di
[all...]
H A Dtestgen.com26 $ mcr 'exe_dir'openssl no-rsa
40 $ mcr 'exe_dir'openssl req -config test.cnf 'req_new' -out testreq.pem
47 $ mcr 'exe_dir'openssl req -config test.cnf -verify -in testreq.pem -noout
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/boot/compressed/
H A Dbig-endian.S12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sh/kernel/
H A Dpm.c34 u16 frqcr, mcr; local
57 mcr = ctrl_inw(MCR);
58 ctrl_outw(mcr & ~MCR_RFSH, MCR);
69 ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR);

Completed in 178 milliseconds

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