Lines Matching refs:mcr
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
56 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
69 mcr p15, 0, r0, c6, c3 @ disable area 3~7
70 mcr p15, 0, r0, c6, c4
71 mcr p15, 0, r0, c6, c5
72 mcr p15, 0, r0, c6, c6
73 mcr p15, 0, r0, c6, c7
76 mcr p15, 0, r0, c6, c0 @ set area 0, default
86 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
96 mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
99 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
105 mcr p15, 0, r0, c3, c0
109 mcr p15, 0, r0, c5, c0 @ all read/write access