Lines Matching refs:mcr
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c7, c10, 4 @ drain WB
78 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
97 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
99 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
121 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
125 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
151 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
154 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
158 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
161 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
196 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
197 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 mcr p15, 0, r0, c7, c10, 4 @ drain WB
214 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
244 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
248 mcr p15, 0, r0, c7, c10, 4 @ drain WB
264 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
269 mcr p15, 0, r0, c7, c10, 4 @ drain WB
284 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
286 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
291 mcr p15, 0, r0, c7, c10, 4 @ drain WB
307 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
312 mcr p15, 0, r0, c7, c10, 4 @ drain WB
329 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
333 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
337 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
338 mcr p15, 0, ip, c7, c10, 4 @ drain WB
339 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
340 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379 mcr p15, 0, r0, c7, c10, 4 @ drain WB
394 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
398 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
400 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
405 mcr p15, 7, r0, c15, c0, 0