Searched refs:clock_type (Results 1 - 17 of 17) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/hdlc/
H A Dioctl.h39 unsigned int clock_type; /* internal, external, TX-internal etc. */ member in struct:__anon9828
45 unsigned int clock_type; /* internal, external, TX-internal etc. */ member in struct:__anon9829
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-ppc/
H A Dtodc.h440 #define TODC_INIT(clock_type, as0, as1, data, bits) { \
441 todc_info->rtc_type = clock_type; \
449 todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
450 todc_info->sw_flags = clock_type ##_SW_FLAGS; \
452 todc_info->year = clock_type ##_YEAR; \
453 todc_info->month = clock_type ##_MONTH; \
454 todc_info->day_of_month = clock_type ##_DOM; \
455 todc_info->day_of_week = clock_type ##_DOW; \
456 todc_info->hours = clock_type ##_HOURS; \
457 todc_info->minutes = clock_type ##_MINUTE
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/wan/
H A Dc101.c155 switch(port->settings.clock_type) {
262 if (new_line.clock_type != CLOCK_EXT &&
263 new_line.clock_type != CLOCK_TXFROMRX &&
264 new_line.clock_type != CLOCK_INT &&
265 new_line.clock_type != CLOCK_TXINT)
377 card->settings.clock_type = CLOCK_EXT;
H A Dpci200syn.c142 switch(port->settings.clock_type) {
234 if (new_line.clock_type != CLOCK_EXT &&
235 new_line.clock_type != CLOCK_TXFROMRX &&
236 new_line.clock_type != CLOCK_INT &&
237 new_line.clock_type != CLOCK_TXINT)
431 port->settings.clock_type = CLOCK_EXT;
H A Dn2.c176 switch(port->settings.clock_type) {
283 if (new_line.clock_type != CLOCK_EXT &&
284 new_line.clock_type != CLOCK_TXFROMRX &&
285 new_line.clock_type != CLOCK_INT &&
286 new_line.clock_type != CLOCK_TXINT)
473 port->settings.clock_type = CLOCK_EXT;
H A Dpc300too.c144 switch(port->settings.clock_type) {
260 if (new_line.clock_type != CLOCK_EXT &&
261 new_line.clock_type != CLOCK_TXFROMRX &&
262 new_line.clock_type != CLOCK_INT &&
263 new_line.clock_type != CLOCK_TXINT)
483 port->settings.clock_type = CLOCK_EXT;
H A Dwanxl.c59 unsigned int clock_type; member in struct:__anon5982
360 line.clock_type = get_status(port)->clocking;
378 if (line.clock_type != CLOCK_EXT &&
379 line.clock_type != CLOCK_TXFROMRX)
385 get_status(port)->clocking = line.clock_type;
H A Dfarsync.c1954 switch (sync.clock_type) {
2012 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
H A Dpc300_drv.c619 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
783 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
2656 uclong clktype = chan->conf.phys_settings.clock_type;
3130 chan->conf.phys_settings.clock_type = CLOCK_EXT;
H A Ddscc4.c954 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/sound/pci/pcxhr/
H A Dpcxhr.h187 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate);
H A Dpcxhr.c291 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, argument
298 switch (clock_type) {
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/
H A Dsm501fb.c365 unsigned int clock_type; local
375 clock_type = SM501_CLOCK_V2XCLK;
381 clock_type = SM501_CLOCK_P2XCLK;
388 clock_type = 0;
431 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/pcmcia/
H A Dsynclink_cs.c4322 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4323 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4324 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4325 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4326 default: new_line.clock_type = CLOCK_DEFAULT;
4343 switch (new_line.clock_type)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/
H A Dsynclink_gt.c1687 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1688 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1689 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1690 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1691 default: new_line.clock_type = CLOCK_DEFAULT;
1708 switch (new_line.clock_type)
H A Dsynclink.c7909 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7910 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7911 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7912 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7913 default: new_line.clock_type = CLOCK_DEFAULT;
7930 switch (new_line.clock_type)
H A Dsynclinkmp.c1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1837 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1838 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1840 default: new_line.clock_type = CLOCK_DEFAULT;
1857 switch (new_line.clock_type)

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