1/* 2 * Cyclades PC300 synchronous serial card driver for Linux 3 * 4 * Copyright (C) 2000-2007 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>. 11 * 12 * Sources of information: 13 * Hitachi HD64572 SCA-II User's Manual 14 * Cyclades PC300 Linux driver 15 * 16 * This driver currently supports only PC300/RSV (V.24/V.35) and 17 * PC300/X21 cards. 18 */ 19 20#include <linux/module.h> 21#include <linux/kernel.h> 22#include <linux/slab.h> 23#include <linux/sched.h> 24#include <linux/types.h> 25#include <linux/fcntl.h> 26#include <linux/in.h> 27#include <linux/string.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/ioport.h> 31#include <linux/moduleparam.h> 32#include <linux/netdevice.h> 33#include <linux/hdlc.h> 34#include <linux/pci.h> 35#include <linux/delay.h> 36#include <asm/io.h> 37 38#include "hd64572.h" 39 40static const char* version = "Cyclades PC300 driver version: 1.17"; 41static const char* devname = "PC300"; 42 43#undef DEBUG_PKT 44#define DEBUG_RINGS 45 46#define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */ 47#define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */ 48#define ALL_PAGES_ALWAYS_MAPPED 49#define NEED_DETECT_RAM 50#define NEED_SCA_MSCI_INTR 51#define MAX_TX_BUFFERS 10 52 53static int pci_clock_freq = 33000000; 54static int use_crystal_clock = 0; 55static unsigned int CLOCK_BASE; 56 57/* Masks to access the init_ctrl PLX register */ 58#define PC300_CLKSEL_MASK (0x00000004UL) 59#define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3)) 60#define PC300_CTYPE_MASK (0x00000800UL) 61 62 63enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */ 64 65/* 66 * PLX PCI9050-1 local configuration and shared runtime registers. 67 * This structure can be used to access 9050 registers (memory mapped). 68 */ 69typedef struct { 70 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 71 u32 loc_rom_range; /* 10h : Local ROM Range */ 72 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 73 u32 loc_rom_base; /* 24h : Local ROM Base */ 74 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 75 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ 76 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 77 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 78 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 79}plx9050; 80 81 82 83typedef struct port_s { 84 struct net_device *dev; 85 struct card_s *card; 86 spinlock_t lock; /* TX lock */ 87 sync_serial_settings settings; 88 int rxpart; /* partial frame received, next frame invalid*/ 89 unsigned short encoding; 90 unsigned short parity; 91 unsigned int iface; 92 u16 rxin; /* rx ring buffer 'in' pointer */ 93 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 94 u16 txlast; 95 u8 rxs, txs, tmc; /* SCA registers */ 96 u8 phy_node; /* physical port # - 0 or 1 */ 97}port_t; 98 99 100 101typedef struct card_s { 102 int type; /* RSV, X21, etc. */ 103 int n_ports; /* 1 or 2 ports */ 104 u8 __iomem *rambase; /* buffer memory base (virtual) */ 105 u8 __iomem *scabase; /* SCA memory base (virtual) */ 106 plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */ 107 u32 init_ctrl_value; 108 u16 rx_ring_buffers; /* number of buffers in a ring */ 109 u16 tx_ring_buffers; 110 u16 buff_offset; /* offset of first buffer of first channel */ 111 u8 irq; /* interrupt request level */ 112 113 port_t ports[2]; 114}card_t; 115 116 117#define sca_in(reg, card) readb(card->scabase + (reg)) 118#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) 119#define sca_inw(reg, card) readw(card->scabase + (reg)) 120#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) 121#define sca_inl(reg, card) readl(card->scabase + (reg)) 122#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) 123 124#define port_to_card(port) (port->card) 125#define log_node(port) (port->phy_node) 126#define phy_node(port) (port->phy_node) 127#define winbase(card) (card->rambase) 128#define get_port(card, port) ((port) < (card)->n_ports ? \ 129 (&(card)->ports[port]) : (NULL)) 130 131#include "hd6457x.c" 132 133 134static void pc300_set_iface(port_t *port) 135{ 136 card_t *card = port->card; 137 u32 __iomem * init_ctrl = &card->plxbase->init_ctrl; 138 u16 msci = get_msci(port); 139 u8 rxs = port->rxs & CLK_BRG_MASK; 140 u8 txs = port->txs & CLK_BRG_MASK; 141 142 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, 143 port_to_card(port)); 144 switch(port->settings.clock_type) { 145 case CLOCK_INT: 146 rxs |= CLK_BRG; /* BRG output */ 147 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 148 break; 149 150 case CLOCK_TXINT: 151 rxs |= CLK_LINE; /* RXC input */ 152 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ 153 break; 154 155 case CLOCK_TXFROMRX: 156 rxs |= CLK_LINE; /* RXC input */ 157 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 158 break; 159 160 default: /* EXTernal clock */ 161 rxs |= CLK_LINE; /* RXC input */ 162 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ 163 break; 164 } 165 166 port->rxs = rxs; 167 port->txs = txs; 168 sca_out(rxs, msci + RXS, card); 169 sca_out(txs, msci + TXS, card); 170 sca_set_port(port); 171 172 if (port->card->type == PC300_RSV) { 173 if (port->iface == IF_IFACE_V35) 174 writel(card->init_ctrl_value | 175 PC300_CHMEDIA_MASK(port->phy_node), init_ctrl); 176 else 177 writel(card->init_ctrl_value & 178 ~PC300_CHMEDIA_MASK(port->phy_node), init_ctrl); 179 } 180} 181 182 183 184static int pc300_open(struct net_device *dev) 185{ 186 port_t *port = dev_to_port(dev); 187 188 int result = hdlc_open(dev); 189 if (result) 190 return result; 191 192 sca_open(dev); 193 pc300_set_iface(port); 194 return 0; 195} 196 197 198 199static int pc300_close(struct net_device *dev) 200{ 201 sca_close(dev); 202 hdlc_close(dev); 203 return 0; 204} 205 206 207 208static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 209{ 210 const size_t size = sizeof(sync_serial_settings); 211 sync_serial_settings new_line; 212 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 213 int new_type; 214 port_t *port = dev_to_port(dev); 215 216#ifdef DEBUG_RINGS 217 if (cmd == SIOCDEVPRIVATE) { 218 sca_dump_rings(dev); 219 return 0; 220 } 221#endif 222 if (cmd != SIOCWANDEV) 223 return hdlc_ioctl(dev, ifr, cmd); 224 225 if (ifr->ifr_settings.type == IF_GET_IFACE) { 226 ifr->ifr_settings.type = port->iface; 227 if (ifr->ifr_settings.size < size) { 228 ifr->ifr_settings.size = size; /* data size wanted */ 229 return -ENOBUFS; 230 } 231 if (copy_to_user(line, &port->settings, size)) 232 return -EFAULT; 233 return 0; 234 235 } 236 237 if (port->card->type == PC300_X21 && 238 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || 239 ifr->ifr_settings.type == IF_IFACE_X21)) 240 new_type = IF_IFACE_X21; 241 242 else if (port->card->type == PC300_RSV && 243 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || 244 ifr->ifr_settings.type == IF_IFACE_V35)) 245 new_type = IF_IFACE_V35; 246 247 else if (port->card->type == PC300_RSV && 248 ifr->ifr_settings.type == IF_IFACE_V24) 249 new_type = IF_IFACE_V24; 250 251 else 252 return hdlc_ioctl(dev, ifr, cmd); 253 254 if (!capable(CAP_NET_ADMIN)) 255 return -EPERM; 256 257 if (copy_from_user(&new_line, line, size)) 258 return -EFAULT; 259 260 if (new_line.clock_type != CLOCK_EXT && 261 new_line.clock_type != CLOCK_TXFROMRX && 262 new_line.clock_type != CLOCK_INT && 263 new_line.clock_type != CLOCK_TXINT) 264 return -EINVAL; /* No such clock setting */ 265 266 if (new_line.loopback != 0 && new_line.loopback != 1) 267 return -EINVAL; 268 269 memcpy(&port->settings, &new_line, size); /* Update settings */ 270 port->iface = new_type; 271 pc300_set_iface(port); 272 return 0; 273} 274 275 276 277static void pc300_pci_remove_one(struct pci_dev *pdev) 278{ 279 int i; 280 card_t *card = pci_get_drvdata(pdev); 281 282 for (i = 0; i < 2; i++) 283 if (card->ports[i].card) { 284 struct net_device *dev = port_to_dev(&card->ports[i]); 285 unregister_hdlc_device(dev); 286 } 287 288 if (card->irq) 289 free_irq(card->irq, card); 290 291 if (card->rambase) 292 iounmap(card->rambase); 293 if (card->scabase) 294 iounmap(card->scabase); 295 if (card->plxbase) 296 iounmap(card->plxbase); 297 298 pci_release_regions(pdev); 299 pci_disable_device(pdev); 300 pci_set_drvdata(pdev, NULL); 301 if (card->ports[0].dev) 302 free_netdev(card->ports[0].dev); 303 if (card->ports[1].dev) 304 free_netdev(card->ports[1].dev); 305 kfree(card); 306} 307 308 309 310static int __devinit pc300_pci_init_one(struct pci_dev *pdev, 311 const struct pci_device_id *ent) 312{ 313 card_t *card; 314 u8 rev_id; 315 u32 __iomem *p; 316 int i; 317 u32 ramsize; 318 u32 ramphys; /* buffer memory base */ 319 u32 scaphys; /* SCA memory base */ 320 u32 plxphys; /* PLX registers memory base */ 321 322#ifndef MODULE 323 static int printed_version; 324 if (!printed_version++) 325 printk(KERN_INFO "%s\n", version); 326#endif 327 328 i = pci_enable_device(pdev); 329 if (i) 330 return i; 331 332 i = pci_request_regions(pdev, "PC300"); 333 if (i) { 334 pci_disable_device(pdev); 335 return i; 336 } 337 338 card = kmalloc(sizeof(card_t), GFP_KERNEL); 339 if (card == NULL) { 340 printk(KERN_ERR "pc300: unable to allocate memory\n"); 341 pci_release_regions(pdev); 342 pci_disable_device(pdev); 343 return -ENOBUFS; 344 } 345 memset(card, 0, sizeof(card_t)); 346 pci_set_drvdata(pdev, card); 347 348 if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 || 349 pdev->device == PCI_DEVICE_ID_PC300_TE_2) 350 card->type = PC300_TE; /* not fully supported */ 351 else if (card->init_ctrl_value & PC300_CTYPE_MASK) 352 card->type = PC300_X21; 353 else 354 card->type = PC300_RSV; 355 356 if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 || 357 pdev->device == PCI_DEVICE_ID_PC300_TE_1) 358 card->n_ports = 1; 359 else 360 card->n_ports = 2; 361 362 for (i = 0; i < card->n_ports; i++) 363 if (!(card->ports[i].dev = alloc_hdlcdev(&card->ports[i]))) { 364 printk(KERN_ERR "pc300: unable to allocate memory\n"); 365 pc300_pci_remove_one(pdev); 366 return -ENOMEM; 367 } 368 369 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 370 if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE || 371 pci_resource_len(pdev, 2) != PC300_SCA_SIZE || 372 pci_resource_len(pdev, 3) < 16384) { 373 printk(KERN_ERR "pc300: invalid card EEPROM parameters\n"); 374 pc300_pci_remove_one(pdev); 375 return -EFAULT; 376 } 377 378 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK; 379 card->plxbase = ioremap(plxphys, PC300_PLX_SIZE); 380 381 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK; 382 card->scabase = ioremap(scaphys, PC300_SCA_SIZE); 383 384 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK; 385 card->rambase = ioremap(ramphys, pci_resource_len(pdev,3)); 386 387 if (card->plxbase == NULL || 388 card->scabase == NULL || 389 card->rambase == NULL) { 390 printk(KERN_ERR "pc300: ioremap() failed\n"); 391 pc300_pci_remove_one(pdev); 392 } 393 394 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys); 395 card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl); 396 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys); 397 398 /* Reset PLX */ 399 p = &card->plxbase->init_ctrl; 400 writel(card->init_ctrl_value | 0x40000000, p); 401 readl(p); /* Flush the write - do not use sca_flush */ 402 udelay(1); 403 404 writel(card->init_ctrl_value, p); 405 readl(p); /* Flush the write - do not use sca_flush */ 406 udelay(1); 407 408 /* Reload Config. Registers from EEPROM */ 409 writel(card->init_ctrl_value | 0x20000000, p); 410 readl(p); /* Flush the write - do not use sca_flush */ 411 udelay(1); 412 413 writel(card->init_ctrl_value, p); 414 readl(p); /* Flush the write - do not use sca_flush */ 415 udelay(1); 416 417 ramsize = sca_detect_ram(card, card->rambase, 418 pci_resource_len(pdev, 3)); 419 420 if (use_crystal_clock) 421 card->init_ctrl_value &= ~PC300_CLKSEL_MASK; 422 else 423 card->init_ctrl_value |= PC300_CLKSEL_MASK; 424 425 writel(card->init_ctrl_value, &card->plxbase->init_ctrl); 426 /* number of TX + RX buffers for one port */ 427 i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU)); 428 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); 429 card->rx_ring_buffers = i - card->tx_ring_buffers; 430 431 card->buff_offset = card->n_ports * sizeof(pkt_desc) * 432 (card->tx_ring_buffers + card->rx_ring_buffers); 433 434 printk(KERN_INFO "pc300: PC300/%s, %u KB RAM at 0x%x, IRQ%u, " 435 "using %u TX + %u RX packets rings\n", 436 card->type == PC300_X21 ? "X21" : 437 card->type == PC300_TE ? "TE" : "RSV", 438 ramsize / 1024, ramphys, pdev->irq, 439 card->tx_ring_buffers, card->rx_ring_buffers); 440 441 if (card->tx_ring_buffers < 1) { 442 printk(KERN_ERR "pc300: RAM test failed\n"); 443 pc300_pci_remove_one(pdev); 444 return -EFAULT; 445 } 446 447 /* Enable interrupts on the PCI bridge, LINTi1 active low */ 448 writew(0x0041, &card->plxbase->intr_ctrl_stat); 449 450 /* Allocate IRQ */ 451 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, devname, card)) { 452 printk(KERN_WARNING "pc300: could not allocate IRQ%d.\n", 453 pdev->irq); 454 pc300_pci_remove_one(pdev); 455 return -EBUSY; 456 } 457 card->irq = pdev->irq; 458 459 sca_init(card, 0); 460 461 // COTE not set - allows better TX DMA settings 462 // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card); 463 464 sca_out(0x10, BTCR, card); 465 466 for (i = 0; i < card->n_ports; i++) { 467 port_t *port = &card->ports[i]; 468 struct net_device *dev = port_to_dev(port); 469 hdlc_device *hdlc = dev_to_hdlc(dev); 470 port->phy_node = i; 471 472 spin_lock_init(&port->lock); 473 SET_MODULE_OWNER(dev); 474 dev->irq = card->irq; 475 dev->mem_start = ramphys; 476 dev->mem_end = ramphys + ramsize - 1; 477 dev->tx_queue_len = 50; 478 dev->do_ioctl = pc300_ioctl; 479 dev->open = pc300_open; 480 dev->stop = pc300_close; 481 hdlc->attach = sca_attach; 482 hdlc->xmit = sca_xmit; 483 port->settings.clock_type = CLOCK_EXT; 484 port->card = card; 485 if (card->type == PC300_X21) 486 port->iface = IF_IFACE_X21; 487 else 488 port->iface = IF_IFACE_V35; 489 490 if (register_hdlc_device(dev)) { 491 printk(KERN_ERR "pc300: unable to register hdlc " 492 "device\n"); 493 port->card = NULL; 494 pc300_pci_remove_one(pdev); 495 return -ENOBUFS; 496 } 497 sca_init_sync_port(port); /* Set up SCA memory */ 498 499 printk(KERN_INFO "%s: PC300 node %d\n", 500 dev->name, port->phy_node); 501 } 502 return 0; 503} 504 505 506 507static struct pci_device_id pc300_pci_tbl[] __devinitdata = { 508 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID, 509 PCI_ANY_ID, 0, 0, 0 }, 510 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID, 511 PCI_ANY_ID, 0, 0, 0 }, 512 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID, 513 PCI_ANY_ID, 0, 0, 0 }, 514 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID, 515 PCI_ANY_ID, 0, 0, 0 }, 516 { 0, } 517}; 518 519 520static struct pci_driver pc300_pci_driver = { 521 .name = "PC300", 522 .id_table = pc300_pci_tbl, 523 .probe = pc300_pci_init_one, 524 .remove = pc300_pci_remove_one, 525}; 526 527 528static int __init pc300_init_module(void) 529{ 530#ifdef MODULE 531 printk(KERN_INFO "%s\n", version); 532#endif 533 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { 534 printk(KERN_ERR "pc300: Invalid PCI clock frequency\n"); 535 return -EINVAL; 536 } 537 if (use_crystal_clock != 0 && use_crystal_clock != 1) { 538 printk(KERN_ERR "pc300: Invalid 'use_crystal_clock' value\n"); 539 return -EINVAL; 540 } 541 542 CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq; 543 544 return pci_register_driver(&pc300_pci_driver); 545} 546 547 548 549static void __exit pc300_cleanup_module(void) 550{ 551 pci_unregister_driver(&pc300_pci_driver); 552} 553 554MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 555MODULE_DESCRIPTION("Cyclades PC300 serial port driver"); 556MODULE_LICENSE("GPL v2"); 557MODULE_DEVICE_TABLE(pci, pc300_pci_tbl); 558module_param(pci_clock_freq, int, 0444); 559MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); 560module_param(use_crystal_clock, int, 0444); 561MODULE_PARM_DESC(use_crystal_clock, 562 "Use 24.576 MHz clock instead of PCI clock"); 563module_init(pc300_init_module); 564module_exit(pc300_cleanup_module); 565