Searched refs:RS (Results 1 - 21 of 21) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/xmon/
H A Dppc-opc.c415 the RS field in the instruction. This is used for extended
420 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
423 #define RS RBS + 1
424 #define RT RS
428 /* The RS field of the DS form stq instruction, which has special
430 #define RSQ RS + 1
438 /* The RS field of the tlbwe instruction, which is optional. */
1355 the RS field in the instruction. This is used for extended
1393 /* The RS field of the DS form stq instruction, which has special
2077 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, R
421 #define RS macro
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/macintosh/
H A Dvia-macii.c43 #define RS 0x200 /* skip between registers */ macro
45 #define A RS /* A-side data */
46 #define DIRB (2*RS) /* B-side direction (1=output) */
47 #define DIRA (3*RS) /* A-side direction (1=output) */
48 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
49 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
50 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
51 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
52 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
53 #define T2CH (9*RS) /* Time
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H A Dvia-cuda.c37 #define RS 0x200 /* skip between registers */ macro
39 #define A RS /* A-side data */
40 #define DIRB (2*RS) /* B-side direction (1=output) */
41 #define DIRA (3*RS) /* A-side direction (1=output) */
42 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
43 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
44 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
45 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
46 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
47 #define T2CH (9*RS) /* Time
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H A Dvia-pmu68k.c50 #define RS 0x200 /* skip between registers */ macro
52 #define A RS /* A-side data */
53 #define DIRB (2*RS) /* B-side direction (1=output) */
54 #define DIRA (3*RS) /* A-side direction (1=output) */
55 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
56 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
57 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
58 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
59 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
60 #define T2CH (9*RS) /* Time
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H A Dvia-maciisi.c33 #define RS 0x200 /* skip between registers */ macro
35 #define A RS /* A-side data */
36 #define DIRB (2*RS) /* B-side direction (1=output) */
37 #define DIRA (3*RS) /* A-side direction (1=output) */
38 #define SR (10*RS) /* Shift register */
39 #define ACR (11*RS) /* Auxiliary control register */
40 #define IFR (13*RS) /* Interrupt flag register */
41 #define IER (14*RS) /* Interrupt enable register */
H A Dvia-pmu.c81 #define RS 0x200 /* skip between registers */ macro
83 #define A RS /* A-side data */
84 #define DIRB (2*RS) /* B-side direction (1=output) */
85 #define DIRA (3*RS) /* A-side direction (1=output) */
86 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
87 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
88 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
89 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
90 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
91 #define T2CH (9*RS) /* Time
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/xmon/
H A Dppc-opc.c315 the RS field in the instruction. This is used for extended
320 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
323 #define RS (46)
324 #define RT (RS)
795 the RS field in the instruction. This is used for extended
1803 { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1804 { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1806 { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1807 { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1809 { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, S
321 #define RS macro
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/platforms/powermac/
H A Dtime.c54 #define RS 0x200 /* skip between registers */ macro
55 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
56 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
57 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
58 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
59 #define ACR (11*RS) /* Auxiliary control register */
60 #define IFR (13*RS) /* Interrupt flag register */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/mips/mm/
H A Dtlbex.c67 RS = 0x001, enumerator in enum:fields
127 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
128 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
129 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
130 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
131 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
132 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
133 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
134 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
135 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIM
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/zlib-1.2.3/old/
H A DMakefile.riscos25 @copy @.lib @.libc A~C~DF~L~N~P~Q~RS~TV
52 @copy @.h.zlib $(libdest).h.zlib A~C~DF~L~N~P~Q~RS~TV
53 @copy @.h.zconf $(libdest).h.zconf A~C~DF~L~N~P~Q~RS~TV
54 @copy @.lib $(libdest).lib A~C~DF~L~N~P~Q~RS~TV
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/zlib-1.2.3/old/
H A DMakefile.riscos25 @copy @.lib @.libc A~C~DF~L~N~P~Q~RS~TV
52 @copy @.h.zlib $(libdest).h.zlib A~C~DF~L~N~P~Q~RS~TV
53 @copy @.h.zconf $(libdest).h.zconf A~C~DF~L~N~P~Q~RS~TV
54 @copy @.lib $(libdest).lib A~C~DF~L~N~P~Q~RS~TV
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mm/
H A Dproc-arm6_7.S265 mov r0, #0x3d @ . ..RS BLDP WCAM
268 mov r0, #0x3c @ . ..RS BLDP WCA.
279 mov r0, #0x7d @ . ..RS BLDP WCAM
282 mov r0, #0x7c @ . ..RS BLDP WCA.
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/flac-1.2.1/src/plugin_winamp2/
H A Dconfigure.c41 #define RS(x, n, def) GetPrivateProfileString("FLAC", #x, def, x, n, ini_name) macro
75 RS(flac_cfg.title.tag_format, sizeof(flac_cfg.title.tag_format), default_format);
80 RS(flac_cfg.title.sep, sizeof(flac_cfg.title.sep), default_sep);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/fpsp040/
H A Dstan.S236 fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3))
241 faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3))
274 fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3))
279 faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/kernel/
H A Dmisc_64.S318 #define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/wan/
H A Dpc300-falc-lh.h1238 #define RS(nbr) (0x70 + (nbr)) /* Rx CAS Reg (0 to 15) */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/router/busybox-1.x/editors/
H A Dawk.c369 ORS, RS, RT, FILENAME, enumerator in enum:__anon11268
378 "ORS\0" "RS\0*" "RT\0" "FILENAME\0"
1521 if (*getvar_s(intvar[RS]) == '\0')
1653 } else if (v == intvar[RS]) {
2800 handle_special(intvar[RS]);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/usb/serial/
H A Dxircom_pgs.S135 ;;; turn on the RS-232 driver chip (bring the STANDBY pin low)
H A Dkeyspan_pda.S133 ;;; turn on the RS-232 driver chip (bring the STANDBY pin low)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/
H A Dh264.c1380 # define RS 7 macro
1384 # define RS 3
1392 # define RS 0 macro
1404 i-= RS;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/ifpsp060/src/
H A Dfplsp.S5822 fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3))
5826 fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3))
5859 fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3))
5863 fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3))

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