1/* ppc-opc.c -- PowerPC opcode list 2 Copyright 1994 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5This file is part of GDB, GAS, and the GNU binutils. 6 7GDB, GAS, and the GNU binutils are free software; you can redistribute 8them and/or modify them under the terms of the GNU General Public 9License as published by the Free Software Foundation; either version 102, or (at your option) any later version. 11 12GDB, GAS, and the GNU binutils are distributed in the hope that they 13will be useful, but WITHOUT ANY WARRANTY; without even the implied 14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15the GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this file; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21#include <linux/posix_types.h> 22#include <linux/kernel.h> 23#include "ansidecl.h" 24#include "ppc.h" 25 26/* This file holds the PowerPC opcode table. The opcode table 27 includes almost all of the extended instruction mnemonics. This 28 permits the disassembler to use them, and simplifies the assembler 29 logic, at the cost of increasing the table size. The table is 30 strictly constant data, so the compiler should be able to put it in 31 the .text section. 32 33 This file also holds the operand table. All knowledge about 34 inserting operands into instructions and vice-versa is kept in this 35 file. */ 36 37/* Local insertion and extraction functions. */ 38 39static unsigned long insert_bat PARAMS ((unsigned long, long, const char **)); 40static long extract_bat PARAMS ((unsigned long, int *)); 41static unsigned long insert_bba PARAMS ((unsigned long, long, const char **)); 42static long extract_bba PARAMS ((unsigned long, int *)); 43static unsigned long insert_bd PARAMS ((unsigned long, long, const char **)); 44static long extract_bd PARAMS ((unsigned long, int *)); 45static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **)); 46static long extract_bdm PARAMS ((unsigned long, int *)); 47static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **)); 48static long extract_bdp PARAMS ((unsigned long, int *)); 49static unsigned long insert_bo PARAMS ((unsigned long, long, const char **)); 50static long extract_bo PARAMS ((unsigned long, int *)); 51static unsigned long insert_boe PARAMS ((unsigned long, long, const char **)); 52static long extract_boe PARAMS ((unsigned long, int *)); 53static unsigned long insert_ds PARAMS ((unsigned long, long, const char **)); 54static long extract_ds PARAMS ((unsigned long, int *)); 55static unsigned long insert_li PARAMS ((unsigned long, long, const char **)); 56static long extract_li PARAMS ((unsigned long, int *)); 57static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **)); 58static long extract_mbe PARAMS ((unsigned long, int *)); 59static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **)); 60static long extract_mb6 PARAMS ((unsigned long, int *)); 61static unsigned long insert_nb PARAMS ((unsigned long, long, const char **)); 62static long extract_nb PARAMS ((unsigned long, int *)); 63static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **)); 64static long extract_nsi PARAMS ((unsigned long, int *)); 65static unsigned long insert_ral PARAMS ((unsigned long, long, const char **)); 66static unsigned long insert_ram PARAMS ((unsigned long, long, const char **)); 67static unsigned long insert_ras PARAMS ((unsigned long, long, const char **)); 68static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **)); 69static long extract_rbs PARAMS ((unsigned long, int *)); 70static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **)); 71static long extract_sh6 PARAMS ((unsigned long, int *)); 72static unsigned long insert_spr PARAMS ((unsigned long, long, const char **)); 73static long extract_spr PARAMS ((unsigned long, int *)); 74static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **)); 75static long extract_tbr PARAMS ((unsigned long, int *)); 76 77/* The operands table. 78 79 The fields are bits, shift, signed, insert, extract, flags. */ 80 81const struct powerpc_operand powerpc_operands[] = 82{ 83 /* The zero index is used to indicate the end of the list of 84 operands. */ 85#define UNUSED (0) 86 { 0, 0, NULL, NULL, 0 }, 87 88 /* The BA field in an XL form instruction. */ 89#define BA (1) 90#define BA_MASK (0x1f << 16) 91 { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 92 93 /* The BA field in an XL form instruction when it must be the same 94 as the BT field in the same instruction. */ 95#define BAT (2) 96 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 97 98 /* The BB field in an XL form instruction. */ 99#define BB (3) 100#define BB_MASK (0x1f << 11) 101 { 5, 11, NULL, NULL, PPC_OPERAND_CR }, 102 103 /* The BB field in an XL form instruction when it must be the same 104 as the BA field in the same instruction. */ 105#define BBA (4) 106 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 107 108 /* The BD field in a B form instruction. The lower two bits are 109 forced to zero. */ 110#define BD (5) 111 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 112 113 /* The BD field in a B form instruction when absolute addressing is 114 used. */ 115#define BDA (6) 116 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 117 118 /* The BD field in a B form instruction when the - modifier is used. 119 This sets the y bit of the BO field appropriately. */ 120#define BDM (7) 121 { 16, 0, insert_bdm, extract_bdm, 122 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 123 124 /* The BD field in a B form instruction when the - modifier is used 125 and absolute address is used. */ 126#define BDMA (8) 127 { 16, 0, insert_bdm, extract_bdm, 128 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 129 130 /* The BD field in a B form instruction when the + modifier is used. 131 This sets the y bit of the BO field appropriately. */ 132#define BDP (9) 133 { 16, 0, insert_bdp, extract_bdp, 134 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 135 136 /* The BD field in a B form instruction when the + modifier is used 137 and absolute addressing is used. */ 138#define BDPA (10) 139 { 16, 0, insert_bdp, extract_bdp, 140 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 141 142 /* The BF field in an X or XL form instruction. */ 143#define BF (11) 144 { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 145 146 /* An optional BF field. This is used for comparison instructions, 147 in which an omitted BF field is taken as zero. */ 148#define OBF (12) 149 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 150 151 /* The BFA field in an X or XL form instruction. */ 152#define BFA (13) 153 { 3, 18, NULL, NULL, PPC_OPERAND_CR }, 154 155 /* The BI field in a B form or XL form instruction. */ 156#define BI (14) 157#define BI_MASK (0x1f << 16) 158 { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 159 160 /* The BO field in a B form instruction. Certain values are 161 illegal. */ 162#define BO (15) 163#define BO_MASK (0x1f << 21) 164 { 5, 21, insert_bo, extract_bo, 0 }, 165 166 /* The BO field in a B form instruction when the + or - modifier is 167 used. This is like the BO field, but it must be even. */ 168#define BOE (16) 169 { 5, 21, insert_boe, extract_boe, 0 }, 170 171 /* The BT field in an X or XL form instruction. */ 172#define BT (17) 173 { 5, 21, NULL, NULL, PPC_OPERAND_CR }, 174 175 /* The condition register number portion of the BI field in a B form 176 or XL form instruction. This is used for the extended 177 conditional branch mnemonics, which set the lower two bits of the 178 BI field. This field is optional. */ 179#define CR (18) 180 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 181 182 /* The D field in a D form instruction. This is a displacement off 183 a register, and implies that the next operand is a register in 184 parentheses. */ 185#define D (19) 186 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 187 188 /* The DS field in a DS form instruction. This is like D, but the 189 lower two bits are forced to zero. */ 190#define DS (20) 191 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 192 193 /* The FL1 field in a POWER SC form instruction. */ 194#define FL1 (21) 195 { 4, 12, NULL, NULL, 0 }, 196 197 /* The FL2 field in a POWER SC form instruction. */ 198#define FL2 (22) 199 { 3, 2, NULL, NULL, 0 }, 200 201 /* The FLM field in an XFL form instruction. */ 202#define FLM (23) 203 { 8, 17, NULL, NULL, 0 }, 204 205 /* The FRA field in an X or A form instruction. */ 206#define FRA (24) 207#define FRA_MASK (0x1f << 16) 208 { 5, 16, NULL, NULL, PPC_OPERAND_FPR }, 209 210 /* The FRB field in an X or A form instruction. */ 211#define FRB (25) 212#define FRB_MASK (0x1f << 11) 213 { 5, 11, NULL, NULL, PPC_OPERAND_FPR }, 214 215 /* The FRC field in an A form instruction. */ 216#define FRC (26) 217#define FRC_MASK (0x1f << 6) 218 { 5, 6, NULL, NULL, PPC_OPERAND_FPR }, 219 220 /* The FRS field in an X form instruction or the FRT field in a D, X 221 or A form instruction. */ 222#define FRS (27) 223#define FRT (FRS) 224 { 5, 21, NULL, NULL, PPC_OPERAND_FPR }, 225 226 /* The FXM field in an XFX instruction. */ 227#define FXM (28) 228#define FXM_MASK (0xff << 12) 229 { 8, 12, NULL, NULL, 0 }, 230 231 /* The L field in a D or X form instruction. */ 232#define L (29) 233 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 234 235 /* The LEV field in a POWER SC form instruction. */ 236#define LEV (30) 237 { 7, 5, NULL, NULL, 0 }, 238 239 /* The LI field in an I form instruction. The lower two bits are 240 forced to zero. */ 241#define LI (31) 242 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 243 244 /* The LI field in an I form instruction when used as an absolute 245 address. */ 246#define LIA (32) 247 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 248 249 /* The MB field in an M form instruction. */ 250#define MB (33) 251#define MB_MASK (0x1f << 6) 252 { 5, 6, NULL, NULL, 0 }, 253 254 /* The ME field in an M form instruction. */ 255#define ME (34) 256#define ME_MASK (0x1f << 1) 257 { 5, 1, NULL, NULL, 0 }, 258 259 /* The MB and ME fields in an M form instruction expressed a single 260 operand which is a bitmask indicating which bits to select. This 261 is a two operand form using PPC_OPERAND_NEXT. See the 262 description in opcode/ppc.h for what this means. */ 263#define MBE (35) 264 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 265 { 32, 0, insert_mbe, extract_mbe, 0 }, 266 267 /* The MB or ME field in an MD or MDS form instruction. The high 268 bit is wrapped to the low end. */ 269#define MB6 (37) 270#define ME6 (MB6) 271#define MB6_MASK (0x3f << 5) 272 { 6, 5, insert_mb6, extract_mb6, 0 }, 273 274 /* The NB field in an X form instruction. The value 32 is stored as 275 0. */ 276#define NB (38) 277 { 6, 11, insert_nb, extract_nb, 0 }, 278 279 /* The NSI field in a D form instruction. This is the same as the 280 SI field, only negated. */ 281#define NSI (39) 282 { 16, 0, insert_nsi, extract_nsi, 283 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 284 285 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ 286#define RA (40) 287#define RA_MASK (0x1f << 16) 288 { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, 289 290 /* The RA field in a D or X form instruction which is an updating 291 load, which means that the RA field may not be zero and may not 292 equal the RT field. */ 293#define RAL (41) 294 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR }, 295 296 /* The RA field in an lmw instruction, which has special value 297 restrictions. */ 298#define RAM (42) 299 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR }, 300 301 /* The RA field in a D or X form instruction which is an updating 302 store or an updating floating point load, which means that the RA 303 field may not be zero. */ 304#define RAS (43) 305 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR }, 306 307 /* The RB field in an X, XO, M, or MDS form instruction. */ 308#define RB (44) 309#define RB_MASK (0x1f << 11) 310 { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, 311 312 /* The RB field in an X form instruction when it must be the same as 313 the RS field in the instruction. This is used for extended 314 mnemonics like mr. */ 315#define RBS (45) 316 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 317 318 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 319 instruction or the RT field in a D, DS, X, XFX or XO form 320 instruction. */ 321#define RS (46) 322#define RT (RS) 323#define RT_MASK (0x1f << 21) 324 { 5, 21, NULL, NULL, PPC_OPERAND_GPR }, 325 326 /* The SH field in an X or M form instruction. */ 327#define SH (47) 328#define SH_MASK (0x1f << 11) 329 { 5, 11, NULL, NULL, 0 }, 330 331 /* The SH field in an MD form instruction. This is split. */ 332#define SH6 (48) 333#define SH6_MASK ((0x1f << 11) | (1 << 1)) 334 { 6, 1, insert_sh6, extract_sh6, 0 }, 335 336 /* The SI field in a D form instruction. */ 337#define SI (49) 338 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 339 340 /* The SI field in a D form instruction when we accept a wide range 341 of positive values. */ 342#define SISIGNOPT (50) 343 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 344 345 /* The SPR field in an XFX form instruction. This is flipped--the 346 lower 5 bits are stored in the upper 5 and vice- versa. */ 347#define SPR (51) 348#define SPR_MASK (0x3ff << 11) 349 { 10, 11, insert_spr, extract_spr, 0 }, 350 351 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 352#define SPRBAT (52) 353#define SPRBAT_MASK (0x3 << 17) 354 { 2, 17, NULL, NULL, 0 }, 355 356 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 357#define SPRG (53) 358#define SPRG_MASK (0x3 << 16) 359 { 2, 16, NULL, NULL, 0 }, 360 361 /* The SR field in an X form instruction. */ 362#define SR (54) 363 { 4, 16, NULL, NULL, 0 }, 364 365 /* The SV field in a POWER SC form instruction. */ 366#define SV (55) 367 { 14, 2, NULL, NULL, 0 }, 368 369 /* The TBR field in an XFX form instruction. This is like the SPR 370 field, but it is optional. */ 371#define TBR (56) 372 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 373 374 /* The TO field in a D or X form instruction. */ 375#define TO (57) 376#define TO_MASK (0x1f << 21) 377 { 5, 21, NULL, NULL, 0 }, 378 379 /* The U field in an X form instruction. */ 380#define U (58) 381 { 4, 12, NULL, NULL, 0 }, 382 383 /* The UI field in a D form instruction. */ 384#define UI (59) 385 { 16, 0, NULL, NULL, 0 }, 386}; 387 388/* The functions used to insert and extract complicated operands. */ 389 390/* The BA field in an XL form instruction when it must be the same as 391 the BT field in the same instruction. This operand is marked FAKE. 392 The insertion function just copies the BT field into the BA field, 393 and the extraction function just checks that the fields are the 394 same. */ 395 396/*ARGSUSED*/ 397static unsigned long 398insert_bat(unsigned long insn, long value, const char **errmsg) 399{ 400 return insn | (((insn >> 21) & 0x1f) << 16); 401} 402 403static long 404extract_bat(unsigned long insn, int *invalid) 405{ 406 if (invalid != (int *) NULL 407 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 408 *invalid = 1; 409 return 0; 410} 411 412/* The BB field in an XL form instruction when it must be the same as 413 the BA field in the same instruction. This operand is marked FAKE. 414 The insertion function just copies the BA field into the BB field, 415 and the extraction function just checks that the fields are the 416 same. */ 417 418/*ARGSUSED*/ 419static unsigned long 420insert_bba(unsigned long insn, long value, const char **errmsg) 421{ 422 return insn | (((insn >> 16) & 0x1f) << 11); 423} 424 425static long 426extract_bba(unsigned long insn, int *invalid) 427{ 428 if (invalid != (int *) NULL 429 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 430 *invalid = 1; 431 return 0; 432} 433 434/* The BD field in a B form instruction. The lower two bits are 435 forced to zero. */ 436 437/*ARGSUSED*/ 438static unsigned long 439insert_bd(unsigned long insn, long value, const char **errmsg) 440{ 441 return insn | (value & 0xfffc); 442} 443 444/*ARGSUSED*/ 445static long 446extract_bd(unsigned long insn, int *invalid) 447{ 448 if ((insn & 0x8000) != 0) 449 return (insn & 0xfffc) - 0x10000; 450 else 451 return insn & 0xfffc; 452} 453 454/* The BD field in a B form instruction when the - modifier is used. 455 This modifier means that the branch is not expected to be taken. 456 We must set the y bit of the BO field to 1 if the offset is 457 negative. When extracting, we require that the y bit be 1 and that 458 the offset be positive, since if the y bit is 0 we just want to 459 print the normal form of the instruction. */ 460 461/*ARGSUSED*/ 462static unsigned long 463insert_bdm(unsigned long insn, long value, const char **errmsg) 464{ 465 if ((value & 0x8000) != 0) 466 insn |= 1 << 21; 467 return insn | (value & 0xfffc); 468} 469 470static long 471extract_bdm(unsigned long insn, int *invalid) 472{ 473 if (invalid != (int *) NULL 474 && ((insn & (1 << 21)) == 0 475 || (insn & (1 << 15)) == 0)) 476 *invalid = 1; 477 if ((insn & 0x8000) != 0) 478 return (insn & 0xfffc) - 0x10000; 479 else 480 return insn & 0xfffc; 481} 482 483/* The BD field in a B form instruction when the + modifier is used. 484 This is like BDM, above, except that the branch is expected to be 485 taken. */ 486 487/*ARGSUSED*/ 488static unsigned long 489insert_bdp(unsigned long insn, long value, const char **errmsg) 490{ 491 if ((value & 0x8000) == 0) 492 insn |= 1 << 21; 493 return insn | (value & 0xfffc); 494} 495 496static long 497extract_bdp(unsigned long insn, int *invalid) 498{ 499 if (invalid != (int *) NULL 500 && ((insn & (1 << 21)) == 0 501 || (insn & (1 << 15)) != 0)) 502 *invalid = 1; 503 if ((insn & 0x8000) != 0) 504 return (insn & 0xfffc) - 0x10000; 505 else 506 return insn & 0xfffc; 507} 508 509/* Check for legal values of a BO field. */ 510 511static int 512valid_bo (long value) 513{ 514 /* Certain encodings have bits that are required to be zero. These 515 are (z must be zero, y may be anything): 516 001zy 517 011zy 518 1z00y 519 1z01y 520 1z1zz 521 */ 522 switch (value & 0x14) 523 { 524 default: 525 case 0: 526 return 1; 527 case 0x4: 528 return (value & 0x2) == 0; 529 case 0x10: 530 return (value & 0x8) == 0; 531 case 0x14: 532 return value == 0x14; 533 } 534} 535 536/* The BO field in a B form instruction. Warn about attempts to set 537 the field to an illegal value. */ 538 539static unsigned long 540insert_bo(unsigned long insn, long value, const char **errmsg) 541{ 542 if (errmsg != (const char **) NULL 543 && ! valid_bo (value)) 544 *errmsg = "invalid conditional option"; 545 return insn | ((value & 0x1f) << 21); 546} 547 548static long 549extract_bo(unsigned long insn, int *invalid) 550{ 551 long value; 552 553 value = (insn >> 21) & 0x1f; 554 if (invalid != (int *) NULL 555 && ! valid_bo (value)) 556 *invalid = 1; 557 return value; 558} 559 560/* The BO field in a B form instruction when the + or - modifier is 561 used. This is like the BO field, but it must be even. When 562 extracting it, we force it to be even. */ 563 564static unsigned long 565insert_boe(unsigned long insn, long value, const char **errmsg) 566{ 567 if (errmsg != (const char **) NULL) 568 { 569 if (! valid_bo (value)) 570 *errmsg = "invalid conditional option"; 571 else if ((value & 1) != 0) 572 *errmsg = "attempt to set y bit when using + or - modifier"; 573 } 574 return insn | ((value & 0x1f) << 21); 575} 576 577static long 578extract_boe(unsigned long insn, int *invalid) 579{ 580 long value; 581 582 value = (insn >> 21) & 0x1f; 583 if (invalid != (int *) NULL 584 && ! valid_bo (value)) 585 *invalid = 1; 586 return value & 0x1e; 587} 588 589/* The DS field in a DS form instruction. This is like D, but the 590 lower two bits are forced to zero. */ 591 592/*ARGSUSED*/ 593static unsigned long 594insert_ds(unsigned long insn, long value, const char **errmsg) 595{ 596 return insn | (value & 0xfffc); 597} 598 599/*ARGSUSED*/ 600static long 601extract_ds(unsigned long insn, int *invalid) 602{ 603 if ((insn & 0x8000) != 0) 604 return (insn & 0xfffc) - 0x10000; 605 else 606 return insn & 0xfffc; 607} 608 609/* The LI field in an I form instruction. The lower two bits are 610 forced to zero. */ 611 612/*ARGSUSED*/ 613static unsigned long 614insert_li(unsigned long insn, long value, const char **errmsg) 615{ 616 return insn | (value & 0x3fffffc); 617} 618 619/*ARGSUSED*/ 620static long 621extract_li(unsigned long insn, int *invalid) 622{ 623 if ((insn & 0x2000000) != 0) 624 return (insn & 0x3fffffc) - 0x4000000; 625 else 626 return insn & 0x3fffffc; 627} 628 629/* The MB and ME fields in an M form instruction expressed as a single 630 operand which is itself a bitmask. The extraction function always 631 marks it as invalid, since we never want to recognize an 632 instruction which uses a field of this type. */ 633 634static unsigned long 635insert_mbe(unsigned long insn, long value, const char **errmsg) 636{ 637 unsigned long uval; 638 int mb, me; 639 640 uval = value; 641 642 if (uval == 0) 643 { 644 if (errmsg != (const char **) NULL) 645 *errmsg = "illegal bitmask"; 646 return insn; 647 } 648 649 me = 31; 650 while ((uval & 1) == 0) 651 { 652 uval >>= 1; 653 --me; 654 } 655 656 mb = me; 657 uval >>= 1; 658 while ((uval & 1) != 0) 659 { 660 uval >>= 1; 661 --mb; 662 } 663 664 if (uval != 0) 665 { 666 if (errmsg != (const char **) NULL) 667 *errmsg = "illegal bitmask"; 668 } 669 670 return insn | (mb << 6) | (me << 1); 671} 672 673static long 674extract_mbe(unsigned long insn, int *invalid) 675{ 676 long ret; 677 int mb, me; 678 int i; 679 680 if (invalid != (int *) NULL) 681 *invalid = 1; 682 683 ret = 0; 684 mb = (insn >> 6) & 0x1f; 685 me = (insn >> 1) & 0x1f; 686 for (i = mb; i < me; i++) 687 ret |= 1 << (31 - i); 688 return ret; 689} 690 691/* The MB or ME field in an MD or MDS form instruction. The high bit 692 is wrapped to the low end. */ 693 694/*ARGSUSED*/ 695static unsigned long 696insert_mb6(unsigned long insn, long value, const char **errmsg) 697{ 698 return insn | ((value & 0x1f) << 6) | (value & 0x20); 699} 700 701/*ARGSUSED*/ 702static long 703extract_mb6(unsigned long insn, int *invalid) 704{ 705 return ((insn >> 6) & 0x1f) | (insn & 0x20); 706} 707 708/* The NB field in an X form instruction. The value 32 is stored as 709 0. */ 710 711static unsigned long 712insert_nb(unsigned long insn, long value, const char **errmsg) 713{ 714 if (value < 0 || value > 32) 715 *errmsg = "value out of range"; 716 if (value == 32) 717 value = 0; 718 return insn | ((value & 0x1f) << 11); 719} 720 721/*ARGSUSED*/ 722static long 723extract_nb(unsigned long insn, int *invalid) 724{ 725 long ret; 726 727 ret = (insn >> 11) & 0x1f; 728 if (ret == 0) 729 ret = 32; 730 return ret; 731} 732 733/* The NSI field in a D form instruction. This is the same as the SI 734 field, only negated. The extraction function always marks it as 735 invalid, since we never want to recognize an instruction which uses 736 a field of this type. */ 737 738/*ARGSUSED*/ 739static unsigned long 740insert_nsi(unsigned long insn, long value, const char **errmsg) 741{ 742 return insn | ((- value) & 0xffff); 743} 744 745static long 746extract_nsi(unsigned long insn, int *invalid) 747{ 748 if (invalid != (int *) NULL) 749 *invalid = 1; 750 if ((insn & 0x8000) != 0) 751 return - ((insn & 0xffff) - 0x10000); 752 else 753 return - (insn & 0xffff); 754} 755 756/* The RA field in a D or X form instruction which is an updating 757 load, which means that the RA field may not be zero and may not 758 equal the RT field. */ 759 760static unsigned long 761insert_ral(unsigned long insn, long value, const char **errmsg) 762{ 763 if (value == 0 764 || value == ((insn >> 21) & 0x1f)) 765 *errmsg = "invalid register operand when updating"; 766 return insn | ((value & 0x1f) << 16); 767} 768 769/* The RA field in an lmw instruction, which has special value 770 restrictions. */ 771 772static unsigned long 773insert_ram(unsigned long insn, long value, const char **errmsg) 774{ 775 if (value >= ((insn >> 21) & 0x1f)) 776 *errmsg = "index register in load range"; 777 return insn | ((value & 0x1f) << 16); 778} 779 780/* The RA field in a D or X form instruction which is an updating 781 store or an updating floating point load, which means that the RA 782 field may not be zero. */ 783 784static unsigned long 785insert_ras(unsigned long insn, long value, const char **errmsg) 786{ 787 if (value == 0) 788 *errmsg = "invalid register operand when updating"; 789 return insn | ((value & 0x1f) << 16); 790} 791 792/* The RB field in an X form instruction when it must be the same as 793 the RS field in the instruction. This is used for extended 794 mnemonics like mr. This operand is marked FAKE. The insertion 795 function just copies the BT field into the BA field, and the 796 extraction function just checks that the fields are the same. */ 797 798/*ARGSUSED*/ 799static unsigned long 800insert_rbs(unsigned long insn, long value, const char **errmsg) 801{ 802 return insn | (((insn >> 21) & 0x1f) << 11); 803} 804 805static long 806extract_rbs(unsigned long insn, int *invalid) 807{ 808 if (invalid != (int *) NULL 809 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 810 *invalid = 1; 811 return 0; 812} 813 814/* The SH field in an MD form instruction. This is split. */ 815 816/*ARGSUSED*/ 817static unsigned long 818insert_sh6(unsigned long insn, long value, const char **errmsg) 819{ 820 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 821} 822 823/*ARGSUSED*/ 824static long 825extract_sh6(unsigned long insn, int *invalid) 826{ 827 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 828} 829 830/* The SPR field in an XFX form instruction. This is flipped--the 831 lower 5 bits are stored in the upper 5 and vice- versa. */ 832 833static unsigned long 834insert_spr(unsigned long insn, long value, const char **errmsg) 835{ 836 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 837} 838 839static long 840extract_spr(unsigned long insn, int *invalid) 841{ 842 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 843} 844 845/* The TBR field in an XFX instruction. This is just like SPR, but it 846 is optional. When TBR is omitted, it must be inserted as 268 (the 847 magic number of the TB register). These functions treat 0 848 (indicating an omitted optional operand) as 268. This means that 849 ``mftb 4,0'' is not handled correctly. This does not matter very 850 much, since the architecture manual does not define mftb as 851 accepting any values other than 268 or 269. */ 852 853#define TB (268) 854 855static unsigned long 856insert_tbr(unsigned long insn, long value, const char **errmsg) 857{ 858 if (value == 0) 859 value = TB; 860 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 861} 862 863static long 864extract_tbr(unsigned long insn, int *invalid) 865{ 866 long ret; 867 868 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 869 if (ret == TB) 870 ret = 0; 871 return ret; 872} 873 874/* Macros used to form opcodes. */ 875 876/* The main opcode. */ 877#define OP(x) (((x) & 0x3f) << 26) 878#define OP_MASK OP (0x3f) 879 880/* The main opcode combined with a trap code in the TO field of a D 881 form instruction. Used for extended mnemonics for the trap 882 instructions. */ 883#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21)) 884#define OPTO_MASK (OP_MASK | TO_MASK) 885 886/* The main opcode combined with a comparison size bit in the L field 887 of a D form or X form instruction. Used for extended mnemonics for 888 the comparison instructions. */ 889#define OPL(x,l) (OP (x) | (((l) & 1) << 21)) 890#define OPL_MASK OPL (0x3f,1) 891 892/* An A form instruction. */ 893#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1)) 894#define A_MASK A (0x3f, 0x1f, 1) 895 896/* An A_MASK with the FRB field fixed. */ 897#define AFRB_MASK (A_MASK | FRB_MASK) 898 899/* An A_MASK with the FRC field fixed. */ 900#define AFRC_MASK (A_MASK | FRC_MASK) 901 902/* An A_MASK with the FRA and FRC fields fixed. */ 903#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 904 905/* A B form instruction. */ 906#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1)) 907#define B_MASK B (0x3f, 1, 1) 908 909/* A B form instruction setting the BO field. */ 910#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21)) 911#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 912 913/* A BBO_MASK with the y bit of the BO field removed. This permits 914 matching a conditional branch regardless of the setting of the y 915 bit. */ 916#define Y_MASK (1 << 21) 917#define BBOY_MASK (BBO_MASK &~ Y_MASK) 918 919/* A B form instruction setting the BO field and the condition bits of 920 the BI field. */ 921#define BBOCB(op, bo, cb, aa, lk) \ 922 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16)) 923#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 924 925/* A BBOCB_MASK with the y bit of the BO field removed. */ 926#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 927 928/* A BBOYCB_MASK in which the BI field is fixed. */ 929#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 930 931/* The main opcode mask with the RA field clear. */ 932#define DRA_MASK (OP_MASK | RA_MASK) 933 934/* A DS form instruction. */ 935#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 936#define DS_MASK DSO (0x3f, 3) 937 938/* An M form instruction. */ 939#define M(op, rc) (OP (op) | ((rc) & 1)) 940#define M_MASK M (0x3f, 1) 941 942/* An M form instruction with the ME field specified. */ 943#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1)) 944 945/* An M_MASK with the MB and ME fields fixed. */ 946#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 947 948/* An M_MASK with the SH and ME fields fixed. */ 949#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 950 951/* An MD form instruction. */ 952#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1)) 953#define MD_MASK MD (0x3f, 0x7, 1) 954 955/* An MD_MASK with the MB field fixed. */ 956#define MDMB_MASK (MD_MASK | MB6_MASK) 957 958/* An MD_MASK with the SH field fixed. */ 959#define MDSH_MASK (MD_MASK | SH6_MASK) 960 961/* An MDS form instruction. */ 962#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1)) 963#define MDS_MASK MDS (0x3f, 0xf, 1) 964 965/* An MDS_MASK with the MB field fixed. */ 966#define MDSMB_MASK (MDS_MASK | MB6_MASK) 967 968/* An SC form instruction. */ 969#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1)) 970#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1) 971 972/* An X form instruction. */ 973#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) 974 975/* An X form instruction with the RC bit specified. */ 976#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 977 978/* The mask for an X form instruction. */ 979#define X_MASK XRC (0x3f, 0x3ff, 1) 980 981/* An X_MASK with the RA field fixed. */ 982#define XRA_MASK (X_MASK | RA_MASK) 983 984/* An X_MASK with the RB field fixed. */ 985#define XRB_MASK (X_MASK | RB_MASK) 986 987/* An X_MASK with the RT field fixed. */ 988#define XRT_MASK (X_MASK | RT_MASK) 989 990/* An X_MASK with the RA and RB fields fixed. */ 991#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 992 993/* An X_MASK with the RT and RA fields fixed. */ 994#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 995 996/* An X form comparison instruction. */ 997#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21)) 998 999/* The mask for an X form comparison instruction. */ 1000#define XCMP_MASK (X_MASK | (1 << 22)) 1001 1002/* The mask for an X form comparison instruction with the L field 1003 fixed. */ 1004#define XCMPL_MASK (XCMP_MASK | (1 << 21)) 1005 1006/* An X form trap instruction with the TO field specified. */ 1007#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21)) 1008#define XTO_MASK (X_MASK | TO_MASK) 1009 1010/* An XFL form instruction. */ 1011#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1)) 1012#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16)) 1013 1014/* An XL form instruction with the LK field set to 0. */ 1015#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) 1016 1017/* An XL form instruction which uses the LK field. */ 1018#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 1019 1020/* The mask for an XL form instruction. */ 1021#define XL_MASK XLLK (0x3f, 0x3ff, 1) 1022 1023/* An XL form instruction which explicitly sets the BO field. */ 1024#define XLO(op, bo, xop, lk) \ 1025 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21)) 1026#define XLO_MASK (XL_MASK | BO_MASK) 1027 1028/* An XL form instruction which explicitly sets the y bit of the BO 1029 field. */ 1030#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21)) 1031#define XLYLK_MASK (XL_MASK | Y_MASK) 1032 1033/* An XL form instruction which sets the BO field and the condition 1034 bits of the BI field. */ 1035#define XLOCB(op, bo, cb, xop, lk) \ 1036 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16)) 1037#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 1038 1039/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 1040#define XLBB_MASK (XL_MASK | BB_MASK) 1041#define XLYBB_MASK (XLYLK_MASK | BB_MASK) 1042#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 1043 1044/* An XL_MASK with the BO and BB fields fixed. */ 1045#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 1046 1047/* An XL_MASK with the BO, BI and BB fields fixed. */ 1048#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 1049 1050/* An XO form instruction. */ 1051#define XO(op, xop, oe, rc) \ 1052 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1)) 1053#define XO_MASK XO (0x3f, 0x1ff, 1, 1) 1054 1055/* An XO_MASK with the RB field fixed. */ 1056#define XORB_MASK (XO_MASK | RB_MASK) 1057 1058/* An XS form instruction. */ 1059#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1)) 1060#define XS_MASK XS (0x3f, 0x1ff, 1) 1061 1062/* A mask for the FXM version of an XFX form instruction. */ 1063#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11)) 1064 1065/* An XFX form instruction with the FXM field filled in. */ 1066#define XFXM(op, xop, fxm) \ 1067 (X ((op), (xop)) | (((fxm) & 0xff) << 12)) 1068 1069/* An XFX form instruction with the SPR field filled in. */ 1070#define XSPR(op, xop, spr) \ 1071 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6)) 1072#define XSPR_MASK (X_MASK | SPR_MASK) 1073 1074/* An XFX form instruction with the SPR field filled in except for the 1075 SPRBAT field. */ 1076#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 1077 1078/* An XFX form instruction with the SPR field filled in except for the 1079 SPRG field. */ 1080#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) 1081 1082/* The BO encodings used in extended conditional branch mnemonics. */ 1083#define BODNZF (0x0) 1084#define BODNZFP (0x1) 1085#define BODZF (0x2) 1086#define BODZFP (0x3) 1087#define BOF (0x4) 1088#define BOFP (0x5) 1089#define BODNZT (0x8) 1090#define BODNZTP (0x9) 1091#define BODZT (0xa) 1092#define BODZTP (0xb) 1093#define BOT (0xc) 1094#define BOTP (0xd) 1095#define BODNZ (0x10) 1096#define BODNZP (0x11) 1097#define BODZ (0x12) 1098#define BODZP (0x13) 1099#define BOU (0x14) 1100 1101/* The BI condition bit encodings used in extended conditional branch 1102 mnemonics. */ 1103#define CBLT (0) 1104#define CBGT (1) 1105#define CBEQ (2) 1106#define CBSO (3) 1107 1108/* The TO encodings used in extended trap mnemonics. */ 1109#define TOLGT (0x1) 1110#define TOLLT (0x2) 1111#define TOEQ (0x4) 1112#define TOLGE (0x5) 1113#define TOLNL (0x5) 1114#define TOLLE (0x6) 1115#define TOLNG (0x6) 1116#define TOGT (0x8) 1117#define TOGE (0xc) 1118#define TONL (0xc) 1119#define TOLT (0x10) 1120#define TOLE (0x14) 1121#define TONG (0x14) 1122#define TONE (0x18) 1123#define TOU (0x1f) 1124 1125/* Smaller names for the flags so each entry in the opcodes table will 1126 fit on a single line. */ 1127#undef PPC 1128#define PPC PPC_OPCODE_PPC 1129#define POWER PPC_OPCODE_POWER 1130#define POWER2 PPC_OPCODE_POWER2 1131#define B32 PPC_OPCODE_32 1132#define B64 PPC_OPCODE_64 1133#define M601 PPC_OPCODE_601 1134 1135/* The opcode table. 1136 1137 The format of the opcode table is: 1138 1139 NAME OPCODE MASK FLAGS { OPERANDS } 1140 1141 NAME is the name of the instruction. 1142 OPCODE is the instruction opcode. 1143 MASK is the opcode mask; this is used to tell the disassembler 1144 which bits in the actual opcode must match OPCODE. 1145 FLAGS are flags indicated what processors support the instruction. 1146 OPERANDS is the list of operands. 1147 1148 The disassembler reads the table in order and prints the first 1149 instruction which matches, so this table is sorted to put more 1150 specific instructions before more general instructions. It is also 1151 sorted by major opcode. */ 1152 1153const struct powerpc_opcode powerpc_opcodes[] = { 1154{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } }, 1155{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } }, 1156{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } }, 1157{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } }, 1158{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } }, 1159{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } }, 1160{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } }, 1161{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } }, 1162{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } }, 1163{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } }, 1164{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } }, 1165{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } }, 1166{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } }, 1167{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } }, 1168{ "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } }, 1169 1170{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } }, 1171{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } }, 1172{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } }, 1173{ "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } }, 1174{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } }, 1175{ "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } }, 1176{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } }, 1177{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } }, 1178{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } }, 1179{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } }, 1180{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } }, 1181{ "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } }, 1182{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } }, 1183{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } }, 1184{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } }, 1185{ "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } }, 1186{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } }, 1187{ "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } }, 1188{ "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } }, 1189{ "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } }, 1190{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } }, 1191{ "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } }, 1192{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } }, 1193{ "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } }, 1194{ "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } }, 1195{ "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } }, 1196{ "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } }, 1197{ "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } }, 1198{ "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } }, 1199{ "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } }, 1200 1201{ "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } }, 1202{ "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } }, 1203 1204{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } }, 1205{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } }, 1206 1207{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } }, 1208 1209{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } }, 1210{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } }, 1211{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, 1212{ "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } }, 1213 1214{ "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } }, 1215{ "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } }, 1216{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, 1217{ "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } }, 1218 1219{ "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } }, 1220{ "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } }, 1221{ "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } }, 1222 1223{ "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } }, 1224{ "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } }, 1225{ "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } }, 1226 1227{ "li", OP(14), DRA_MASK, PPC, { RT, SI } }, 1228{ "lil", OP(14), DRA_MASK, POWER, { RT, SI } }, 1229{ "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } }, 1230{ "cal", OP(14), OP_MASK, POWER, { RT, D, RA } }, 1231{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } }, 1232{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } }, 1233 1234{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } }, 1235{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } }, 1236{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } }, 1237{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } }, 1238{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } }, 1239 1240{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } }, 1241{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } }, 1242{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } }, 1243{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } }, 1244{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } }, 1245{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } }, 1246{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } }, 1247{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } }, 1248{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, 1249{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, 1250{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } }, 1251{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } }, 1252{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, 1253{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, 1254{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } }, 1255{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } }, 1256{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } }, 1257{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } }, 1258{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } }, 1259{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } }, 1260{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } }, 1261{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } }, 1262{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, 1263{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, 1264{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } }, 1265{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, 1266{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, 1267{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } }, 1268{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1269{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1270{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1271{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1272{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1273{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1274{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1275{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1276{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1277{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1278{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1279{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1280{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1281{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1282{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1283{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1284{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1285{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1286{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1287{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1288{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1289{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1290{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1291{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1292{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1293{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1294{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1295{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1296{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1297{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1298{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1299{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1300{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1301{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1302{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1303{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1304{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1305{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1306{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1307{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1308{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1309{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1310{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1311{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1312{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1313{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1314{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1315{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1316{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1317{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1318{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, 1319{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1320{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1321{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, 1322{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1323{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1324{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, 1325{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1326{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1327{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, 1328{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1329{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1330{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1331{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1332{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1333{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1334{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1335{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1336{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1337{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1338{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1339{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1340{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1341{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1342{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1343{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1344{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1345{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1346{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1347{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1348{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1349{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1350{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1351{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1352{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1353{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1354{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1355{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1356{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1357{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1358{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1359{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1360{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1361{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1362{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1363{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1364{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1365{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1366{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1367{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1368{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1369{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1370{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1371{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1372{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1373{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1374{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1375{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1376{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1377{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1378{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1379{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1380{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1381{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1382{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1383{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1384{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1385{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1386{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1387{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1388{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1389{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1390{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1391{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1392{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1393{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, 1394{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1395{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1396{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1397{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1398{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1399{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, 1400{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, 1401{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, 1402{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, 1403{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, 1404{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, 1405{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, 1406{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, 1407{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, 1408{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, 1409{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, 1410{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, 1411{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, 1412{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, 1413{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, 1414{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } }, 1415{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, 1416{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, 1417{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } }, 1418{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, 1419{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, 1420{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, 1421{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, 1422{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, 1423{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, 1424{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, 1425{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, 1426{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } }, 1427{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, 1428{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, 1429{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } }, 1430{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, 1431{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, 1432{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, 1433{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, 1434{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, 1435{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, 1436{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } }, 1437{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } }, 1438{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } }, 1439{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } }, 1440{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } }, 1441{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } }, 1442{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } }, 1443{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } }, 1444{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, 1445{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, 1446{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } }, 1447{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } }, 1448{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, 1449{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, 1450{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } }, 1451{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } }, 1452{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } }, 1453{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } }, 1454{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } }, 1455{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } }, 1456{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } }, 1457{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } }, 1458{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } }, 1459{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } }, 1460{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, 1461{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, 1462{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } }, 1463{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } }, 1464{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, 1465{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, 1466{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } }, 1467{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } }, 1468{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, 1469{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, 1470{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } }, 1471{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, 1472{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, 1473{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } }, 1474{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, 1475{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, 1476{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, 1477{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, 1478{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, 1479{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, 1480{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, 1481{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, 1482{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } }, 1483{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, 1484{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, 1485{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } }, 1486{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, 1487{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, 1488{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, 1489{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, 1490{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, 1491{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, 1492{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } }, 1493{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } }, 1494{ "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } }, 1495{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } }, 1496{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } }, 1497{ "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } }, 1498{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } }, 1499{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } }, 1500{ "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } }, 1501{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } }, 1502{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } }, 1503{ "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } }, 1504 1505{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, 1506{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, 1507{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, 1508{ "svca", SC(17,1,0), SC_MASK, POWER, { SV } }, 1509{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 1510 1511{ "b", B(18,0,0), B_MASK, PPC|POWER, { LI } }, 1512{ "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } }, 1513{ "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } }, 1514{ "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } }, 1515 1516{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, 1517 1518{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1519{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } }, 1520{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1521{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } }, 1522{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1523{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1524{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1525{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1526{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1527{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1528{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1529{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1530{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, 1531{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1532{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1533{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, 1534{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1535{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1536{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1537{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1538{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1539{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1540{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1541{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1542{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1543{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1544{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1545{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1546{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1547{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1548{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1549{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1550{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1551{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1552{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1553{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1554{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1555{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1556{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1557{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1558{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1559{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1560{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1561{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1562{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1563{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1564{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1565{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1566{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1567{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1568{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1569{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1570{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1571{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1572{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1573{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1574{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1575{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1576{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1577{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1578{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1579{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1580{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1581{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1582{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1583{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1584{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1585{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1586{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1587{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1588{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1589{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1590{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1591{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1592{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1593{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1594{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1595{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1596{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1597{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1598{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1599{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1600{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1601{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1602{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1603{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1604{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1605{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1606{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1607{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1608{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1609{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1610{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1611{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1612{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1613{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1614{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1615{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, 1616{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1617{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1618{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1619{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, 1620{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1621{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1622{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, 1623{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1624{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1625{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, 1626{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, 1627{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, 1628{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } }, 1629{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } }, 1630{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, 1631{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, 1632{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } }, 1633{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } }, 1634{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, 1635{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, 1636{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } }, 1637{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } }, 1638{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, 1639{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, 1640{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } }, 1641{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } }, 1642{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, 1643{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, 1644{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } }, 1645{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, 1646{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, 1647{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } }, 1648{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, 1649{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, 1650{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } }, 1651{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, 1652{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, 1653{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } }, 1654{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, 1655{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, 1656{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } }, 1657{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, 1658{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, 1659{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } }, 1660{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, 1661{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, 1662{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } }, 1663{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, 1664{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, 1665{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } }, 1666{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } }, 1667{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } }, 1668{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } }, 1669{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } }, 1670{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } }, 1671{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } }, 1672{ "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } }, 1673{ "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } }, 1674 1675{ "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } }, 1676{ "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1677 1678{ "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } }, 1679{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } }, 1680 1681{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, 1682 1683{ "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1684 1685{ "isync", XL(19,150), 0xffffffff, PPC, { 0 } }, 1686{ "ics", XL(19,150), 0xffffffff, POWER, { 0 } }, 1687 1688{ "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } }, 1689{ "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1690 1691{ "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1692 1693{ "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1694 1695{ "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } }, 1696{ "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1697 1698{ "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1699 1700{ "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } }, 1701{ "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } }, 1702 1703{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } }, 1704{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } }, 1705{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1706{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1707{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1708{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1709{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1710{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1711{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1712{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1713{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1714{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1715{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1716{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1717{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1718{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1719{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1720{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1721{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1722{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1723{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1724{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1725{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1726{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1727{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1728{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1729{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1730{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1731{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1732{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1733{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1734{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1735{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1736{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1737{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1738{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1739{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1740{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1741{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1742{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1743{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1744{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1745{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1746{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1747{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1748{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1749{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1750{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1751{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1752{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1753{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1754{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1755{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1756{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1757{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1758{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1759{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1760{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1761{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1762{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1763{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1764{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1765{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1766{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1767{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1768{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1769{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1770{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1771{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1772{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1773{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, 1774{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1775{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1776{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, 1777{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, 1778{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, 1779{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } }, 1780{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, 1781{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, 1782{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } }, 1783{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, 1784{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, 1785{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } }, 1786{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, 1787{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, 1788{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } }, 1789{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } }, 1790{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } }, 1791{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } }, 1792{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } }, 1793{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } }, 1794{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } }, 1795{ "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } }, 1796{ "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } }, 1797 1798{ "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, 1799{ "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, 1800 1801{ "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, 1802{ "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, 1803 1804{ "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } }, 1805{ "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } }, 1806{ "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, 1807{ "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, 1808{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } }, 1809{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } }, 1810{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, 1811{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, 1812 1813{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, 1814{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, 1815 1816{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } }, 1817{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, 1818{ "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, 1819{ "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } }, 1820{ "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, 1821{ "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, 1822 1823{ "nop", OP(24), 0xffffffff, PPC, { 0 } }, 1824{ "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } }, 1825{ "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } }, 1826 1827{ "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } }, 1828{ "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } }, 1829 1830{ "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } }, 1831{ "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } }, 1832 1833{ "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } }, 1834{ "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } }, 1835 1836{ "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } }, 1837{ "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } }, 1838 1839{ "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } }, 1840{ "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } }, 1841 1842{ "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, 1843{ "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, 1844{ "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, 1845{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, 1846{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, 1847{ "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, 1848 1849{ "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, 1850{ "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, 1851 1852{ "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, 1853{ "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, 1854 1855{ "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, 1856{ "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, 1857 1858{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, 1859{ "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, 1860{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, 1861{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, 1862 1863{ "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, 1864{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, 1865 1866{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, 1867{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, 1868{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 1869{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } }, 1870 1871{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } }, 1872{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } }, 1873{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } }, 1874{ "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } }, 1875{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } }, 1876{ "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } }, 1877{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } }, 1878{ "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } }, 1879{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } }, 1880{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } }, 1881{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } }, 1882{ "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } }, 1883{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } }, 1884{ "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } }, 1885{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } }, 1886{ "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } }, 1887{ "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } }, 1888{ "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } }, 1889{ "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } }, 1890{ "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } }, 1891{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } }, 1892{ "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } }, 1893{ "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } }, 1894{ "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } }, 1895{ "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } }, 1896{ "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } }, 1897{ "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } }, 1898{ "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } }, 1899{ "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } }, 1900{ "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } }, 1901{ "t", X(31,4), X_MASK, POWER, { TO, RA, RB } }, 1902 1903{ "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } }, 1904{ "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } }, 1905{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, 1906{ "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } }, 1907{ "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } }, 1908{ "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } }, 1909{ "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } }, 1910{ "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } }, 1911{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, 1912{ "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } }, 1913{ "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } }, 1914{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, 1915 1916{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 1917{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 1918 1919{ "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } }, 1920{ "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } }, 1921{ "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } }, 1922{ "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } }, 1923{ "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } }, 1924{ "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } }, 1925{ "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } }, 1926{ "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } }, 1927 1928{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, 1929{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, 1930 1931{ "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } }, 1932 1933{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, 1934 1935{ "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } }, 1936 1937{ "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } }, 1938{ "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } }, 1939 1940{ "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } }, 1941{ "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } }, 1942{ "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } }, 1943{ "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } }, 1944 1945{ "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } }, 1946{ "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } }, 1947{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } }, 1948{ "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } }, 1949 1950{ "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } }, 1951{ "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } }, 1952 1953{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 1954{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 1955 1956{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } }, 1957{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } }, 1958 1959{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, 1960{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, 1961{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 1962{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } }, 1963 1964{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, 1965{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, 1966{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, 1967{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, 1968{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, 1969{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, 1970{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, 1971{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, 1972 1973{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } }, 1974 1975{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, 1976 1977{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } }, 1978{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } }, 1979 1980{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } }, 1981{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } }, 1982 1983{ "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 1984{ "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 1985 1986{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } }, 1987{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } }, 1988{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } }, 1989{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } }, 1990{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } }, 1991{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } }, 1992{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } }, 1993{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } }, 1994{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } }, 1995{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } }, 1996{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } }, 1997{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } }, 1998{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } }, 1999{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } }, 2000{ "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } }, 2001 2002{ "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2003{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2004 2005{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2006{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2007 2008{ "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } }, 2009 2010{ "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } }, 2011 2012{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, 2013 2014{ "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } }, 2015 2016{ "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } }, 2017{ "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } }, 2018{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } }, 2019{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } }, 2020 2021{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2022{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2023{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2024{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2025 2026{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } }, 2027 2028{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } }, 2029 2030{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, 2031{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 2032{ "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, 2033{ "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 2034 2035{ "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2036{ "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } }, 2037{ "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2038{ "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } }, 2039{ "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } }, 2040{ "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } }, 2041{ "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } }, 2042{ "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } }, 2043 2044{ "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2045{ "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } }, 2046{ "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2047{ "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } }, 2048{ "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } }, 2049{ "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } }, 2050{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } }, 2051{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } }, 2052 2053{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }}, 2054{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } }, 2055 2056{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } }, 2057 2058{ "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } }, 2059 2060{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, 2061 2062{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } }, 2063{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } }, 2064 2065{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2066{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2067 2068{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2069{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2070 2071{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } }, 2072 2073{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } }, 2074{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } }, 2075 2076{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } }, 2077{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } }, 2078 2079{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } }, 2080{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } }, 2081{ "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } }, 2082{ "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } }, 2083{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } }, 2084{ "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } }, 2085{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } }, 2086{ "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } }, 2087 2088{ "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } }, 2089{ "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } }, 2090{ "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } }, 2091{ "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } }, 2092{ "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } }, 2093{ "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } }, 2094{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } }, 2095{ "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } }, 2096 2097{ "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } }, 2098 2099{ "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } }, 2100 2101{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } }, 2102 2103{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2104{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2105 2106{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2107{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2108 2109{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } }, 2110{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } }, 2111{ "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } }, 2112{ "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } }, 2113{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } }, 2114{ "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } }, 2115{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } }, 2116{ "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } }, 2117 2118{ "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2119{ "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2120{ "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2121{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2122 2123{ "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } }, 2124{ "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } }, 2125{ "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } }, 2126{ "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } }, 2127{ "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } }, 2128{ "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } }, 2129{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } }, 2130{ "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } }, 2131 2132{ "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2133{ "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } }, 2134{ "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2135{ "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } }, 2136{ "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } }, 2137{ "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } }, 2138{ "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } }, 2139{ "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } }, 2140 2141{ "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } }, 2142{ "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } }, 2143 2144{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, 2145 2146{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } }, 2147 2148{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } }, 2149{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } }, 2150 2151{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2152{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2153{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2154{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2155 2156{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2157{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } }, 2158{ "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2159{ "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } }, 2160{ "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } }, 2161{ "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } }, 2162{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } }, 2163{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } }, 2164 2165{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } }, 2166{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } }, 2167 2168{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, 2169 2170{ "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } }, 2171 2172{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } }, 2173 2174{ "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 2175{ "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 2176 2177{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, 2178{ "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } }, 2179 2180{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, 2181 2182{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } }, 2183 2184{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 2185{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 2186 2187{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } }, 2188 2189{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2190{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2191{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2192{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2193 2194{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } }, 2195{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } }, 2196{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } }, 2197{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } }, 2198{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } }, 2199{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } }, 2200{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } }, 2201{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, 2202{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } }, 2203{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } }, 2204{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } }, 2205{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, 2206{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } }, 2207{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } }, 2208{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } }, 2209{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, 2210{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } }, 2211{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, 2212{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, 2213{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 2214{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 2215{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 2216{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 2217{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } }, 2218 2219{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } }, 2220 2221{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } }, 2222 2223{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } }, 2224 2225{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } }, 2226{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } }, 2227{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } }, 2228{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } }, 2229 2230{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2231{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2232{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, 2233{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, 2234 2235{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, 2236 2237{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, 2238{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, 2239 2240{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } }, 2241 2242{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } }, 2243 2244{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } }, 2245 2246{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, 2247 2248{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, 2249 2250{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, 2251 2252{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, 2253 2254{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 2255{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 2256 2257{ "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } }, 2258{ "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } }, 2259 2260{ "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } }, 2261 2262{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, 2263 2264{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } }, 2265 2266{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, 2267{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 2268{ "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, 2269{ "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 2270 2271{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } }, 2272 2273{ "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2274{ "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2275{ "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2276{ "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2277 2278{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2279{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2280{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, 2281{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, 2282 2283{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } }, 2284{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } }, 2285{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } }, 2286{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } }, 2287{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, 2288{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } }, 2289{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } }, 2290{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } }, 2291{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } }, 2292{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } }, 2293{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, 2294{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } }, 2295{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } }, 2296{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } }, 2297{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, 2298{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } }, 2299{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, 2300{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, 2301{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, 2302{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 2303{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 2304{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 2305{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 2306{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } }, 2307 2308{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, 2309 2310{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } }, 2311{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } }, 2312 2313{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } }, 2314{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } }, 2315{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } }, 2316{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } }, 2317 2318{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2319{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2320{ "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, 2321{ "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, 2322 2323{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, 2324{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, 2325{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, 2326{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, 2327 2328{ "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } }, 2329 2330{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, 2331 2332{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } }, 2333 2334{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } }, 2335 2336{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } }, 2337{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } }, 2338 2339{ "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } }, 2340{ "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } }, 2341 2342{ "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } }, 2343 2344{ "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } }, 2345{ "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } }, 2346{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } }, 2347{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } }, 2348 2349{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2350{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2351 2352{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } }, 2353{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } }, 2354 2355{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2356{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2357 2358{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 2359 2360{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } }, 2361 2362{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } }, 2363 2364{ "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } }, 2365{ "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } }, 2366 2367{ "sync", X(31,598), 0xffffffff, PPC, { 0 } }, 2368{ "dcs", X(31,598), 0xffffffff, POWER, { 0 } }, 2369 2370{ "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } }, 2371 2372{ "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } }, 2373 2374{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } }, 2375 2376{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } }, 2377 2378{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } }, 2379 2380{ "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } }, 2381{ "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } }, 2382 2383{ "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } }, 2384{ "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } }, 2385 2386{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } }, 2387 2388{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2389{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2390 2391{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2392{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2393 2394{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } }, 2395 2396{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } }, 2397{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } }, 2398 2399{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } }, 2400{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } }, 2401 2402{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } }, 2403 2404{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2405{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2406 2407{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2408{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2409 2410{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } }, 2411 2412{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } }, 2413{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } }, 2414 2415{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } }, 2416 2417{ "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } }, 2418{ "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } }, 2419{ "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } }, 2420{ "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } }, 2421 2422{ "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } }, 2423{ "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } }, 2424 2425{ "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } }, 2426 2427{ "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } }, 2428{ "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } }, 2429{ "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } }, 2430{ "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } }, 2431 2432{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, 2433 2434{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } }, 2435 2436{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2437{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2438 2439{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } }, 2440{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } }, 2441 2442{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } }, 2443{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } }, 2444{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } }, 2445{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } }, 2446 2447{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } }, 2448{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } }, 2449 2450{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, 2451{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, 2452 2453{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } }, 2454 2455{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 2456 2457{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, 2458 2459{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, 2460{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, 2461 2462{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 2463{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 2464 2465{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } }, 2466{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } }, 2467 2468{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } }, 2469{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } }, 2470 2471{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } }, 2472 2473{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } }, 2474 2475{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } }, 2476{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } }, 2477 2478{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } }, 2479{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } }, 2480 2481{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } }, 2482 2483{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } }, 2484 2485{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } }, 2486 2487{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } }, 2488 2489{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } }, 2490 2491{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } }, 2492 2493{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } }, 2494 2495{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } }, 2496 2497{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } }, 2498{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } }, 2499 2500{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } }, 2501{ "stm", OP(47), OP_MASK, POWER, { RS, D, RA } }, 2502 2503{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } }, 2504 2505{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } }, 2506 2507{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } }, 2508 2509{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } }, 2510 2511{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } }, 2512 2513{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } }, 2514 2515{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } }, 2516 2517{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } }, 2518 2519{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, 2520 2521{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, 2522 2523{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } }, 2524 2525{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } }, 2526 2527{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } }, 2528 2529{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2530{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2531 2532{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2533{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2534 2535{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2536{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2537 2538{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 2539{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 2540 2541{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 2542{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 2543 2544{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 2545{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 2546 2547{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2548{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2549 2550{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2551{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2552 2553{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2554{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2555 2556{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2557{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2558 2559{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 2560 2561{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 2562 2563{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } }, 2564 2565{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } }, 2566 2567{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, 2568 2569{ "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2570{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2571 2572{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } }, 2573{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, 2574{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } }, 2575{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, 2576 2577{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } }, 2578{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, 2579{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } }, 2580{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, 2581 2582{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2583{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, 2584{ "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2585{ "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, 2586 2587{ "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2588{ "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, 2589{ "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2590{ "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, 2591 2592{ "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2593{ "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, 2594{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 2595{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, 2596 2597{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, 2598{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, 2599 2600{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2601{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2602 2603{ "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 2604{ "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } }, 2605{ "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 2606{ "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } }, 2607 2608{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 2609{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 2610 2611{ "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2612{ "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2613{ "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2614{ "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2615 2616{ "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2617{ "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2618{ "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2619{ "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2620 2621{ "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2622{ "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2623{ "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2624{ "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2625 2626{ "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2627{ "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2628{ "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 2629{ "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, 2630 2631{ "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, 2632 2633{ "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } }, 2634{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } }, 2635 2636{ "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2637{ "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2638 2639{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, 2640 2641{ "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } }, 2642{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } }, 2643 2644{ "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2645{ "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2646 2647{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, 2648{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, 2649 2650{ "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2651{ "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2652 2653{ "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2654{ "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, 2655 2656{ "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } }, 2657{ "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } }, 2658 2659{ "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } }, 2660{ "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } }, 2661 2662{ "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } }, 2663{ "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } }, 2664 2665{ "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } }, 2666{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } }, 2667 2668{ "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } }, 2669{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } }, 2670 2671}; 2672 2673const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes); 2674 2675/* The macro table. This is only used by the assembler. */ 2676 2677const struct powerpc_macro powerpc_macros[] = { 2678{ "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" }, 2679{ "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" }, 2680{ "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, 2681{ "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, 2682{ "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, 2683{ "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, 2684{ "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" }, 2685{ "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" }, 2686{ "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" }, 2687{ "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" }, 2688{ "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" }, 2689{ "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" }, 2690{ "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" }, 2691{ "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" }, 2692{ "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" }, 2693{ "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" }, 2694 2695{ "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" }, 2696{ "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" }, 2697{ "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, 2698{ "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, 2699{ "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" }, 2700{ "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" }, 2701{ "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, 2702{ "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 2703{ "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" }, 2704{ "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" }, 2705{ "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" }, 2706{ "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" }, 2707{ "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" }, 2708{ "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" }, 2709{ "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" }, 2710{ "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" }, 2711{ "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" }, 2712{ "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" }, 2713{ "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" }, 2714{ "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" }, 2715{ "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, 2716{ "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, 2717 2718}; 2719 2720const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros); 2721