Searched refs:NV_RD32 (Results 1 - 10 of 10) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/riva/
H A Dnv_driver.c65 reg52C = NV_RD32(PRAMDAC, 0x052C);
66 reg608 = NV_RD32(PRAMDAC, 0x0608);
72 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
79 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
82 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
144 if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
150 if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
170 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
171 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
172 && ((NV_RD32(chi
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H A Driva_hw.c65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
622 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
629 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
811 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
814 pll = NV_RD32(
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H A Driva_hw.h83 #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) macro
558 (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
H A Dfbdev.c320 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
321 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
803 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
810 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
812 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
818 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
820 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
823 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/nvidia/
H A Dnv_setup.c151 reg52C = NV_RD32(PRAMDAC, 0x052C);
152 reg608 = NV_RD32(PRAMDAC, 0x0608);
158 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
161 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
166 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
173 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
199 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
201 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
204 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
220 par->CrystalFreqKHz = (NV_RD32(pa
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H A Dnv_hw.c83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
147 pll = NV_RD32(par->PMC, 0x4020);
149 pll = NV_RD32(par->PMC, 0x4024);
163 pll = NV_RD32(par->PMC, 0x4000);
165 pll = NV_RD32(par->PMC, 0x4004);
173 pll = NV_RD32(par->PRAMDAC0, 0x0504);
177 pll = NV_RD32(par->PRAMDAC0, 0x0574);
187 pll = NV_RD32(par->PRAMDAC0, 0x0500);
191 pll = NV_RD32(par->PRAMDAC0, 0x0570);
203 pll = NV_RD32(pa
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H A Dnv_backlight.c66 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
67 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
68 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
H A Dnv_local.h67 #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) macro
96 #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
H A Dnvidia.c425 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
435 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
451 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
452 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
455 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
457 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
459 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
460 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
462 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
464 state->vpll2B = NV_RD32(pa
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H A Dnv_accel.c99 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;

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