1 /***************************************************************************\
2|*                                                                           *|
3|*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
4|*                                                                           *|
5|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
6|*     international laws.  Users and possessors of this source code are     *|
7|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
8|*     use this code in individual and commercial software.                  *|
9|*                                                                           *|
10|*     Any use of this source code must include,  in the user documenta-     *|
11|*     tion and  internal comments to the code,  notices to the end user     *|
12|*     as follows:                                                           *|
13|*                                                                           *|
14|*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
15|*                                                                           *|
16|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
17|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
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19|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
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27|*                                                                           *|
28|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
29|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
30|*     consisting  of "commercial  computer  software"  and  "commercial     *|
31|*     computer  software  documentation,"  as such  terms  are  used in     *|
32|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
33|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
34|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
35|*     all U.S. Government End Users  acquire the source code  with only     *|
36|*     those rights set forth herein.                                        *|
37|*                                                                           *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#include <video/vga.h>
51#include <linux/delay.h>
52#include <linux/pci.h>
53#include "nv_type.h"
54#include "nv_local.h"
55#include "nv_proto.h"
56/*
57 * Override VGA I/O routines.
58 */
59void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
60{
61	VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
62	VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
63}
64u8 NVReadCrtc(struct nvidia_par *par, u8 index)
65{
66	VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
67	return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
68}
69void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
70{
71	VGA_WR08(par->PVIO, VGA_GFX_I, index);
72	VGA_WR08(par->PVIO, VGA_GFX_D, value);
73}
74u8 NVReadGr(struct nvidia_par *par, u8 index)
75{
76	VGA_WR08(par->PVIO, VGA_GFX_I, index);
77	return (VGA_RD08(par->PVIO, VGA_GFX_D));
78}
79void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
80{
81	VGA_WR08(par->PVIO, VGA_SEQ_I, index);
82	VGA_WR08(par->PVIO, VGA_SEQ_D, value);
83}
84u8 NVReadSeq(struct nvidia_par *par, u8 index)
85{
86	VGA_WR08(par->PVIO, VGA_SEQ_I, index);
87	return (VGA_RD08(par->PVIO, VGA_SEQ_D));
88}
89void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
90{
91	volatile u8 tmp;
92
93	tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
94	if (par->paletteEnabled)
95		index &= ~0x20;
96	else
97		index |= 0x20;
98	VGA_WR08(par->PCIO, VGA_ATT_IW, index);
99	VGA_WR08(par->PCIO, VGA_ATT_W, value);
100}
101u8 NVReadAttr(struct nvidia_par *par, u8 index)
102{
103	volatile u8 tmp;
104
105	tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
106	if (par->paletteEnabled)
107		index &= ~0x20;
108	else
109		index |= 0x20;
110	VGA_WR08(par->PCIO, VGA_ATT_IW, index);
111	return (VGA_RD08(par->PCIO, VGA_ATT_R));
112}
113void NVWriteMiscOut(struct nvidia_par *par, u8 value)
114{
115	VGA_WR08(par->PVIO, VGA_MIS_W, value);
116}
117u8 NVReadMiscOut(struct nvidia_par *par)
118{
119	return (VGA_RD08(par->PVIO, VGA_MIS_R));
120}
121void NVWriteDacMask(struct nvidia_par *par, u8 value)
122{
123	VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
124}
125void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
126{
127	VGA_WR08(par->PDIO, VGA_PEL_IR, value);
128}
129void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
130{
131	VGA_WR08(par->PDIO, VGA_PEL_IW, value);
132}
133void NVWriteDacData(struct nvidia_par *par, u8 value)
134{
135	VGA_WR08(par->PDIO, VGA_PEL_D, value);
136}
137u8 NVReadDacData(struct nvidia_par *par)
138{
139	return (VGA_RD08(par->PDIO, VGA_PEL_D));
140}
141
142static int NVIsConnected(struct nvidia_par *par, int output)
143{
144	volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
145	u32 reg52C, reg608;
146	int present;
147
148	if (output)
149		PRAMDAC += 0x800;
150
151	reg52C = NV_RD32(PRAMDAC, 0x052C);
152	reg608 = NV_RD32(PRAMDAC, 0x0608);
153
154	NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
155
156	NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
157	msleep(1);
158	NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
159
160	NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
161	NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
162		0x00001000);
163
164	msleep(1);
165
166	present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
167
168	if (present)
169		printk("nvidiafb: CRTC%i analog found\n", output);
170	else
171		printk("nvidiafb: CRTC%i analog not found\n", output);
172
173	NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
174		0x0000EFFF);
175
176	NV_WR32(PRAMDAC, 0x052C, reg52C);
177	NV_WR32(PRAMDAC, 0x0608, reg608);
178
179	return present;
180}
181
182static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
183{
184	if (head) {
185		par->PCIO = par->PCIO0 + 0x2000;
186		par->PCRTC = par->PCRTC0 + 0x800;
187		par->PRAMDAC = par->PRAMDAC0 + 0x800;
188		par->PDIO = par->PDIO0 + 0x2000;
189	} else {
190		par->PCIO = par->PCIO0;
191		par->PCRTC = par->PCRTC0;
192		par->PRAMDAC = par->PRAMDAC0;
193		par->PDIO = par->PDIO0;
194	}
195}
196
197static void nv4GetConfig(struct nvidia_par *par)
198{
199	if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
200		par->RamAmountKBytes =
201		    ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
202		    1024 * 2;
203	} else {
204		switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
205		case 0:
206			par->RamAmountKBytes = 1024 * 32;
207			break;
208		case 1:
209			par->RamAmountKBytes = 1024 * 4;
210			break;
211		case 2:
212			par->RamAmountKBytes = 1024 * 8;
213			break;
214		case 3:
215		default:
216			par->RamAmountKBytes = 1024 * 16;
217			break;
218		}
219	}
220	par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
221	    14318 : 13500;
222	par->CURSOR = &par->PRAMIN[0x1E00];
223	par->MinVClockFreqKHz = 12000;
224	par->MaxVClockFreqKHz = 350000;
225}
226
227static void nv10GetConfig(struct nvidia_par *par)
228{
229	struct pci_dev *dev;
230	u32 implementation = par->Chipset & 0x0ff0;
231
232#ifdef __BIG_ENDIAN
233	/* turn on big endian register access */
234	if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
235		NV_WR32(par->PMC, 0x0004, 0x01000001);
236		mb();
237	}
238#endif
239
240	dev = pci_get_bus_and_slot(0, 1);
241	if ((par->Chipset & 0xffff) == 0x01a0) {
242		int amt = 0;
243
244		pci_read_config_dword(dev, 0x7c, &amt);
245		par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
246	} else if ((par->Chipset & 0xffff) == 0x01f0) {
247		int amt = 0;
248
249		pci_read_config_dword(dev, 0x84, &amt);
250		par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
251	} else {
252		par->RamAmountKBytes =
253		    (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
254	}
255	pci_dev_put(dev);
256
257	par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
258	    14318 : 13500;
259
260	if (par->twoHeads && (implementation != 0x0110)) {
261		if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
262			par->CrystalFreqKHz = 27000;
263	}
264
265	par->CURSOR = NULL;	/* can't set this here */
266	par->MinVClockFreqKHz = 12000;
267	par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
268}
269
270int NVCommonSetup(struct fb_info *info)
271{
272	struct nvidia_par *par = info->par;
273	struct fb_var_screeninfo *var;
274	u16 implementation = par->Chipset & 0x0ff0;
275	u8 *edidA = NULL, *edidB = NULL;
276	struct fb_monspecs *monitorA, *monitorB;
277	struct fb_monspecs *monA = NULL, *monB = NULL;
278	int mobile = 0;
279	int tvA = 0;
280	int tvB = 0;
281	int FlatPanel = -1;	/* really means the CRTC is slaved */
282	int Television = 0;
283	int err = 0;
284
285	var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
286	monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
287	monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
288
289	if (!var || !monitorA || !monitorB) {
290		err = -ENOMEM;
291		goto done;
292	}
293
294	par->PRAMIN = par->REGS + (0x00710000 / 4);
295	par->PCRTC0 = par->REGS + (0x00600000 / 4);
296	par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
297	par->PFB = par->REGS + (0x00100000 / 4);
298	par->PFIFO = par->REGS + (0x00002000 / 4);
299	par->PGRAPH = par->REGS + (0x00400000 / 4);
300	par->PEXTDEV = par->REGS + (0x00101000 / 4);
301	par->PTIMER = par->REGS + (0x00009000 / 4);
302	par->PMC = par->REGS + (0x00000000 / 4);
303	par->FIFO = par->REGS + (0x00800000 / 4);
304
305	/* 8 bit registers */
306	par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
307	par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
308	par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
309
310	par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
311	    (implementation != 0x0100) &&
312	    (implementation != 0x0150) &&
313	    (implementation != 0x01A0) && (implementation != 0x0200);
314
315	par->fpScaler = (par->FpScale && par->twoHeads &&
316			 (implementation != 0x0110));
317
318	par->twoStagePLL = (implementation == 0x0310) ||
319	    (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
320
321	par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
322	    (implementation != 0x0100);
323
324	par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
325
326	/* look for known laptop chips */
327	switch (par->Chipset & 0xffff) {
328	case 0x0112:
329	case 0x0174:
330	case 0x0175:
331	case 0x0176:
332	case 0x0177:
333	case 0x0179:
334	case 0x017C:
335	case 0x017D:
336	case 0x0186:
337	case 0x0187:
338	case 0x018D:
339	case 0x0228:
340	case 0x0286:
341	case 0x028C:
342	case 0x0316:
343	case 0x0317:
344	case 0x031A:
345	case 0x031B:
346	case 0x031C:
347	case 0x031D:
348	case 0x031E:
349	case 0x031F:
350	case 0x0324:
351	case 0x0325:
352	case 0x0328:
353	case 0x0329:
354	case 0x032C:
355	case 0x032D:
356	case 0x0347:
357	case 0x0348:
358	case 0x0349:
359	case 0x034B:
360	case 0x034C:
361	case 0x0160:
362	case 0x0166:
363	case 0x0169:
364	case 0x016B:
365	case 0x016C:
366	case 0x016D:
367	case 0x00C8:
368	case 0x00CC:
369	case 0x0144:
370	case 0x0146:
371	case 0x0147:
372	case 0x0148:
373	case 0x0098:
374	case 0x0099:
375		mobile = 1;
376		break;
377	default:
378		break;
379	}
380
381	if (par->Architecture == NV_ARCH_04)
382		nv4GetConfig(par);
383	else
384		nv10GetConfig(par);
385
386	NVSelectHeadRegisters(par, 0);
387
388	NVLockUnlock(par, 0);
389
390	par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
391
392	par->Television = 0;
393
394	nvidia_create_i2c_busses(par);
395	if (!par->twoHeads) {
396		par->CRTCnumber = 0;
397		if (nvidia_probe_i2c_connector(info, 1, &edidA))
398			nvidia_probe_of_connector(info, 1, &edidA);
399		if (edidA && !fb_parse_edid(edidA, var)) {
400			printk("nvidiafb: EDID found from BUS1\n");
401			monA = monitorA;
402			fb_edid_to_monspecs(edidA, monA);
403			FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
404
405			/* NV4 doesn't support FlatPanels */
406			if ((par->Chipset & 0x0fff) <= 0x0020)
407				FlatPanel = 0;
408		} else {
409			VGA_WR08(par->PCIO, 0x03D4, 0x28);
410			if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
411				VGA_WR08(par->PCIO, 0x03D4, 0x33);
412				if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
413					Television = 1;
414				FlatPanel = 1;
415			} else {
416				FlatPanel = 0;
417			}
418			printk("nvidiafb: HW is currently programmed for %s\n",
419			       FlatPanel ? (Television ? "TV" : "DFP") :
420			       "CRT");
421		}
422
423		if (par->FlatPanel == -1) {
424			par->FlatPanel = FlatPanel;
425			par->Television = Television;
426		} else {
427			printk("nvidiafb: Forcing display type to %s as "
428			       "specified\n", par->FlatPanel ? "DFP" : "CRT");
429		}
430	} else {
431		u8 outputAfromCRTC, outputBfromCRTC;
432		int CRTCnumber = -1;
433		u8 slaved_on_A, slaved_on_B;
434		int analog_on_A, analog_on_B;
435		u32 oldhead;
436		u8 cr44;
437
438		if (implementation != 0x0110) {
439			if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
440				outputAfromCRTC = 1;
441			else
442				outputAfromCRTC = 0;
443			if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
444				outputBfromCRTC = 1;
445			else
446				outputBfromCRTC = 0;
447			analog_on_A = NVIsConnected(par, 0);
448			analog_on_B = NVIsConnected(par, 1);
449		} else {
450			outputAfromCRTC = 0;
451			outputBfromCRTC = 1;
452			analog_on_A = 0;
453			analog_on_B = 0;
454		}
455
456		VGA_WR08(par->PCIO, 0x03D4, 0x44);
457		cr44 = VGA_RD08(par->PCIO, 0x03D5);
458
459		VGA_WR08(par->PCIO, 0x03D5, 3);
460		NVSelectHeadRegisters(par, 1);
461		NVLockUnlock(par, 0);
462
463		VGA_WR08(par->PCIO, 0x03D4, 0x28);
464		slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
465		if (slaved_on_B) {
466			VGA_WR08(par->PCIO, 0x03D4, 0x33);
467			tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
468		}
469
470		VGA_WR08(par->PCIO, 0x03D4, 0x44);
471		VGA_WR08(par->PCIO, 0x03D5, 0);
472		NVSelectHeadRegisters(par, 0);
473		NVLockUnlock(par, 0);
474
475		VGA_WR08(par->PCIO, 0x03D4, 0x28);
476		slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
477		if (slaved_on_A) {
478			VGA_WR08(par->PCIO, 0x03D4, 0x33);
479			tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
480		}
481
482		oldhead = NV_RD32(par->PCRTC0, 0x00000860);
483		NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
484
485		if (nvidia_probe_i2c_connector(info, 1, &edidA))
486			nvidia_probe_of_connector(info, 1, &edidA);
487		if (edidA && !fb_parse_edid(edidA, var)) {
488			printk("nvidiafb: EDID found from BUS1\n");
489			monA = monitorA;
490			fb_edid_to_monspecs(edidA, monA);
491		}
492
493		if (nvidia_probe_i2c_connector(info, 2, &edidB))
494			nvidia_probe_of_connector(info, 2, &edidB);
495		if (edidB && !fb_parse_edid(edidB, var)) {
496			printk("nvidiafb: EDID found from BUS2\n");
497			monB = monitorB;
498			fb_edid_to_monspecs(edidB, monB);
499		}
500
501		if (slaved_on_A && !tvA) {
502			CRTCnumber = 0;
503			FlatPanel = 1;
504			printk("nvidiafb: CRTC 0 is currently programmed for "
505			       "DFP\n");
506		} else if (slaved_on_B && !tvB) {
507			CRTCnumber = 1;
508			FlatPanel = 1;
509			printk("nvidiafb: CRTC 1 is currently programmed "
510			       "for DFP\n");
511		} else if (analog_on_A) {
512			CRTCnumber = outputAfromCRTC;
513			FlatPanel = 0;
514			printk("nvidiafb: CRTC %i appears to have a "
515			       "CRT attached\n", CRTCnumber);
516		} else if (analog_on_B) {
517			CRTCnumber = outputBfromCRTC;
518			FlatPanel = 0;
519			printk("nvidiafb: CRTC %i"
520			       "appears to have a "
521			       "CRT attached\n", CRTCnumber);
522		} else if (slaved_on_A) {
523			CRTCnumber = 0;
524			FlatPanel = 1;
525			Television = 1;
526			printk("nvidiafb: CRTC 0 is currently programmed "
527			       "for TV\n");
528		} else if (slaved_on_B) {
529			CRTCnumber = 1;
530			FlatPanel = 1;
531			Television = 1;
532			printk("nvidiafb: CRTC 1 is currently programmed for "
533			       "TV\n");
534		} else if (monA) {
535			FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
536		} else if (monB) {
537			FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
538		}
539
540		if (par->FlatPanel == -1) {
541			if (FlatPanel != -1) {
542				par->FlatPanel = FlatPanel;
543				par->Television = Television;
544			} else {
545				printk("nvidiafb: Unable to detect display "
546				       "type...\n");
547				if (mobile) {
548					printk("...On a laptop, assuming "
549					       "DFP\n");
550					par->FlatPanel = 1;
551				} else {
552					printk("...Using default of CRT\n");
553					par->FlatPanel = 0;
554				}
555			}
556		} else {
557			printk("nvidiafb: Forcing display type to %s as "
558			       "specified\n", par->FlatPanel ? "DFP" : "CRT");
559		}
560
561		if (par->CRTCnumber == -1) {
562			if (CRTCnumber != -1)
563				par->CRTCnumber = CRTCnumber;
564			else {
565				printk("nvidiafb: Unable to detect which "
566				       "CRTCNumber...\n");
567				if (par->FlatPanel)
568					par->CRTCnumber = 1;
569				else
570					par->CRTCnumber = 0;
571				printk("...Defaulting to CRTCNumber %i\n",
572				       par->CRTCnumber);
573			}
574		} else {
575			printk("nvidiafb: Forcing CRTCNumber %i as "
576			       "specified\n", par->CRTCnumber);
577		}
578
579		if (monA) {
580			if (((monA->input & FB_DISP_DDI) &&
581			     par->FlatPanel) ||
582			    ((!(monA->input & FB_DISP_DDI)) &&
583			     !par->FlatPanel)) {
584				if (monB) {
585					fb_destroy_modedb(monB->modedb);
586					monB = NULL;
587				}
588			} else {
589				fb_destroy_modedb(monA->modedb);
590				monA = NULL;
591			}
592		}
593
594		if (monB) {
595			if (((monB->input & FB_DISP_DDI) &&
596			     !par->FlatPanel) ||
597			    ((!(monB->input & FB_DISP_DDI)) &&
598			     par->FlatPanel)) {
599				fb_destroy_modedb(monB->modedb);
600				monB = NULL;
601			} else
602				monA = monB;
603		}
604
605		if (implementation == 0x0110)
606			cr44 = par->CRTCnumber * 0x3;
607
608		NV_WR32(par->PCRTC0, 0x00000860, oldhead);
609
610		VGA_WR08(par->PCIO, 0x03D4, 0x44);
611		VGA_WR08(par->PCIO, 0x03D5, cr44);
612		NVSelectHeadRegisters(par, par->CRTCnumber);
613	}
614
615	printk("nvidiafb: Using %s on CRTC %i\n",
616	       par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
617	       par->CRTCnumber);
618
619	if (par->FlatPanel && !par->Television) {
620		par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
621		par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
622		par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
623
624		printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
625	}
626
627	if (monA)
628		info->monspecs = *monA;
629
630	if (!par->FlatPanel || !par->twoHeads)
631		par->FPDither = 0;
632
633	par->LVDS = 0;
634	if (par->FlatPanel && par->twoHeads) {
635		NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
636		if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
637			par->LVDS = 1;
638		printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
639	}
640
641	kfree(edidA);
642	kfree(edidB);
643done:
644	kfree(var);
645	kfree(monitorA);
646	kfree(monitorB);
647	return err;
648}
649