1/* 2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver 3 * 4 * Copyright 2004 Antonino Daplas <adaplas@pol.net> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 * 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/errno.h> 15#include <linux/string.h> 16#include <linux/mm.h> 17#include <linux/slab.h> 18#include <linux/delay.h> 19#include <linux/fb.h> 20#include <linux/init.h> 21#include <linux/pci.h> 22#include <linux/console.h> 23#include <linux/backlight.h> 24#ifdef CONFIG_MTRR 25#include <asm/mtrr.h> 26#endif 27#ifdef CONFIG_PPC_OF 28#include <asm/prom.h> 29#include <asm/pci-bridge.h> 30#endif 31#ifdef CONFIG_BOOTX_TEXT 32#include <asm/btext.h> 33#endif 34 35#include "nv_local.h" 36#include "nv_type.h" 37#include "nv_proto.h" 38#include "nv_dma.h" 39 40#ifdef CONFIG_FB_NVIDIA_DEBUG 41#define NVTRACE printk 42#else 43#define NVTRACE if (0) printk 44#endif 45 46#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__) 47#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__) 48 49#ifdef CONFIG_FB_NVIDIA_DEBUG 50#define assert(expr) \ 51 if (!(expr)) { \ 52 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 53 #expr,__FILE__,__FUNCTION__,__LINE__); \ 54 BUG(); \ 55 } 56#else 57#define assert(expr) 58#endif 59 60#define PFX "nvidiafb: " 61 62/* HW cursor parameters */ 63#define MAX_CURS 32 64 65static struct pci_device_id nvidiafb_pci_tbl[] = { 66 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 67 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0}, 68 { 0, } 69}; 70MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl); 71 72/* command line data, set in nvidiafb_setup() */ 73static int flatpanel __devinitdata = -1; /* Autodetect later */ 74static int fpdither __devinitdata = -1; 75static int forceCRTC __devinitdata = -1; 76static int hwcur __devinitdata = 0; 77static int noaccel __devinitdata = 0; 78static int noscale __devinitdata = 0; 79static int paneltweak __devinitdata = 0; 80static int vram __devinitdata = 0; 81static int bpp __devinitdata = 8; 82#ifdef CONFIG_MTRR 83static int nomtrr __devinitdata = 0; 84#endif 85#ifdef CONFIG_PMAC_BACKLIGHT 86static int backlight __devinitdata = 1; 87#else 88static int backlight __devinitdata = 0; 89#endif 90 91static char *mode_option __devinitdata = NULL; 92 93static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = { 94 .type = FB_TYPE_PACKED_PIXELS, 95 .xpanstep = 8, 96 .ypanstep = 1, 97}; 98 99static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = { 100 .xres = 640, 101 .yres = 480, 102 .xres_virtual = 640, 103 .yres_virtual = 480, 104 .bits_per_pixel = 8, 105 .red = {0, 8, 0}, 106 .green = {0, 8, 0}, 107 .blue = {0, 8, 0}, 108 .transp = {0, 0, 0}, 109 .activate = FB_ACTIVATE_NOW, 110 .height = -1, 111 .width = -1, 112 .pixclock = 39721, 113 .left_margin = 40, 114 .right_margin = 24, 115 .upper_margin = 32, 116 .lower_margin = 11, 117 .hsync_len = 96, 118 .vsync_len = 2, 119 .vmode = FB_VMODE_NONINTERLACED 120}; 121 122static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, 123 u16 bg, u16 fg, u32 w, u32 h) 124{ 125 u32 *data = (u32 *) data8; 126 int i, j, k = 0; 127 u32 b, tmp; 128 129 w = (w + 1) & ~1; 130 131 for (i = 0; i < h; i++) { 132 b = *data++; 133 reverse_order(&b); 134 135 for (j = 0; j < w / 2; j++) { 136 tmp = 0; 137#if defined(__BIG_ENDIAN) 138 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 139 b <<= 1; 140 tmp |= (b & (1 << 31)) ? fg : bg; 141 b <<= 1; 142#else 143 tmp = (b & 1) ? fg : bg; 144 b >>= 1; 145 tmp |= (b & 1) ? fg << 16 : bg << 16; 146 b >>= 1; 147#endif 148 NV_WR32(&par->CURSOR[k++], 0, tmp); 149 } 150 k += (MAX_CURS - w) / 2; 151 } 152} 153 154static void nvidia_write_clut(struct nvidia_par *par, 155 u8 regnum, u8 red, u8 green, u8 blue) 156{ 157 NVWriteDacMask(par, 0xff); 158 NVWriteDacWriteAddr(par, regnum); 159 NVWriteDacData(par, red); 160 NVWriteDacData(par, green); 161 NVWriteDacData(par, blue); 162} 163 164static void nvidia_read_clut(struct nvidia_par *par, 165 u8 regnum, u8 * red, u8 * green, u8 * blue) 166{ 167 NVWriteDacMask(par, 0xff); 168 NVWriteDacReadAddr(par, regnum); 169 *red = NVReadDacData(par); 170 *green = NVReadDacData(par); 171 *blue = NVReadDacData(par); 172} 173 174static int nvidia_panel_tweak(struct nvidia_par *par, 175 struct _riva_hw_state *state) 176{ 177 int tweak = 0; 178 179 if (par->paneltweak) { 180 tweak = par->paneltweak; 181 } else { 182 /* begin flat panel hacks */ 183 /* This is unfortunate, but some chips need this register 184 tweaked or else you get artifacts where adjacent pixels are 185 swapped. There are no hard rules for what to set here so all 186 we can do is experiment and apply hacks. */ 187 188 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { 189 tweak = -1; 190 } 191 192 if((par->Chipset & 0xfff0) == 0x0310) { 193 tweak = 1; 194 } 195 /* end flat panel hacks */ 196 } 197 198 return tweak; 199} 200 201static void nvidia_screen_off(struct nvidia_par *par, int on) 202{ 203 unsigned char tmp; 204 205 if (on) { 206 /* 207 * Turn off screen and disable sequencer. 208 */ 209 tmp = NVReadSeq(par, 0x01); 210 211 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ 212 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ 213 } else { 214 /* 215 * Reenable sequencer, then turn on screen. 216 */ 217 218 tmp = NVReadSeq(par, 0x01); 219 220 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ 221 NVWriteSeq(par, 0x00, 0x03); /* End Reset */ 222 } 223} 224 225static void nvidia_save_vga(struct nvidia_par *par, 226 struct _riva_hw_state *state) 227{ 228 int i; 229 230 NVTRACE_ENTER(); 231 NVLockUnlock(par, 0); 232 233 NVUnloadStateExt(par, state); 234 235 state->misc_output = NVReadMiscOut(par); 236 237 for (i = 0; i < NUM_CRT_REGS; i++) 238 state->crtc[i] = NVReadCrtc(par, i); 239 240 for (i = 0; i < NUM_ATC_REGS; i++) 241 state->attr[i] = NVReadAttr(par, i); 242 243 for (i = 0; i < NUM_GRC_REGS; i++) 244 state->gra[i] = NVReadGr(par, i); 245 246 for (i = 0; i < NUM_SEQ_REGS; i++) 247 state->seq[i] = NVReadSeq(par, i); 248 NVTRACE_LEAVE(); 249} 250 251#undef DUMP_REG 252 253static void nvidia_write_regs(struct nvidia_par *par, 254 struct _riva_hw_state *state) 255{ 256 int i; 257 258 NVTRACE_ENTER(); 259 260 NVLoadStateExt(par, state); 261 262 NVWriteMiscOut(par, state->misc_output); 263 264 for (i = 1; i < NUM_SEQ_REGS; i++) { 265#ifdef DUMP_REG 266 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); 267#endif 268 NVWriteSeq(par, i, state->seq[i]); 269 } 270 271 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ 272 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); 273 274 for (i = 0; i < NUM_CRT_REGS; i++) { 275 switch (i) { 276 case 0x19: 277 case 0x20 ... 0x40: 278 break; 279 default: 280#ifdef DUMP_REG 281 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); 282#endif 283 NVWriteCrtc(par, i, state->crtc[i]); 284 } 285 } 286 287 for (i = 0; i < NUM_GRC_REGS; i++) { 288#ifdef DUMP_REG 289 printk(" GRA[%02x] = %08x\n", i, state->gra[i]); 290#endif 291 NVWriteGr(par, i, state->gra[i]); 292 } 293 294 for (i = 0; i < NUM_ATC_REGS; i++) { 295#ifdef DUMP_REG 296 printk("ATTR[%02x] = %08x\n", i, state->attr[i]); 297#endif 298 NVWriteAttr(par, i, state->attr[i]); 299 } 300 301 NVTRACE_LEAVE(); 302} 303 304static int nvidia_calc_regs(struct fb_info *info) 305{ 306 struct nvidia_par *par = info->par; 307 struct _riva_hw_state *state = &par->ModeReg; 308 int i, depth = fb_get_color_depth(&info->var, &info->fix); 309 int h_display = info->var.xres / 8 - 1; 310 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; 311 int h_end = (info->var.xres + info->var.right_margin + 312 info->var.hsync_len) / 8 - 1; 313 int h_total = (info->var.xres + info->var.right_margin + 314 info->var.hsync_len + info->var.left_margin) / 8 - 5; 315 int h_blank_s = h_display; 316 int h_blank_e = h_total + 4; 317 int v_display = info->var.yres - 1; 318 int v_start = info->var.yres + info->var.lower_margin - 1; 319 int v_end = (info->var.yres + info->var.lower_margin + 320 info->var.vsync_len) - 1; 321 int v_total = (info->var.yres + info->var.lower_margin + 322 info->var.vsync_len + info->var.upper_margin) - 2; 323 int v_blank_s = v_display; 324 int v_blank_e = v_total + 1; 325 326 /* 327 * Set all CRTC values. 328 */ 329 330 if (info->var.vmode & FB_VMODE_INTERLACED) 331 v_total |= 1; 332 333 if (par->FlatPanel == 1) { 334 v_start = v_total - 3; 335 v_end = v_total - 2; 336 v_blank_s = v_start; 337 h_start = h_total - 5; 338 h_end = h_total - 2; 339 h_blank_e = h_total + 4; 340 } 341 342 state->crtc[0x0] = Set8Bits(h_total); 343 state->crtc[0x1] = Set8Bits(h_display); 344 state->crtc[0x2] = Set8Bits(h_blank_s); 345 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) 346 | SetBit(7); 347 state->crtc[0x4] = Set8Bits(h_start); 348 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) 349 | SetBitField(h_end, 4: 0, 4:0); 350 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); 351 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) 352 | SetBitField(v_display, 8: 8, 1:1) 353 | SetBitField(v_start, 8: 8, 2:2) 354 | SetBitField(v_blank_s, 8: 8, 3:3) 355 | SetBit(4) 356 | SetBitField(v_total, 9: 9, 5:5) 357 | SetBitField(v_display, 9: 9, 6:6) 358 | SetBitField(v_start, 9: 9, 7:7); 359 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) 360 | SetBit(6) 361 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); 362 state->crtc[0x10] = Set8Bits(v_start); 363 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); 364 state->crtc[0x12] = Set8Bits(v_display); 365 state->crtc[0x13] = ((info->var.xres_virtual / 8) * 366 (info->var.bits_per_pixel / 8)); 367 state->crtc[0x15] = Set8Bits(v_blank_s); 368 state->crtc[0x16] = Set8Bits(v_blank_e); 369 370 state->attr[0x10] = 0x01; 371 372 if (par->Television) 373 state->attr[0x11] = 0x00; 374 375 state->screen = SetBitField(h_blank_e, 6: 6, 4:4) 376 | SetBitField(v_blank_s, 10: 10, 3:3) 377 | SetBitField(v_start, 10: 10, 2:2) 378 | SetBitField(v_display, 10: 10, 1:1) 379 | SetBitField(v_total, 10: 10, 0:0); 380 381 state->horiz = SetBitField(h_total, 8: 8, 0:0) 382 | SetBitField(h_display, 8: 8, 1:1) 383 | SetBitField(h_blank_s, 8: 8, 2:2) 384 | SetBitField(h_start, 8: 8, 3:3); 385 386 state->extra = SetBitField(v_total, 11: 11, 0:0) 387 | SetBitField(v_display, 11: 11, 2:2) 388 | SetBitField(v_start, 11: 11, 4:4) 389 | SetBitField(v_blank_s, 11: 11, 6:6); 390 391 if (info->var.vmode & FB_VMODE_INTERLACED) { 392 h_total = (h_total >> 1) & ~1; 393 state->interlace = Set8Bits(h_total); 394 state->horiz |= SetBitField(h_total, 8: 8, 4:4); 395 } else { 396 state->interlace = 0xff; /* interlace off */ 397 } 398 399 /* 400 * Calculate the extended registers. 401 */ 402 403 if (depth < 24) 404 i = depth; 405 else 406 i = 32; 407 408 if (par->Architecture >= NV_ARCH_10) 409 par->CURSOR = (volatile u32 __iomem *)(info->screen_base + 410 par->CursorStart); 411 412 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 413 state->misc_output &= ~0x40; 414 else 415 state->misc_output |= 0x40; 416 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 417 state->misc_output &= ~0x80; 418 else 419 state->misc_output |= 0x80; 420 421 NVCalcStateExt(par, state, i, info->var.xres_virtual, 422 info->var.xres, info->var.yres_virtual, 423 1000000000 / info->var.pixclock, info->var.vmode); 424 425 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; 426 if (par->FlatPanel == 1) { 427 state->pixel |= (1 << 7); 428 429 if (!par->fpScaler || (par->fpWidth <= info->var.xres) 430 || (par->fpHeight <= info->var.yres)) { 431 state->scale |= (1 << 8); 432 } 433 434 if (!par->crtcSync_read) { 435 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); 436 par->crtcSync_read = 1; 437 } 438 439 par->PanelTweak = nvidia_panel_tweak(par, state); 440 } 441 442 state->vpll = state->pll; 443 state->vpll2 = state->pll; 444 state->vpllB = state->pllB; 445 state->vpll2B = state->pllB; 446 447 VGA_WR08(par->PCIO, 0x03D4, 0x1C); 448 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); 449 450 if (par->CRTCnumber) { 451 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; 452 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; 453 state->crtcOwner = 3; 454 state->pllsel |= 0x20000800; 455 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); 456 if (par->twoStagePLL) 457 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); 458 } else if (par->twoHeads) { 459 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; 460 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; 461 state->crtcOwner = 0; 462 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); 463 if (par->twoStagePLL) 464 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); 465 } 466 467 state->cursorConfig = 0x00000100; 468 469 if (info->var.vmode & FB_VMODE_DOUBLE) 470 state->cursorConfig |= (1 << 4); 471 472 if (par->alphaCursor) { 473 if ((par->Chipset & 0x0ff0) != 0x0110) 474 state->cursorConfig |= 0x04011000; 475 else 476 state->cursorConfig |= 0x14011000; 477 state->general |= (1 << 29); 478 } else 479 state->cursorConfig |= 0x02000000; 480 481 if (par->twoHeads) { 482 if ((par->Chipset & 0x0ff0) == 0x0110) { 483 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & 484 ~0x00010000; 485 if (par->FPDither) 486 state->dither |= 0x00010000; 487 } else { 488 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; 489 if (par->FPDither) 490 state->dither |= 1; 491 } 492 } 493 494 state->timingH = 0; 495 state->timingV = 0; 496 state->displayV = info->var.xres; 497 498 return 0; 499} 500 501static void nvidia_init_vga(struct fb_info *info) 502{ 503 struct nvidia_par *par = info->par; 504 struct _riva_hw_state *state = &par->ModeReg; 505 int i; 506 507 for (i = 0; i < 0x10; i++) 508 state->attr[i] = i; 509 state->attr[0x10] = 0x41; 510 state->attr[0x11] = 0xff; 511 state->attr[0x12] = 0x0f; 512 state->attr[0x13] = 0x00; 513 state->attr[0x14] = 0x00; 514 515 memset(state->crtc, 0x00, NUM_CRT_REGS); 516 state->crtc[0x0a] = 0x20; 517 state->crtc[0x17] = 0xe3; 518 state->crtc[0x18] = 0xff; 519 state->crtc[0x28] = 0x40; 520 521 memset(state->gra, 0x00, NUM_GRC_REGS); 522 state->gra[0x05] = 0x40; 523 state->gra[0x06] = 0x05; 524 state->gra[0x07] = 0x0f; 525 state->gra[0x08] = 0xff; 526 527 state->seq[0x00] = 0x03; 528 state->seq[0x01] = 0x01; 529 state->seq[0x02] = 0x0f; 530 state->seq[0x03] = 0x00; 531 state->seq[0x04] = 0x0e; 532 533 state->misc_output = 0xeb; 534} 535 536static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 537{ 538 struct nvidia_par *par = info->par; 539 u8 data[MAX_CURS * MAX_CURS / 8]; 540 int i, set = cursor->set; 541 u16 fg, bg; 542 543 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 544 return -ENXIO; 545 546 NVShowHideCursor(par, 0); 547 548 if (par->cursor_reset) { 549 set = FB_CUR_SETALL; 550 par->cursor_reset = 0; 551 } 552 553 if (set & FB_CUR_SETSIZE) 554 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); 555 556 if (set & FB_CUR_SETPOS) { 557 u32 xx, yy, temp; 558 559 yy = cursor->image.dy - info->var.yoffset; 560 xx = cursor->image.dx - info->var.xoffset; 561 temp = xx & 0xFFFF; 562 temp |= yy << 16; 563 564 NV_WR32(par->PRAMDAC, 0x0000300, temp); 565 } 566 567 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 568 u32 bg_idx = cursor->image.bg_color; 569 u32 fg_idx = cursor->image.fg_color; 570 u32 s_pitch = (cursor->image.width + 7) >> 3; 571 u32 d_pitch = MAX_CURS / 8; 572 u8 *dat = (u8 *) cursor->image.data; 573 u8 *msk = (u8 *) cursor->mask; 574 u8 *src; 575 576 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 577 578 if (src) { 579 switch (cursor->rop) { 580 case ROP_XOR: 581 for (i = 0; i < s_pitch * cursor->image.height; i++) 582 src[i] = dat[i] ^ msk[i]; 583 break; 584 case ROP_COPY: 585 default: 586 for (i = 0; i < s_pitch * cursor->image.height; i++) 587 src[i] = dat[i] & msk[i]; 588 break; 589 } 590 591 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 592 cursor->image.height); 593 594 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 595 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 596 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; 597 598 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 599 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 600 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; 601 602 NVLockUnlock(par, 0); 603 604 nvidiafb_load_cursor_image(par, data, bg, fg, 605 cursor->image.width, 606 cursor->image.height); 607 kfree(src); 608 } 609 } 610 611 if (cursor->enable) 612 NVShowHideCursor(par, 1); 613 614 return 0; 615} 616 617static int nvidiafb_set_par(struct fb_info *info) 618{ 619 struct nvidia_par *par = info->par; 620 621 NVTRACE_ENTER(); 622 623 NVLockUnlock(par, 1); 624 if (!par->FlatPanel || !par->twoHeads) 625 par->FPDither = 0; 626 627 if (par->FPDither < 0) { 628 if ((par->Chipset & 0x0ff0) == 0x0110) 629 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) 630 & 0x00010000); 631 else 632 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); 633 printk(KERN_INFO PFX "Flat panel dithering %s\n", 634 par->FPDither ? "enabled" : "disabled"); 635 } 636 637 info->fix.visual = (info->var.bits_per_pixel == 8) ? 638 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 639 640 nvidia_init_vga(info); 641 nvidia_calc_regs(info); 642 643 NVLockUnlock(par, 0); 644 if (par->twoHeads) { 645 VGA_WR08(par->PCIO, 0x03D4, 0x44); 646 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); 647 NVLockUnlock(par, 0); 648 } 649 650 nvidia_screen_off(par, 1); 651 652 nvidia_write_regs(par, &par->ModeReg); 653 NVSetStartAddress(par, 0); 654 655#if defined(__BIG_ENDIAN) 656 /* turn on LFB swapping */ 657 { 658 unsigned char tmp; 659 660 VGA_WR08(par->PCIO, 0x3d4, 0x46); 661 tmp = VGA_RD08(par->PCIO, 0x3d5); 662 tmp |= (1 << 7); 663 VGA_WR08(par->PCIO, 0x3d5, tmp); 664 } 665#endif 666 667 info->fix.line_length = (info->var.xres_virtual * 668 info->var.bits_per_pixel) >> 3; 669 if (info->var.accel_flags) { 670 info->fbops->fb_imageblit = nvidiafb_imageblit; 671 info->fbops->fb_fillrect = nvidiafb_fillrect; 672 info->fbops->fb_copyarea = nvidiafb_copyarea; 673 info->fbops->fb_sync = nvidiafb_sync; 674 info->pixmap.scan_align = 4; 675 info->flags &= ~FBINFO_HWACCEL_DISABLED; 676 NVResetGraphics(info); 677 } else { 678 info->fbops->fb_imageblit = cfb_imageblit; 679 info->fbops->fb_fillrect = cfb_fillrect; 680 info->fbops->fb_copyarea = cfb_copyarea; 681 info->fbops->fb_sync = NULL; 682 info->pixmap.scan_align = 1; 683 info->flags |= FBINFO_HWACCEL_DISABLED; 684 } 685 686 par->cursor_reset = 1; 687 688 nvidia_screen_off(par, 0); 689 690#ifdef CONFIG_BOOTX_TEXT 691 /* Update debug text engine */ 692 btext_update_display(info->fix.smem_start, 693 info->var.xres, info->var.yres, 694 info->var.bits_per_pixel, info->fix.line_length); 695#endif 696 697 NVLockUnlock(par, 0); 698 NVTRACE_LEAVE(); 699 return 0; 700} 701 702static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, 703 unsigned blue, unsigned transp, 704 struct fb_info *info) 705{ 706 struct nvidia_par *par = info->par; 707 int i; 708 709 NVTRACE_ENTER(); 710 if (regno >= (1 << info->var.green.length)) 711 return -EINVAL; 712 713 if (info->var.grayscale) { 714 /* gray = 0.30*R + 0.59*G + 0.11*B */ 715 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; 716 } 717 718 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 719 ((u32 *) info->pseudo_palette)[regno] = 720 (regno << info->var.red.offset) | 721 (regno << info->var.green.offset) | 722 (regno << info->var.blue.offset); 723 } 724 725 switch (info->var.bits_per_pixel) { 726 case 8: 727 /* "transparent" stuff is completely ignored. */ 728 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 729 break; 730 case 16: 731 if (info->var.green.length == 5) { 732 for (i = 0; i < 8; i++) { 733 nvidia_write_clut(par, regno * 8 + i, red >> 8, 734 green >> 8, blue >> 8); 735 } 736 } else { 737 u8 r, g, b; 738 739 if (regno < 32) { 740 for (i = 0; i < 8; i++) { 741 nvidia_write_clut(par, regno * 8 + i, 742 red >> 8, green >> 8, 743 blue >> 8); 744 } 745 } 746 747 nvidia_read_clut(par, regno * 4, &r, &g, &b); 748 749 for (i = 0; i < 4; i++) 750 nvidia_write_clut(par, regno * 4 + i, r, 751 green >> 8, b); 752 } 753 break; 754 case 32: 755 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 756 break; 757 default: 758 /* do nothing */ 759 break; 760 } 761 762 NVTRACE_LEAVE(); 763 return 0; 764} 765 766static int nvidiafb_check_var(struct fb_var_screeninfo *var, 767 struct fb_info *info) 768{ 769 struct nvidia_par *par = info->par; 770 int memlen, vramlen, mode_valid = 0; 771 int pitch, err = 0; 772 773 NVTRACE_ENTER(); 774 775 var->transp.offset = 0; 776 var->transp.length = 0; 777 778 var->xres &= ~7; 779 780 if (var->bits_per_pixel <= 8) 781 var->bits_per_pixel = 8; 782 else if (var->bits_per_pixel <= 16) 783 var->bits_per_pixel = 16; 784 else 785 var->bits_per_pixel = 32; 786 787 switch (var->bits_per_pixel) { 788 case 8: 789 var->red.offset = 0; 790 var->red.length = 8; 791 var->green.offset = 0; 792 var->green.length = 8; 793 var->blue.offset = 0; 794 var->blue.length = 8; 795 var->transp.offset = 0; 796 var->transp.length = 0; 797 break; 798 case 16: 799 var->green.length = (var->green.length < 6) ? 5 : 6; 800 var->red.length = 5; 801 var->blue.length = 5; 802 var->transp.length = 6 - var->green.length; 803 var->blue.offset = 0; 804 var->green.offset = 5; 805 var->red.offset = 5 + var->green.length; 806 var->transp.offset = (5 + var->red.offset) & 15; 807 break; 808 case 32: /* RGBA 8888 */ 809 var->red.offset = 16; 810 var->red.length = 8; 811 var->green.offset = 8; 812 var->green.length = 8; 813 var->blue.offset = 0; 814 var->blue.length = 8; 815 var->transp.length = 8; 816 var->transp.offset = 24; 817 break; 818 } 819 820 var->red.msb_right = 0; 821 var->green.msb_right = 0; 822 var->blue.msb_right = 0; 823 var->transp.msb_right = 0; 824 825 if (!info->monspecs.hfmax || !info->monspecs.vfmax || 826 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 827 mode_valid = 1; 828 829 /* calculate modeline if supported by monitor */ 830 if (!mode_valid && info->monspecs.gtf) { 831 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 832 mode_valid = 1; 833 } 834 835 if (!mode_valid) { 836 const struct fb_videomode *mode; 837 838 mode = fb_find_best_mode(var, &info->modelist); 839 if (mode) { 840 fb_videomode_to_var(var, mode); 841 mode_valid = 1; 842 } 843 } 844 845 if (!mode_valid && info->monspecs.modedb_len) 846 return -EINVAL; 847 848 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || 849 par->fpHeight < var->yres)) 850 return -EINVAL; 851 852 if (var->yres_virtual < var->yres) 853 var->yres_virtual = var->yres; 854 855 if (var->xres_virtual < var->xres) 856 var->xres_virtual = var->xres; 857 858 var->xres_virtual = (var->xres_virtual + 63) & ~63; 859 860 vramlen = info->screen_size; 861 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; 862 memlen = pitch * var->yres_virtual; 863 864 if (memlen > vramlen) { 865 var->yres_virtual = vramlen / pitch; 866 867 if (var->yres_virtual < var->yres) { 868 var->yres_virtual = var->yres; 869 var->xres_virtual = vramlen / var->yres_virtual; 870 var->xres_virtual /= var->bits_per_pixel / 8; 871 var->xres_virtual &= ~63; 872 pitch = (var->xres_virtual * 873 var->bits_per_pixel + 7) / 8; 874 memlen = pitch * var->yres; 875 876 if (var->xres_virtual < var->xres) { 877 printk("nvidiafb: required video memory, " 878 "%d bytes, for %dx%d-%d (virtual) " 879 "is out of range\n", 880 memlen, var->xres_virtual, 881 var->yres_virtual, var->bits_per_pixel); 882 err = -ENOMEM; 883 } 884 } 885 } 886 887 if (var->accel_flags) { 888 if (var->yres_virtual > 0x7fff) 889 var->yres_virtual = 0x7fff; 890 if (var->xres_virtual > 0x7fff) 891 var->xres_virtual = 0x7fff; 892 } 893 894 var->xres_virtual &= ~63; 895 896 NVTRACE_LEAVE(); 897 898 return err; 899} 900 901static int nvidiafb_pan_display(struct fb_var_screeninfo *var, 902 struct fb_info *info) 903{ 904 struct nvidia_par *par = info->par; 905 u32 total; 906 907 total = var->yoffset * info->fix.line_length + var->xoffset; 908 909 NVSetStartAddress(par, total); 910 911 return 0; 912} 913 914static int nvidiafb_blank(int blank, struct fb_info *info) 915{ 916 struct nvidia_par *par = info->par; 917 unsigned char tmp, vesa; 918 919 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ 920 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ 921 922 NVTRACE_ENTER(); 923 924 if (blank) 925 tmp |= 0x20; 926 927 switch (blank) { 928 case FB_BLANK_UNBLANK: 929 case FB_BLANK_NORMAL: 930 break; 931 case FB_BLANK_VSYNC_SUSPEND: 932 vesa |= 0x80; 933 break; 934 case FB_BLANK_HSYNC_SUSPEND: 935 vesa |= 0x40; 936 break; 937 case FB_BLANK_POWERDOWN: 938 vesa |= 0xc0; 939 break; 940 } 941 942 NVWriteSeq(par, 0x01, tmp); 943 NVWriteCrtc(par, 0x1a, vesa); 944 945 NVTRACE_LEAVE(); 946 947 return 0; 948} 949 950/* 951 * Because the VGA registers are not mapped linearly in its MMIO space, 952 * restrict VGA register saving and restore to x86 only, where legacy VGA IO 953 * access is legal. Consequently, we must also check if the device is the 954 * primary display. 955 */ 956#ifdef CONFIG_X86 957static void save_vga_x86(struct nvidia_par *par) 958{ 959 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 960 961 if (res && res->flags & IORESOURCE_ROM_SHADOW) { 962 memset(&par->vgastate, 0, sizeof(par->vgastate)); 963 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | 964 VGA_SAVE_CMAP; 965 save_vga(&par->vgastate); 966 } 967} 968 969static void restore_vga_x86(struct nvidia_par *par) 970{ 971 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 972 973 if (res && res->flags & IORESOURCE_ROM_SHADOW) 974 restore_vga(&par->vgastate); 975} 976#else 977#define save_vga_x86(x) do {} while (0) 978#define restore_vga_x86(x) do {} while (0) 979#endif /* X86 */ 980 981static int nvidiafb_open(struct fb_info *info, int user) 982{ 983 struct nvidia_par *par = info->par; 984 985 mutex_lock(&par->open_lock); 986 987 if (!par->open_count) { 988 save_vga_x86(par); 989 nvidia_save_vga(par, &par->initial_state); 990 } 991 992 par->open_count++; 993 mutex_unlock(&par->open_lock); 994 return 0; 995} 996 997static int nvidiafb_release(struct fb_info *info, int user) 998{ 999 struct nvidia_par *par = info->par; 1000 int err = 0; 1001 1002 mutex_lock(&par->open_lock); 1003 1004 if (!par->open_count) { 1005 err = -EINVAL; 1006 goto done; 1007 } 1008 1009 if (par->open_count == 1) { 1010 nvidia_write_regs(par, &par->initial_state); 1011 restore_vga_x86(par); 1012 } 1013 1014 par->open_count--; 1015done: 1016 mutex_unlock(&par->open_lock); 1017 return err; 1018} 1019 1020static struct fb_ops nvidia_fb_ops = { 1021 .owner = THIS_MODULE, 1022 .fb_open = nvidiafb_open, 1023 .fb_release = nvidiafb_release, 1024 .fb_check_var = nvidiafb_check_var, 1025 .fb_set_par = nvidiafb_set_par, 1026 .fb_setcolreg = nvidiafb_setcolreg, 1027 .fb_pan_display = nvidiafb_pan_display, 1028 .fb_blank = nvidiafb_blank, 1029 .fb_fillrect = nvidiafb_fillrect, 1030 .fb_copyarea = nvidiafb_copyarea, 1031 .fb_imageblit = nvidiafb_imageblit, 1032 .fb_cursor = nvidiafb_cursor, 1033 .fb_sync = nvidiafb_sync, 1034}; 1035 1036#ifdef CONFIG_PM 1037static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg) 1038{ 1039 struct fb_info *info = pci_get_drvdata(dev); 1040 struct nvidia_par *par = info->par; 1041 1042 if (mesg.event == PM_EVENT_PRETHAW) 1043 mesg.event = PM_EVENT_FREEZE; 1044 acquire_console_sem(); 1045 par->pm_state = mesg.event; 1046 1047 if (mesg.event == PM_EVENT_SUSPEND) { 1048 fb_set_suspend(info, 1); 1049 nvidiafb_blank(FB_BLANK_POWERDOWN, info); 1050 nvidia_write_regs(par, &par->SavedReg); 1051 pci_save_state(dev); 1052 pci_disable_device(dev); 1053 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1054 } 1055 dev->dev.power.power_state = mesg; 1056 1057 release_console_sem(); 1058 return 0; 1059} 1060 1061static int nvidiafb_resume(struct pci_dev *dev) 1062{ 1063 struct fb_info *info = pci_get_drvdata(dev); 1064 struct nvidia_par *par = info->par; 1065 1066 acquire_console_sem(); 1067 pci_set_power_state(dev, PCI_D0); 1068 1069 if (par->pm_state != PM_EVENT_FREEZE) { 1070 pci_restore_state(dev); 1071 1072 if (pci_enable_device(dev)) 1073 goto fail; 1074 1075 pci_set_master(dev); 1076 } 1077 1078 par->pm_state = PM_EVENT_ON; 1079 nvidiafb_set_par(info); 1080 fb_set_suspend (info, 0); 1081 nvidiafb_blank(FB_BLANK_UNBLANK, info); 1082 1083fail: 1084 release_console_sem(); 1085 return 0; 1086} 1087#else 1088#define nvidiafb_suspend NULL 1089#define nvidiafb_resume NULL 1090#endif 1091 1092static int __devinit nvidia_set_fbinfo(struct fb_info *info) 1093{ 1094 struct fb_monspecs *specs = &info->monspecs; 1095 struct fb_videomode modedb; 1096 struct nvidia_par *par = info->par; 1097 int lpitch; 1098 1099 NVTRACE_ENTER(); 1100 info->flags = FBINFO_DEFAULT 1101 | FBINFO_HWACCEL_IMAGEBLIT 1102 | FBINFO_HWACCEL_FILLRECT 1103 | FBINFO_HWACCEL_COPYAREA 1104 | FBINFO_HWACCEL_YPAN; 1105 1106 fb_videomode_to_modelist(info->monspecs.modedb, 1107 info->monspecs.modedb_len, &info->modelist); 1108 fb_var_to_videomode(&modedb, &nvidiafb_default_var); 1109 1110 switch (bpp) { 1111 case 0 ... 8: 1112 bpp = 8; 1113 break; 1114 case 9 ... 16: 1115 bpp = 16; 1116 break; 1117 default: 1118 bpp = 32; 1119 break; 1120 } 1121 1122 if (specs->modedb != NULL) { 1123 const struct fb_videomode *mode; 1124 1125 mode = fb_find_best_display(specs, &info->modelist); 1126 fb_videomode_to_var(&nvidiafb_default_var, mode); 1127 nvidiafb_default_var.bits_per_pixel = bpp; 1128 } else if (par->fpWidth && par->fpHeight) { 1129 char buf[16]; 1130 1131 memset(buf, 0, 16); 1132 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); 1133 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, 1134 specs->modedb_len, &modedb, bpp); 1135 } 1136 1137 if (mode_option) 1138 fb_find_mode(&nvidiafb_default_var, info, mode_option, 1139 specs->modedb, specs->modedb_len, &modedb, bpp); 1140 1141 info->var = nvidiafb_default_var; 1142 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1143 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1144 info->pseudo_palette = par->pseudo_palette; 1145 fb_alloc_cmap(&info->cmap, 256, 0); 1146 fb_destroy_modedb(info->monspecs.modedb); 1147 info->monspecs.modedb = NULL; 1148 1149 /* maximize virtual vertical length */ 1150 lpitch = info->var.xres_virtual * 1151 ((info->var.bits_per_pixel + 7) >> 3); 1152 info->var.yres_virtual = info->screen_size / lpitch; 1153 1154 info->pixmap.scan_align = 4; 1155 info->pixmap.buf_align = 4; 1156 info->pixmap.access_align = 32; 1157 info->pixmap.size = 8 * 1024; 1158 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1159 1160 if (!hwcur) 1161 info->fbops->fb_cursor = NULL; 1162 1163 info->var.accel_flags = (!noaccel); 1164 1165 switch (par->Architecture) { 1166 case NV_ARCH_04: 1167 info->fix.accel = FB_ACCEL_NV4; 1168 break; 1169 case NV_ARCH_10: 1170 info->fix.accel = FB_ACCEL_NV_10; 1171 break; 1172 case NV_ARCH_20: 1173 info->fix.accel = FB_ACCEL_NV_20; 1174 break; 1175 case NV_ARCH_30: 1176 info->fix.accel = FB_ACCEL_NV_30; 1177 break; 1178 case NV_ARCH_40: 1179 info->fix.accel = FB_ACCEL_NV_40; 1180 break; 1181 } 1182 1183 NVTRACE_LEAVE(); 1184 1185 return nvidiafb_check_var(&info->var, info); 1186} 1187 1188static u32 __devinit nvidia_get_chipset(struct fb_info *info) 1189{ 1190 struct nvidia_par *par = info->par; 1191 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; 1192 1193 printk(KERN_INFO PFX "Device ID: %x \n", id); 1194 1195 if ((id & 0xfff0) == 0x00f0) { 1196 /* pci-e */ 1197 id = NV_RD32(par->REGS, 0x1800); 1198 1199 if ((id & 0x0000ffff) == 0x000010DE) 1200 id = 0x10DE0000 | (id >> 16); 1201 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ 1202 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | 1203 ((id >> 8) & 0x000000ff); 1204 printk(KERN_INFO PFX "Subsystem ID: %x \n", id); 1205 } 1206 1207 return id; 1208} 1209 1210static u32 __devinit nvidia_get_arch(struct fb_info *info) 1211{ 1212 struct nvidia_par *par = info->par; 1213 u32 arch = 0; 1214 1215 switch (par->Chipset & 0x0ff0) { 1216 case 0x0100: /* GeForce 256 */ 1217 case 0x0110: /* GeForce2 MX */ 1218 case 0x0150: /* GeForce2 */ 1219 case 0x0170: /* GeForce4 MX */ 1220 case 0x0180: /* GeForce4 MX (8x AGP) */ 1221 case 0x01A0: /* nForce */ 1222 case 0x01F0: /* nForce2 */ 1223 arch = NV_ARCH_10; 1224 break; 1225 case 0x0200: /* GeForce3 */ 1226 case 0x0250: /* GeForce4 Ti */ 1227 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1228 arch = NV_ARCH_20; 1229 break; 1230 case 0x0300: /* GeForceFX 5800 */ 1231 case 0x0310: /* GeForceFX 5600 */ 1232 case 0x0320: /* GeForceFX 5200 */ 1233 case 0x0330: /* GeForceFX 5900 */ 1234 case 0x0340: /* GeForceFX 5700 */ 1235 arch = NV_ARCH_30; 1236 break; 1237 case 0x0040: /* GeForce 6800 */ 1238 case 0x00C0: /* GeForce 6800 */ 1239 case 0x0120: /* GeForce 6800 */ 1240 case 0x0130: 1241 case 0x0140: /* GeForce 6600 */ 1242 case 0x0160: /* GeForce 6200 */ 1243 case 0x01D0: /* GeForce 7200, 7300, 7400 */ 1244 case 0x02E0: /* GeForce 7300 GT */ 1245 case 0x0090: /* GeForce 7800 */ 1246 case 0x0210: /* GeForce 6800 */ 1247 case 0x0220: /* GeForce 6200 */ 1248 case 0x0230: 1249 case 0x0240: /* GeForce 6100 */ 1250 case 0x0290: /* GeForce 7900 */ 1251 case 0x0390: /* GeForce 7600 */ 1252 arch = NV_ARCH_40; 1253 break; 1254 case 0x0020: /* TNT, TNT2 */ 1255 arch = NV_ARCH_04; 1256 break; 1257 default: /* unknown architecture */ 1258 break; 1259 } 1260 1261 return arch; 1262} 1263 1264static int __devinit nvidiafb_probe(struct pci_dev *pd, 1265 const struct pci_device_id *ent) 1266{ 1267 struct nvidia_par *par; 1268 struct fb_info *info; 1269 unsigned short cmd; 1270 1271 1272 NVTRACE_ENTER(); 1273 assert(pd != NULL); 1274 1275 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); 1276 1277 if (!info) 1278 goto err_out; 1279 1280 par = info->par; 1281 par->pci_dev = pd; 1282 mutex_init(&par->open_lock); 1283 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1284 1285 if (info->pixmap.addr == NULL) 1286 goto err_out_kfree; 1287 1288 if (pci_enable_device(pd)) { 1289 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1290 goto err_out_enable; 1291 } 1292 1293 if (pci_request_regions(pd, "nvidiafb")) { 1294 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1295 goto err_out_enable; 1296 } 1297 1298 par->FlatPanel = flatpanel; 1299 if (flatpanel == 1) 1300 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1301 par->FPDither = fpdither; 1302 1303 par->CRTCnumber = forceCRTC; 1304 par->FpScale = (!noscale); 1305 par->paneltweak = paneltweak; 1306 1307 /* enable IO and mem if not already done */ 1308 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1309 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1310 pci_write_config_word(pd, PCI_COMMAND, cmd); 1311 1312 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); 1313 nvidiafb_fix.smem_start = pci_resource_start(pd, 1); 1314 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); 1315 1316 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1317 1318 if (!par->REGS) { 1319 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1320 goto err_out_free_base0; 1321 } 1322 1323 par->Chipset = nvidia_get_chipset(info); 1324 par->Architecture = nvidia_get_arch(info); 1325 1326 if (par->Architecture == 0) { 1327 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1328 goto err_out_arch; 1329 } 1330 1331 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1332 1333 if (NVCommonSetup(info)) 1334 goto err_out_arch; 1335 1336 par->FbAddress = nvidiafb_fix.smem_start; 1337 par->FbMapSize = par->RamAmountKBytes * 1024; 1338 if (vram && vram * 1024 * 1024 < par->FbMapSize) 1339 par->FbMapSize = vram * 1024 * 1024; 1340 1341 /* Limit amount of vram to 64 MB */ 1342 if (par->FbMapSize > 64 * 1024 * 1024) 1343 par->FbMapSize = 64 * 1024 * 1024; 1344 1345 if(par->Architecture >= NV_ARCH_40) 1346 par->FbUsableSize = par->FbMapSize - (560 * 1024); 1347 else 1348 par->FbUsableSize = par->FbMapSize - (128 * 1024); 1349 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : 1350 16 * 1024; 1351 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; 1352 par->CursorStart = par->FbUsableSize + (32 * 1024); 1353 1354 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize); 1355 info->screen_size = par->FbUsableSize; 1356 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; 1357 1358 if (!info->screen_base) { 1359 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 1360 goto err_out_free_base1; 1361 } 1362 1363 par->FbStart = info->screen_base; 1364 1365#ifdef CONFIG_MTRR 1366 if (!nomtrr) { 1367 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start, 1368 par->RamAmountKBytes * 1024, 1369 MTRR_TYPE_WRCOMB, 1); 1370 if (par->mtrr.vram < 0) { 1371 printk(KERN_ERR PFX "unable to setup MTRR\n"); 1372 } else { 1373 par->mtrr.vram_valid = 1; 1374 /* let there be speed */ 1375 printk(KERN_INFO PFX "MTRR set to ON\n"); 1376 } 1377 } 1378#endif /* CONFIG_MTRR */ 1379 1380 info->fbops = &nvidia_fb_ops; 1381 info->fix = nvidiafb_fix; 1382 1383 if (nvidia_set_fbinfo(info) < 0) { 1384 printk(KERN_ERR PFX "error setting initial video mode\n"); 1385 goto err_out_iounmap_fb; 1386 } 1387 1388 nvidia_save_vga(par, &par->SavedReg); 1389 1390 pci_set_drvdata(pd, info); 1391 1392 if (backlight) 1393 nvidia_bl_init(par); 1394 1395 if (register_framebuffer(info) < 0) { 1396 printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); 1397 goto err_out_iounmap_fb; 1398 } 1399 1400 1401 printk(KERN_INFO PFX 1402 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", 1403 info->fix.id, 1404 par->FbMapSize / (1024 * 1024), info->fix.smem_start); 1405 1406 NVTRACE_LEAVE(); 1407 return 0; 1408 1409err_out_iounmap_fb: 1410 iounmap(info->screen_base); 1411err_out_free_base1: 1412 fb_destroy_modedb(info->monspecs.modedb); 1413 nvidia_delete_i2c_busses(par); 1414err_out_arch: 1415 iounmap(par->REGS); 1416 err_out_free_base0: 1417 pci_release_regions(pd); 1418err_out_enable: 1419 kfree(info->pixmap.addr); 1420err_out_kfree: 1421 framebuffer_release(info); 1422err_out: 1423 return -ENODEV; 1424} 1425 1426static void __devexit nvidiafb_remove(struct pci_dev *pd) 1427{ 1428 struct fb_info *info = pci_get_drvdata(pd); 1429 struct nvidia_par *par = info->par; 1430 1431 NVTRACE_ENTER(); 1432 1433 unregister_framebuffer(info); 1434 1435 nvidia_bl_exit(par); 1436 1437#ifdef CONFIG_MTRR 1438 if (par->mtrr.vram_valid) 1439 mtrr_del(par->mtrr.vram, info->fix.smem_start, 1440 info->fix.smem_len); 1441#endif /* CONFIG_MTRR */ 1442 1443 iounmap(info->screen_base); 1444 fb_destroy_modedb(info->monspecs.modedb); 1445 nvidia_delete_i2c_busses(par); 1446 iounmap(par->REGS); 1447 pci_release_regions(pd); 1448 kfree(info->pixmap.addr); 1449 framebuffer_release(info); 1450 pci_set_drvdata(pd, NULL); 1451 NVTRACE_LEAVE(); 1452} 1453 1454/* ------------------------------------------------------------------------- * 1455 * 1456 * initialization 1457 * 1458 * ------------------------------------------------------------------------- */ 1459 1460#ifndef MODULE 1461static int __devinit nvidiafb_setup(char *options) 1462{ 1463 char *this_opt; 1464 1465 NVTRACE_ENTER(); 1466 if (!options || !*options) 1467 return 0; 1468 1469 while ((this_opt = strsep(&options, ",")) != NULL) { 1470 if (!strncmp(this_opt, "forceCRTC", 9)) { 1471 char *p; 1472 1473 p = this_opt + 9; 1474 if (!*p || !*(++p)) 1475 continue; 1476 forceCRTC = *p - '0'; 1477 if (forceCRTC < 0 || forceCRTC > 1) 1478 forceCRTC = -1; 1479 } else if (!strncmp(this_opt, "flatpanel", 9)) { 1480 flatpanel = 1; 1481 } else if (!strncmp(this_opt, "hwcur", 5)) { 1482 hwcur = 1; 1483 } else if (!strncmp(this_opt, "noaccel", 6)) { 1484 noaccel = 1; 1485 } else if (!strncmp(this_opt, "noscale", 7)) { 1486 noscale = 1; 1487 } else if (!strncmp(this_opt, "paneltweak:", 11)) { 1488 paneltweak = simple_strtoul(this_opt+11, NULL, 0); 1489 } else if (!strncmp(this_opt, "vram:", 5)) { 1490 vram = simple_strtoul(this_opt+5, NULL, 0); 1491 } else if (!strncmp(this_opt, "backlight:", 10)) { 1492 backlight = simple_strtoul(this_opt+10, NULL, 0); 1493#ifdef CONFIG_MTRR 1494 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1495 nomtrr = 1; 1496#endif 1497 } else if (!strncmp(this_opt, "fpdither:", 9)) { 1498 fpdither = simple_strtol(this_opt+9, NULL, 0); 1499 } else if (!strncmp(this_opt, "bpp:", 4)) { 1500 bpp = simple_strtoul(this_opt+4, NULL, 0); 1501 } else 1502 mode_option = this_opt; 1503 } 1504 NVTRACE_LEAVE(); 1505 return 0; 1506} 1507#endif /* !MODULE */ 1508 1509static struct pci_driver nvidiafb_driver = { 1510 .name = "nvidiafb", 1511 .id_table = nvidiafb_pci_tbl, 1512 .probe = nvidiafb_probe, 1513 .suspend = nvidiafb_suspend, 1514 .resume = nvidiafb_resume, 1515 .remove = __devexit_p(nvidiafb_remove), 1516}; 1517 1518/* ------------------------------------------------------------------------- * 1519 * 1520 * modularization 1521 * 1522 * ------------------------------------------------------------------------- */ 1523 1524static int __devinit nvidiafb_init(void) 1525{ 1526#ifndef MODULE 1527 char *option = NULL; 1528 1529 if (fb_get_options("nvidiafb", &option)) 1530 return -ENODEV; 1531 nvidiafb_setup(option); 1532#endif 1533 return pci_register_driver(&nvidiafb_driver); 1534} 1535 1536module_init(nvidiafb_init); 1537 1538#ifdef MODULE 1539static void __exit nvidiafb_exit(void) 1540{ 1541 pci_unregister_driver(&nvidiafb_driver); 1542} 1543 1544module_exit(nvidiafb_exit); 1545 1546module_param(flatpanel, int, 0); 1547MODULE_PARM_DESC(flatpanel, 1548 "Enables experimental flat panel support for some chipsets. " 1549 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1550module_param(fpdither, int, 0); 1551MODULE_PARM_DESC(fpdither, 1552 "Enables dithering of flat panel for 6 bits panels. " 1553 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1554module_param(hwcur, int, 0); 1555MODULE_PARM_DESC(hwcur, 1556 "Enables hardware cursor implementation. (0 or 1=enabled) " 1557 "(default=0)"); 1558module_param(noaccel, int, 0); 1559MODULE_PARM_DESC(noaccel, 1560 "Disables hardware acceleration. (0 or 1=disable) " 1561 "(default=0)"); 1562module_param(noscale, int, 0); 1563MODULE_PARM_DESC(noscale, 1564 "Disables screen scaleing. (0 or 1=disable) " 1565 "(default=0, do scaling)"); 1566module_param(paneltweak, int, 0); 1567MODULE_PARM_DESC(paneltweak, 1568 "Tweak display settings for flatpanels. " 1569 "(default=0, no tweaks)"); 1570module_param(forceCRTC, int, 0); 1571MODULE_PARM_DESC(forceCRTC, 1572 "Forces usage of a particular CRTC in case autodetection " 1573 "fails. (0 or 1) (default=autodetect)"); 1574module_param(vram, int, 0); 1575MODULE_PARM_DESC(vram, 1576 "amount of framebuffer memory to remap in MiB" 1577 "(default=0 - remap entire memory)"); 1578module_param(mode_option, charp, 0); 1579MODULE_PARM_DESC(mode_option, "Specify initial video mode"); 1580module_param(bpp, int, 0); 1581MODULE_PARM_DESC(bpp, "pixel width in bits" 1582 "(default=8)"); 1583#ifdef CONFIG_MTRR 1584module_param(nomtrr, bool, 0); 1585MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " 1586 "(default=0)"); 1587#endif 1588 1589MODULE_AUTHOR("Antonino Daplas"); 1590MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); 1591MODULE_LICENSE("GPL"); 1592#endif /* MODULE */ 1593