Searched refs:DCRN_DMA3_BASE (Results 1 - 9 of 9) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-ppc/
H A Dibm405.h112 #ifdef DCRN_DMA3_BASE
113 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */
114 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */
115 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */
116 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */
118 #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
121 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
H A Dibm403.h22 #define DCRN_DMA3_BASE 0x0D8 macro
243 #ifdef DCRN_DMA3_BASE
244 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */
245 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */
246 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */
247 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */
249 #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
252 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
H A Dibm44x.h195 #define DCRN_DMA3_BASE 0x118 macro
407 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
408 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
409 #define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
410 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
411 #define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
412 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
413 #define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
414 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dibm405ep.h128 #define DCRN_DMA3_BASE 0x118 macro
H A Dibm405gp.h131 #define DCRN_DMA3_BASE 0x118 macro
H A Dibm405gpr.h131 #define DCRN_DMA3_BASE 0x118 macro
H A Dibmstb4.h120 #define DCRN_DMA3_BASE 0x0D8 macro
132 #define DCRN_DMA3_BASE 0x0D8 macro
H A Dibmstbx25.h137 #define DCRN_DMA3_BASE 0x0D8 macro
149 #define DCRN_DMA3_BASE 0x0D8 macro
H A Dibmnp405h.h117 #define DCRN_DMA3_BASE 0x118 macro

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