1/* 2 * IBM PPC 405EP processor defines. 3 * 4 * Author: SAW (IBM), derived from ibm405gp.h. 5 * Maintained by MontaVista Software <source@mvista.com> 6 * 7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the 8 * terms of the GNU General Public License version 2. This program is 9 * licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 13#ifdef __KERNEL__ 14#ifndef __ASM_IBM405EP_H__ 15#define __ASM_IBM405EP_H__ 16 17 18/* ibm405.h at bottom of this file */ 19 20/* PCI 21 * PCI Bridge config reg definitions 22 * see 17-19 of manual 23 */ 24 25#define PPC405_PCI_CONFIG_ADDR 0xeec00000 26#define PPC405_PCI_CONFIG_DATA 0xeec00004 27 28#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ 29 /* setbat */ 30#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ 31#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ 32#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ 33 34#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ 35#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ 36#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ 37#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ 38 39#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE 40 41#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) 42#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR 43#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) 44#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) 45#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR 46#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) 47#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) 48#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR 49#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) 50#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) 51#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR 52#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) 53 54/* serial port defines */ 55#define RS_TABLE_SIZE 2 56 57#define UART0_INT 0 58#define UART1_INT 1 59 60#define PCIL0_BASE 0xEF400000 61#define UART0_IO_BASE 0xEF600300 62#define UART1_IO_BASE 0xEF600400 63#define EMAC0_BASE 0xEF600800 64 65#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i] 66 67#if defined(CONFIG_UART0_TTYS0) 68#define ACTING_UART0_IO_BASE UART0_IO_BASE 69#define ACTING_UART1_IO_BASE UART1_IO_BASE 70#define ACTING_UART0_INT UART0_INT 71#define ACTING_UART1_INT UART1_INT 72#else 73#define ACTING_UART0_IO_BASE UART1_IO_BASE 74#define ACTING_UART1_IO_BASE UART0_IO_BASE 75#define ACTING_UART0_INT UART1_INT 76#define ACTING_UART1_INT UART0_INT 77#endif 78 79#define STD_UART_OP(num) \ 80 { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \ 81 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 82 iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \ 83 io_type: SERIAL_IO_MEM}, 84 85#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE 86#define SERIAL_PORT_DFNS \ 87 STD_UART_OP(0) \ 88 STD_UART_OP(1) 89 90/* DCR defines */ 91#define DCRN_CPMSR_BASE 0x0BA 92#define DCRN_CPMFR_BASE 0x0B9 93 94#define DCRN_CPC0_PLLMR0_BASE 0x0F0 95#define DCRN_CPC0_BOOT_BASE 0x0F1 96#define DCRN_CPC0_CR1_BASE 0x0F2 97#define DCRN_CPC0_EPRCSR_BASE 0x0F3 98#define DCRN_CPC0_PLLMR1_BASE 0x0F4 99#define DCRN_CPC0_UCR_BASE 0x0F5 100#define DCRN_CPC0_UCR_U0DIV 0x07F 101#define DCRN_CPC0_SRR_BASE 0x0F6 102#define DCRN_CPC0_JTAGID_BASE 0x0F7 103#define DCRN_CPC0_SPARE_BASE 0x0F8 104#define DCRN_CPC0_PCI_BASE 0x0F9 105 106 107#define IBM_CPM_GPT 0x80000000 /* GPT interface */ 108#define IBM_CPM_PCI 0x40000000 /* PCI bridge */ 109#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */ 110#define IBM_CPM_CPU 0x00008000 /* processor core */ 111#define IBM_CPM_EBC 0x00002000 /* EBC controller */ 112#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */ 113#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */ 114#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */ 115#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */ 116#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */ 117#define IBM_CPM_DMA 0x00000040 /* DMA controller */ 118#define IBM_CPM_IIC0 0x00000010 /* IIC interface */ 119#define IBM_CPM_UART1 0x00000002 /* serial port 0 */ 120#define IBM_CPM_UART0 0x00000001 /* serial port 1 */ 121#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ 122 | IBM_CPM_OPB | IBM_CPM_EBC \ 123 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ 124 | IBM_CPM_UIC | IBM_CPM_TMRCLK) 125#define DCRN_DMA0_BASE 0x100 126#define DCRN_DMA1_BASE 0x108 127#define DCRN_DMA2_BASE 0x110 128#define DCRN_DMA3_BASE 0x118 129#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 130#define DCRN_DMASR_BASE 0x120 131#define DCRN_EBC_BASE 0x012 132#define DCRN_DCP0_BASE 0x014 133#define DCRN_MAL_BASE 0x180 134#define DCRN_OCM0_BASE 0x018 135#define DCRN_PLB0_BASE 0x084 136#define DCRN_PLLMR_BASE 0x0B0 137#define DCRN_POB0_BASE 0x0A0 138#define DCRN_SDRAM0_BASE 0x010 139#define DCRN_UIC0_BASE 0x0C0 140#define UIC0 DCRN_UIC0_BASE 141 142#include <asm/ibm405.h> 143 144#endif /* __ASM_IBM405EP_H__ */ 145#endif /* __KERNEL__ */ 146