Searched refs:DCRN_DMA2_BASE (Results 1 - 9 of 9) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-ppc/
H A Dibm405.h99 #ifdef DCRN_DMA2_BASE
100 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */
101 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */
102 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */
103 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */
105 #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
108 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
H A Dibm403.h21 #define DCRN_DMA2_BASE 0x0D0 macro
230 #ifdef DCRN_DMA2_BASE
231 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */
232 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */
233 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */
234 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */
236 #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
239 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
H A Dibm44x.h194 #define DCRN_DMA2_BASE 0x110 macro
398 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
399 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
400 #define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
401 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
402 #define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
403 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
404 #define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
405 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dibm405ep.h127 #define DCRN_DMA2_BASE 0x110 macro
H A Dibm405gp.h130 #define DCRN_DMA2_BASE 0x110 macro
H A Dibm405gpr.h130 #define DCRN_DMA2_BASE 0x110 macro
H A Dibmstb4.h119 #define DCRN_DMA2_BASE 0x0D0 macro
131 #define DCRN_DMA2_BASE 0x0D0 macro
H A Dibmstbx25.h136 #define DCRN_DMA2_BASE 0x0D0 macro
148 #define DCRN_DMA2_BASE 0x0D0 macro
H A Dibmnp405h.h116 #define DCRN_DMA2_BASE 0x110 macro

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