Searched refs:DCRN_DMA0_BASE (Results 1 - 9 of 9) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-ppc/
H A Dibm405.h63 #ifdef DCRN_DMA0_BASE
65 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0)
66 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */
68 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2)
70 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3)
73 #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4)
77 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4)
H A Dibm403.h19 #define DCRN_DMA0_BASE 0x0C0 macro
202 #ifdef DCRN_DMA0_BASE
203 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */
204 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */
205 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */
206 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */
208 #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */
212 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */
H A Dibm44x.h192 #define DCRN_DMA0_BASE 0x100 macro
380 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
381 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
382 #define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
383 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
384 #define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
385 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
386 #define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
387 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dibm405ep.h125 #define DCRN_DMA0_BASE 0x100 macro
H A Dibm405gp.h128 #define DCRN_DMA0_BASE 0x100 macro
H A Dibm405gpr.h128 #define DCRN_DMA0_BASE 0x100 macro
H A Dibmstb4.h117 #define DCRN_DMA0_BASE 0x0C0 macro
129 #define DCRN_DMA0_BASE 0x0C0 macro
H A Dibmstbx25.h134 #define DCRN_DMA0_BASE 0x0C0 macro
146 #define DCRN_DMA0_BASE 0x0C0 macro
H A Dibmnp405h.h114 #define DCRN_DMA0_BASE 0x100 macro

Completed in 73 milliseconds