Searched refs:CL_3 (Results 1 - 7 of 7) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A Dmem_init.h112 #define SDRAM_CL CL_3
119 #define SDRAM_CL CL_3
126 #define SDRAM_CL CL_3
133 #define SDRAM_CL CL_3
140 #define SDRAM_CL CL_3
H A DdefBF534.h1602 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A Dmem_init.h112 #define SDRAM_CL CL_3
119 #define SDRAM_CL CL_3
126 #define SDRAM_CL CL_3
H A DdefBF532.h1186 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A Dmem_init.h111 #define SDRAM_CL CL_3
118 #define SDRAM_CL CL_3
125 #define SDRAM_CL CL_3
132 #define SDRAM_CL CL_3
H A DdefBF561.h1618 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DdefBF52x_base.h1343 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ macro

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