1/* 2 * File: include/asm-blackfin/mach-bf537/mem_init.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * Copyright 2004-2006 Analog Devices Inc. 13 * 14 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2, or (at your option) 19 * any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; see the file COPYING. 28 * If not, write to the Free Software Foundation, 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \ 33 CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75) 34#if (CONFIG_SCLK_HZ > 119402985) 35#define SDRAM_tRP TRP_2 36#define SDRAM_tRP_num 2 37#define SDRAM_tRAS TRAS_7 38#define SDRAM_tRAS_num 7 39#define SDRAM_tRCD TRCD_2 40#define SDRAM_tWR TWR_2 41#endif 42#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) 43#define SDRAM_tRP TRP_2 44#define SDRAM_tRP_num 2 45#define SDRAM_tRAS TRAS_6 46#define SDRAM_tRAS_num 6 47#define SDRAM_tRCD TRCD_2 48#define SDRAM_tWR TWR_2 49#endif 50#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) 51#define SDRAM_tRP TRP_2 52#define SDRAM_tRP_num 2 53#define SDRAM_tRAS TRAS_5 54#define SDRAM_tRAS_num 5 55#define SDRAM_tRCD TRCD_2 56#define SDRAM_tWR TWR_2 57#endif 58#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) 59#define SDRAM_tRP TRP_2 60#define SDRAM_tRP_num 2 61#define SDRAM_tRAS TRAS_4 62#define SDRAM_tRAS_num 4 63#define SDRAM_tRCD TRCD_2 64#define SDRAM_tWR TWR_2 65#endif 66#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) 67#define SDRAM_tRP TRP_2 68#define SDRAM_tRP_num 2 69#define SDRAM_tRAS TRAS_3 70#define SDRAM_tRAS_num 3 71#define SDRAM_tRCD TRCD_2 72#define SDRAM_tWR TWR_2 73#endif 74#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) 75#define SDRAM_tRP TRP_1 76#define SDRAM_tRP_num 1 77#define SDRAM_tRAS TRAS_4 78#define SDRAM_tRAS_num 3 79#define SDRAM_tRCD TRCD_1 80#define SDRAM_tWR TWR_2 81#endif 82#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) 83#define SDRAM_tRP TRP_1 84#define SDRAM_tRP_num 1 85#define SDRAM_tRAS TRAS_3 86#define SDRAM_tRAS_num 3 87#define SDRAM_tRCD TRCD_1 88#define SDRAM_tWR TWR_2 89#endif 90#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) 91#define SDRAM_tRP TRP_1 92#define SDRAM_tRP_num 1 93#define SDRAM_tRAS TRAS_2 94#define SDRAM_tRAS_num 2 95#define SDRAM_tRCD TRCD_1 96#define SDRAM_tWR TWR_2 97#endif 98#if (CONFIG_SCLK_HZ <= 29850746) 99#define SDRAM_tRP TRP_1 100#define SDRAM_tRP_num 1 101#define SDRAM_tRAS TRAS_1 102#define SDRAM_tRAS_num 1 103#define SDRAM_tRCD TRCD_1 104#define SDRAM_tWR TWR_2 105#endif 106#endif 107 108#if CONFIG_MEM_MT48LC16M16A2TG_75 109 /*SDRAM INFORMATION: */ 110#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 111#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 112#define SDRAM_CL CL_3 113#endif 114 115#if CONFIG_MEM_MT48LC16M8A2TG_75 116 /*SDRAM INFORMATION: */ 117#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 118#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ 119#define SDRAM_CL CL_3 120#endif 121 122#if CONFIG_MEM_MT48LC32M8A2_75 123 /*SDRAM INFORMATION: */ 124#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 125#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 126#define SDRAM_CL CL_3 127#endif 128 129#if CONFIG_MEM_MT48LC64M4A2FB_7E 130 /*SDRAM INFORMATION: */ 131#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 132#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 133#define SDRAM_CL CL_3 134#endif 135 136#if CONFIG_MEM_GENERIC_BOARD 137 /*SDRAM INFORMATION: Modify this for your board */ 138#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 139#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 140#define SDRAM_CL CL_3 141#endif 142 143#if (CONFIG_MEM_SIZE == 128) 144#define SDRAM_SIZE EBSZ_128 145#endif 146#if (CONFIG_MEM_SIZE == 64) 147#define SDRAM_SIZE EBSZ_64 148#endif 149#if (CONFIG_MEM_SIZE == 32) 150#define SDRAM_SIZE EBSZ_32 151#endif 152#if (CONFIG_MEM_SIZE == 16) 153#define SDRAM_SIZE EBSZ_16 154#endif 155#if (CONFIG_MEM_ADD_WIDTH == 11) 156#define SDRAM_WIDTH EBCAW_11 157#endif 158#if (CONFIG_MEM_ADD_WIDTH == 10) 159#define SDRAM_WIDTH EBCAW_10 160#endif 161#if (CONFIG_MEM_ADD_WIDTH == 9) 162#define SDRAM_WIDTH EBCAW_9 163#endif 164#if (CONFIG_MEM_ADD_WIDTH == 8) 165#define SDRAM_WIDTH EBCAW_8 166#endif 167 168#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE) 169 170/* Equation from section 17 (p17-46) of BF533 HRM */ 171#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) 172 173/* Enable SCLK Out */ 174#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) 175 176#if defined CONFIG_CLKIN_HALF 177#define CLKIN_HALF 1 178#else 179#define CLKIN_HALF 0 180#endif 181 182#if defined CONFIG_PLL_BYPASS 183#define PLL_BYPASS 1 184#else 185#define PLL_BYPASS 0 186#endif 187 188/***************************************Currently Not Being Used *********************************/ 189#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 190#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 191#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) 192#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 193#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 194 195#if (flash_EBIU_AMBCTL_TT > 3) 196#define flash_EBIU_AMBCTL0_TT B0TT_4 197#endif 198#if (flash_EBIU_AMBCTL_TT == 3) 199#define flash_EBIU_AMBCTL0_TT B0TT_3 200#endif 201#if (flash_EBIU_AMBCTL_TT == 2) 202#define flash_EBIU_AMBCTL0_TT B0TT_2 203#endif 204#if (flash_EBIU_AMBCTL_TT < 2) 205#define flash_EBIU_AMBCTL0_TT B0TT_1 206#endif 207 208#if (flash_EBIU_AMBCTL_ST > 3) 209#define flash_EBIU_AMBCTL0_ST B0ST_4 210#endif 211#if (flash_EBIU_AMBCTL_ST == 3) 212#define flash_EBIU_AMBCTL0_ST B0ST_3 213#endif 214#if (flash_EBIU_AMBCTL_ST == 2) 215#define flash_EBIU_AMBCTL0_ST B0ST_2 216#endif 217#if (flash_EBIU_AMBCTL_ST < 2) 218#define flash_EBIU_AMBCTL0_ST B0ST_1 219#endif 220 221#if (flash_EBIU_AMBCTL_HT > 2) 222#define flash_EBIU_AMBCTL0_HT B0HT_3 223#endif 224#if (flash_EBIU_AMBCTL_HT == 2) 225#define flash_EBIU_AMBCTL0_HT B0HT_2 226#endif 227#if (flash_EBIU_AMBCTL_HT == 1) 228#define flash_EBIU_AMBCTL0_HT B0HT_1 229#endif 230#if (flash_EBIU_AMBCTL_HT == 1) 231#define flash_EBIU_AMBCTL0_HT B0HT_0 232#endif 233#if (flash_EBIU_AMBCTL_HT == 0) 234#define flash_EBIU_AMBCTL0_HT B0HT_1 235#endif 236 237#if (flash_EBIU_AMBCTL_WAT > 14) 238#define flash_EBIU_AMBCTL0_WAT B0WAT_15 239#endif 240#if (flash_EBIU_AMBCTL_WAT == 14) 241#define flash_EBIU_AMBCTL0_WAT B0WAT_14 242#endif 243#if (flash_EBIU_AMBCTL_WAT == 13) 244#define flash_EBIU_AMBCTL0_WAT B0WAT_13 245#endif 246#if (flash_EBIU_AMBCTL_WAT == 12) 247#define flash_EBIU_AMBCTL0_WAT B0WAT_12 248#endif 249#if (flash_EBIU_AMBCTL_WAT == 11) 250#define flash_EBIU_AMBCTL0_WAT B0WAT_11 251#endif 252#if (flash_EBIU_AMBCTL_WAT == 10) 253#define flash_EBIU_AMBCTL0_WAT B0WAT_10 254#endif 255#if (flash_EBIU_AMBCTL_WAT == 9) 256#define flash_EBIU_AMBCTL0_WAT B0WAT_9 257#endif 258#if (flash_EBIU_AMBCTL_WAT == 8) 259#define flash_EBIU_AMBCTL0_WAT B0WAT_8 260#endif 261#if (flash_EBIU_AMBCTL_WAT == 7) 262#define flash_EBIU_AMBCTL0_WAT B0WAT_7 263#endif 264#if (flash_EBIU_AMBCTL_WAT == 6) 265#define flash_EBIU_AMBCTL0_WAT B0WAT_6 266#endif 267#if (flash_EBIU_AMBCTL_WAT == 5) 268#define flash_EBIU_AMBCTL0_WAT B0WAT_5 269#endif 270#if (flash_EBIU_AMBCTL_WAT == 4) 271#define flash_EBIU_AMBCTL0_WAT B0WAT_4 272#endif 273#if (flash_EBIU_AMBCTL_WAT == 3) 274#define flash_EBIU_AMBCTL0_WAT B0WAT_3 275#endif 276#if (flash_EBIU_AMBCTL_WAT == 2) 277#define flash_EBIU_AMBCTL0_WAT B0WAT_2 278#endif 279#if (flash_EBIU_AMBCTL_WAT == 1) 280#define flash_EBIU_AMBCTL0_WAT B0WAT_1 281#endif 282 283#if (flash_EBIU_AMBCTL_RAT > 14) 284#define flash_EBIU_AMBCTL0_RAT B0RAT_15 285#endif 286#if (flash_EBIU_AMBCTL_RAT == 14) 287#define flash_EBIU_AMBCTL0_RAT B0RAT_14 288#endif 289#if (flash_EBIU_AMBCTL_RAT == 13) 290#define flash_EBIU_AMBCTL0_RAT B0RAT_13 291#endif 292#if (flash_EBIU_AMBCTL_RAT == 12) 293#define flash_EBIU_AMBCTL0_RAT B0RAT_12 294#endif 295#if (flash_EBIU_AMBCTL_RAT == 11) 296#define flash_EBIU_AMBCTL0_RAT B0RAT_11 297#endif 298#if (flash_EBIU_AMBCTL_RAT == 10) 299#define flash_EBIU_AMBCTL0_RAT B0RAT_10 300#endif 301#if (flash_EBIU_AMBCTL_RAT == 9) 302#define flash_EBIU_AMBCTL0_RAT B0RAT_9 303#endif 304#if (flash_EBIU_AMBCTL_RAT == 8) 305#define flash_EBIU_AMBCTL0_RAT B0RAT_8 306#endif 307#if (flash_EBIU_AMBCTL_RAT == 7) 308#define flash_EBIU_AMBCTL0_RAT B0RAT_7 309#endif 310#if (flash_EBIU_AMBCTL_RAT == 6) 311#define flash_EBIU_AMBCTL0_RAT B0RAT_6 312#endif 313#if (flash_EBIU_AMBCTL_RAT == 5) 314#define flash_EBIU_AMBCTL0_RAT B0RAT_5 315#endif 316#if (flash_EBIU_AMBCTL_RAT == 4) 317#define flash_EBIU_AMBCTL0_RAT B0RAT_4 318#endif 319#if (flash_EBIU_AMBCTL_RAT == 3) 320#define flash_EBIU_AMBCTL0_RAT B0RAT_3 321#endif 322#if (flash_EBIU_AMBCTL_RAT == 2) 323#define flash_EBIU_AMBCTL0_RAT B0RAT_2 324#endif 325#if (flash_EBIU_AMBCTL_RAT == 1) 326#define flash_EBIU_AMBCTL0_RAT B0RAT_1 327#endif 328 329#define flash_EBIU_AMBCTL0 \ 330 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ 331 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) 332