Searched refs:CLOCK_CNTL_INDEX (Results 1 - 8 of 8) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/aty/
H A Dradeonfb.h457 save = INREG(CLOCK_CNTL_INDEX);
459 OUTREG(CLOCK_CNTL_INDEX, tmp);
461 OUTREG(CLOCK_CNTL_INDEX, save);
469 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
480 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
H A Dradeon_accel.c177 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
234 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
H A Daty128fb.c532 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
540 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
666 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
678 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
1288 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
H A Dradeon_pm.c1476 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1511 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1632 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1650 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1677 OUTREG8(CLOCK_CNTL_INDEX+1, 0);
H A Dradeon_base.c522 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
1223 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1243 OUTREGP(CLOCK_CNTL_INDEX,
1261 OUTREGP(CLOCK_CNTL_INDEX,
H A Dradeon_monitor.c656 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/video/
H A Daty128.h12 #define CLOCK_CNTL_INDEX 0x0008 macro
H A Dradeon.h306 #define CLOCK_CNTL_INDEX 0x0008 macro
509 /* CLOCK_CNTL_INDEX bit constants */

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