1#ifndef __RADEONFB_H__ 2#define __RADEONFB_H__ 3 4#include <linux/module.h> 5#include <linux/kernel.h> 6#include <linux/sched.h> 7#include <linux/delay.h> 8#include <linux/pci.h> 9#include <linux/fb.h> 10 11 12#ifdef CONFIG_FB_RADEON_I2C 13#include <linux/i2c.h> 14#include <linux/i2c-algo-bit.h> 15#endif 16 17#include <asm/io.h> 18 19#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC) 20#include <asm/prom.h> 21#endif 22 23#include <video/radeon.h> 24 25/*************************************************************** 26 * Most of the definitions here are adapted right from XFree86 * 27 ***************************************************************/ 28 29 30/* 31 * Chip families. Must fit in the low 16 bits of a long word 32 */ 33enum radeon_family { 34 CHIP_FAMILY_UNKNOW, 35 CHIP_FAMILY_LEGACY, 36 CHIP_FAMILY_RADEON, 37 CHIP_FAMILY_RV100, 38 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ 39 CHIP_FAMILY_RV200, 40 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), 41 RS250 (IGP 7000) */ 42 CHIP_FAMILY_R200, 43 CHIP_FAMILY_RV250, 44 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ 45 CHIP_FAMILY_RV280, 46 CHIP_FAMILY_R300, 47 CHIP_FAMILY_R350, 48 CHIP_FAMILY_RV350, 49 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 50 CHIP_FAMILY_R420, /* R420/R423/M18 */ 51 CHIP_FAMILY_RS480, 52 CHIP_FAMILY_LAST, 53}; 54 55#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ 56 ((rinfo)->family == CHIP_FAMILY_RV200) || \ 57 ((rinfo)->family == CHIP_FAMILY_RS100) || \ 58 ((rinfo)->family == CHIP_FAMILY_RS200) || \ 59 ((rinfo)->family == CHIP_FAMILY_RV250) || \ 60 ((rinfo)->family == CHIP_FAMILY_RV280) || \ 61 ((rinfo)->family == CHIP_FAMILY_RS300)) 62 63 64#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ 65 ((rinfo)->family == CHIP_FAMILY_RV350) || \ 66 ((rinfo)->family == CHIP_FAMILY_R350) || \ 67 ((rinfo)->family == CHIP_FAMILY_RV380) || \ 68 ((rinfo)->family == CHIP_FAMILY_R420) || \ 69 ((rinfo)->family == CHIP_FAMILY_RS480) ) 70 71/* 72 * Chip flags 73 */ 74enum radeon_chip_flags { 75 CHIP_FAMILY_MASK = 0x0000ffffUL, 76 CHIP_FLAGS_MASK = 0xffff0000UL, 77 CHIP_IS_MOBILITY = 0x00010000UL, 78 CHIP_IS_IGP = 0x00020000UL, 79 CHIP_HAS_CRTC2 = 0x00040000UL, 80}; 81 82/* 83 * Errata workarounds 84 */ 85enum radeon_errata { 86 CHIP_ERRATA_R300_CG = 0x00000001, 87 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 88 CHIP_ERRATA_PLL_DELAY = 0x00000004, 89}; 90 91 92/* 93 * Monitor types 94 */ 95enum radeon_montype { 96 MT_NONE = 0, 97 MT_CRT, /* CRT */ 98 MT_LCD, /* LCD */ 99 MT_DFP, /* DVI */ 100 MT_CTV, /* composite TV */ 101 MT_STV /* S-Video out */ 102}; 103 104/* 105 * DDC i2c ports 106 */ 107enum ddc_type { 108 ddc_none, 109 ddc_monid, 110 ddc_dvi, 111 ddc_vga, 112 ddc_crt2, 113}; 114 115/* 116 * Connector types 117 */ 118enum conn_type { 119 conn_none, 120 conn_proprietary, 121 conn_crt, 122 conn_DVI_I, 123 conn_DVI_D, 124}; 125 126 127/* 128 * PLL infos 129 */ 130struct pll_info { 131 int ppll_max; 132 int ppll_min; 133 int sclk, mclk; 134 int ref_div; 135 int ref_clk; 136}; 137 138 139/* 140 * This structure contains the various registers manipulated by this 141 * driver for setting or restoring a mode. It's mostly copied from 142 * XFree's RADEONSaveRec structure. A few chip settings might still be 143 * tweaked without beeing reflected or saved in these registers though 144 */ 145struct radeon_regs { 146 /* Common registers */ 147 u32 ovr_clr; 148 u32 ovr_wid_left_right; 149 u32 ovr_wid_top_bottom; 150 u32 ov0_scale_cntl; 151 u32 mpp_tb_config; 152 u32 mpp_gp_config; 153 u32 subpic_cntl; 154 u32 viph_control; 155 u32 i2c_cntl_1; 156 u32 gen_int_cntl; 157 u32 cap0_trig_cntl; 158 u32 cap1_trig_cntl; 159 u32 bus_cntl; 160 u32 surface_cntl; 161 u32 bios_5_scratch; 162 163 /* Other registers to save for VT switches or driver load/unload */ 164 u32 dp_datatype; 165 u32 rbbm_soft_reset; 166 u32 clock_cntl_index; 167 u32 amcgpio_en_reg; 168 u32 amcgpio_mask; 169 170 /* Surface/tiling registers */ 171 u32 surf_lower_bound[8]; 172 u32 surf_upper_bound[8]; 173 u32 surf_info[8]; 174 175 /* CRTC registers */ 176 u32 crtc_gen_cntl; 177 u32 crtc_ext_cntl; 178 u32 dac_cntl; 179 u32 crtc_h_total_disp; 180 u32 crtc_h_sync_strt_wid; 181 u32 crtc_v_total_disp; 182 u32 crtc_v_sync_strt_wid; 183 u32 crtc_offset; 184 u32 crtc_offset_cntl; 185 u32 crtc_pitch; 186 u32 disp_merge_cntl; 187 u32 grph_buffer_cntl; 188 u32 crtc_more_cntl; 189 190 /* CRTC2 registers */ 191 u32 crtc2_gen_cntl; 192 u32 dac2_cntl; 193 u32 disp_output_cntl; 194 u32 disp_hw_debug; 195 u32 disp2_merge_cntl; 196 u32 grph2_buffer_cntl; 197 u32 crtc2_h_total_disp; 198 u32 crtc2_h_sync_strt_wid; 199 u32 crtc2_v_total_disp; 200 u32 crtc2_v_sync_strt_wid; 201 u32 crtc2_offset; 202 u32 crtc2_offset_cntl; 203 u32 crtc2_pitch; 204 205 /* Flat panel regs */ 206 u32 fp_crtc_h_total_disp; 207 u32 fp_crtc_v_total_disp; 208 u32 fp_gen_cntl; 209 u32 fp2_gen_cntl; 210 u32 fp_h_sync_strt_wid; 211 u32 fp2_h_sync_strt_wid; 212 u32 fp_horz_stretch; 213 u32 fp_panel_cntl; 214 u32 fp_v_sync_strt_wid; 215 u32 fp2_v_sync_strt_wid; 216 u32 fp_vert_stretch; 217 u32 lvds_gen_cntl; 218 u32 lvds_pll_cntl; 219 u32 tmds_crc; 220 u32 tmds_transmitter_cntl; 221 222 /* Computed values for PLL */ 223 u32 dot_clock_freq; 224 int feedback_div; 225 int post_div; 226 227 /* PLL registers */ 228 u32 ppll_div_3; 229 u32 ppll_ref_div; 230 u32 vclk_ecp_cntl; 231 u32 clk_cntl_index; 232 233 /* Computed values for PLL2 */ 234 u32 dot_clock_freq_2; 235 int feedback_div_2; 236 int post_div_2; 237 238 /* PLL2 registers */ 239 u32 p2pll_ref_div; 240 u32 p2pll_div_0; 241 u32 htotal_cntl2; 242 243 /* Palette */ 244 int palette_valid; 245}; 246 247struct panel_info { 248 int xres, yres; 249 int valid; 250 int clock; 251 int hOver_plus, hSync_width, hblank; 252 int vOver_plus, vSync_width, vblank; 253 int hAct_high, vAct_high, interlaced; 254 int pwr_delay; 255 int use_bios_dividers; 256 int ref_divider; 257 int post_divider; 258 int fbk_divider; 259}; 260 261struct radeonfb_info; 262 263#ifdef CONFIG_FB_RADEON_I2C 264struct radeon_i2c_chan { 265 struct radeonfb_info *rinfo; 266 u32 ddc_reg; 267 struct i2c_adapter adapter; 268 struct i2c_algo_bit_data algo; 269}; 270#endif 271 272enum radeon_pm_mode { 273 radeon_pm_none = 0, /* Nothing supported */ 274 radeon_pm_d2 = 0x00000001, /* Can do D2 state */ 275 radeon_pm_off = 0x00000002, /* Can resume from D3 cold */ 276}; 277 278typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo); 279 280struct radeonfb_info { 281 struct fb_info *info; 282 283 struct radeon_regs state; 284 struct radeon_regs init_state; 285 286 char name[DEVICE_NAME_SIZE]; 287 288 unsigned long mmio_base_phys; 289 unsigned long fb_base_phys; 290 291 void __iomem *mmio_base; 292 void __iomem *fb_base; 293 294 unsigned long fb_local_base; 295 296 struct pci_dev *pdev; 297#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC) 298 struct device_node *of_node; 299#endif 300 301 void __iomem *bios_seg; 302 int fp_bios_start; 303 304 u32 pseudo_palette[17]; 305 struct { u8 red, green, blue, pad; } 306 palette[256]; 307 308 int chipset; 309 u8 family; 310 u8 rev; 311 unsigned int errata; 312 unsigned long video_ram; 313 unsigned long mapped_vram; 314 int vram_width; 315 int vram_ddr; 316 317 int pitch, bpp, depth; 318 319 int has_CRTC2; 320 int is_mobility; 321 int is_IGP; 322 int reversed_DAC; 323 int reversed_TMDS; 324 struct panel_info panel_info; 325 int mon1_type; 326 u8 *mon1_EDID; 327 struct fb_videomode *mon1_modedb; 328 int mon1_dbsize; 329 int mon2_type; 330 u8 *mon2_EDID; 331 332 u32 dp_gui_master_cntl; 333 334 struct pll_info pll; 335 336 int mtrr_hdl; 337 338 int pm_reg; 339 u32 save_regs[100]; 340 int asleep; 341 int lock_blank; 342 int dynclk; 343 int no_schedule; 344 enum radeon_pm_mode pm_mode; 345 reinit_function_ptr reinit_func; 346 347 /* Lock on register access */ 348 spinlock_t reg_lock; 349 350 /* Timer used for delayed LVDS operations */ 351 struct timer_list lvds_timer; 352 u32 pending_lvds_gen_cntl; 353 354#ifdef CONFIG_FB_RADEON_I2C 355 struct radeon_i2c_chan i2c[4]; 356#endif 357 358 u32 cfg_save[64]; 359}; 360 361 362#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type) 363 364 365/* 366 * Debugging stuffs 367 */ 368#ifdef CONFIG_FB_RADEON_DEBUG 369#define DEBUG 1 370#else 371#define DEBUG 0 372#endif 373 374#if DEBUG 375#define RTRACE printk 376#else 377#define RTRACE if(0) printk 378#endif 379 380 381/* 382 * IO macros 383 */ 384 385/* Note about this function: we have some rare cases where we must not schedule, 386 * this typically happen with our special "wake up early" hook which allows us to 387 * wake up the graphic chip (and thus get the console back) before everything else 388 * on some machines that support that mechanism. At this point, interrupts are off 389 * and scheduling is not permitted 390 */ 391static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) 392{ 393 if (rinfo->no_schedule || oops_in_progress) 394 mdelay(ms); 395 else 396 msleep(ms); 397} 398 399 400#define INREG8(addr) readb((rinfo->mmio_base)+addr) 401#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 402#define INREG16(addr) readw((rinfo->mmio_base)+addr) 403#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 404#define INREG(addr) readl((rinfo->mmio_base)+addr) 405#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 406 407static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, 408 u32 val, u32 mask) 409{ 410 unsigned long flags; 411 unsigned int tmp; 412 413 spin_lock_irqsave(&rinfo->reg_lock, flags); 414 tmp = INREG(addr); 415 tmp &= (mask); 416 tmp |= (val); 417 OUTREG(addr, tmp); 418 spin_unlock_irqrestore(&rinfo->reg_lock, flags); 419} 420 421#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) 422 423/* 424 * Note about PLL register accesses: 425 * 426 * I have removed the spinlock on them on purpose. The driver now 427 * expects that it will only manipulate the PLL registers in normal 428 * task environment, where radeon_msleep() will be called, protected 429 * by a semaphore (currently the console semaphore) so that no conflict 430 * will happen on the PLL register index. 431 * 432 * With the latest changes to the VT layer, this is guaranteed for all 433 * calls except the actual drawing/blits which aren't supposed to use 434 * the PLL registers anyway 435 * 436 * This is very important for the workarounds to work properly. The only 437 * possible exception to this rule is the call to unblank(), which may 438 * be done at irq time if an oops is in progress. 439 */ 440static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo) 441{ 442 if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)) 443 return; 444 445 (void)INREG(CLOCK_CNTL_DATA); 446 (void)INREG(CRTC_GEN_CNTL); 447} 448 449static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo) 450{ 451 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { 452 /* we can't deal with posted writes here ... */ 453 _radeon_msleep(rinfo, 5); 454 } 455 if (rinfo->errata & CHIP_ERRATA_R300_CG) { 456 u32 save, tmp; 457 save = INREG(CLOCK_CNTL_INDEX); 458 tmp = save & ~(0x3f | PLL_WR_EN); 459 OUTREG(CLOCK_CNTL_INDEX, tmp); 460 tmp = INREG(CLOCK_CNTL_DATA); 461 OUTREG(CLOCK_CNTL_INDEX, save); 462 } 463} 464 465static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) 466{ 467 u32 data; 468 469 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); 470 radeon_pll_errata_after_index(rinfo); 471 data = INREG(CLOCK_CNTL_DATA); 472 radeon_pll_errata_after_data(rinfo); 473 return data; 474} 475 476static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, 477 u32 val) 478{ 479 480 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); 481 radeon_pll_errata_after_index(rinfo); 482 OUTREG(CLOCK_CNTL_DATA, val); 483 radeon_pll_errata_after_data(rinfo); 484} 485 486 487static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, 488 u32 val, u32 mask) 489{ 490 unsigned int tmp; 491 492 tmp = __INPLL(rinfo, index); 493 tmp &= (mask); 494 tmp |= (val); 495 __OUTPLL(rinfo, index, tmp); 496} 497 498 499#define INPLL(addr) __INPLL(rinfo, addr) 500#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) 501#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) 502 503 504#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v))) 505#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \ 506 (readb(rinfo->bios_seg + (v) + 1) << 8)) 507#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \ 508 (readb(rinfo->bios_seg + (v) + 1) << 8) | \ 509 (readb(rinfo->bios_seg + (v) + 2) << 16) | \ 510 (readb(rinfo->bios_seg + (v) + 3) << 24)) 511 512/* 513 * Inline utilities 514 */ 515static inline int round_div(int num, int den) 516{ 517 return (num + (den / 2)) / den; 518} 519 520static inline int var_to_depth(const struct fb_var_screeninfo *var) 521{ 522 if (var->bits_per_pixel != 16) 523 return var->bits_per_pixel; 524 return (var->green.length == 5) ? 15 : 16; 525} 526 527static inline u32 radeon_get_dstbpp(u16 depth) 528{ 529 switch (depth) { 530 case 8: 531 return DST_8BPP; 532 case 15: 533 return DST_15BPP; 534 case 16: 535 return DST_16BPP; 536 case 32: 537 return DST_32BPP; 538 default: 539 return 0; 540 } 541} 542 543/* 544 * 2D Engine helper routines 545 */ 546static inline void radeon_engine_flush (struct radeonfb_info *rinfo) 547{ 548 int i; 549 550 /* initiate flush */ 551 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, 552 ~RB2D_DC_FLUSH_ALL); 553 554 for (i=0; i < 2000000; i++) { 555 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) 556 return; 557 udelay(1); 558 } 559 printk(KERN_ERR "radeonfb: Flush Timeout !\n"); 560} 561 562 563static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 564{ 565 int i; 566 567 for (i=0; i<2000000; i++) { 568 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) 569 return; 570 udelay(1); 571 } 572 printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); 573} 574 575 576static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) 577{ 578 int i; 579 580 /* ensure FIFO is empty before waiting for idle */ 581 _radeon_fifo_wait (rinfo, 64); 582 583 for (i=0; i<2000000; i++) { 584 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 585 radeon_engine_flush (rinfo); 586 return; 587 } 588 udelay(1); 589 } 590 printk(KERN_ERR "radeonfb: Idle Timeout !\n"); 591} 592 593 594#define radeon_engine_idle() _radeon_engine_idle(rinfo) 595#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) 596#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 597 598 599/* I2C Functions */ 600extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo); 601extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo); 602extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid); 603 604/* PM Functions */ 605extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state); 606extern int radeonfb_pci_resume(struct pci_dev *pdev); 607extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep); 608extern void radeonfb_pm_exit(struct radeonfb_info *rinfo); 609 610/* Monitor probe functions */ 611extern void radeon_probe_screens(struct radeonfb_info *rinfo, 612 const char *monitor_layout, int ignore_edid); 613extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option); 614extern int radeon_match_mode(struct radeonfb_info *rinfo, 615 struct fb_var_screeninfo *dest, 616 const struct fb_var_screeninfo *src); 617 618/* Accel functions */ 619extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region); 620extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 621extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image); 622extern int radeonfb_sync(struct fb_info *info); 623extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 624extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 625 626/* Other functions */ 627extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 628extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, 629 int reg_only); 630 631/* Backlight functions */ 632#ifdef CONFIG_FB_RADEON_BACKLIGHT 633extern void radeonfb_bl_init(struct radeonfb_info *rinfo); 634extern void radeonfb_bl_exit(struct radeonfb_info *rinfo); 635#else 636static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {} 637static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {} 638#endif 639 640#endif /* __RADEONFB_H__ */ 641