1/* $Id: aty128fb.c,v 1.1.1.1 2007/08/03 18:53:03 Exp $ 2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 3 * 4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> 5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 6 * 7 * Ani Joshi / Jeff Garzik 8 * - Code cleanup 9 * 10 * Michel Danzer <michdaen@iiic.ethz.ch> 11 * - 15/16 bit cleanup 12 * - fix panning 13 * 14 * Benjamin Herrenschmidt 15 * - pmac-specific PM stuff 16 * - various fixes & cleanups 17 * 18 * Andreas Hundt <andi@convergence.de> 19 * - FB_ACTIVATE fixes 20 * 21 * Paul Mackerras <paulus@samba.org> 22 * - Convert to new framebuffer API, 23 * fix colormap setting at 16 bits/pixel (565) 24 * 25 * Paul Mundt 26 * - PCI hotplug 27 * 28 * Jon Smirl <jonsmirl@yahoo.com> 29 * - PCI ID update 30 * - replace ROM BIOS search 31 * 32 * Based off of Geert's atyfb.c and vfb.c. 33 * 34 * TODO: 35 * - monitor sensing (DDC) 36 * - virtual display 37 * - other platform support (only ppc/x86 supported) 38 * - hardware cursor support 39 * 40 * Please cc: your patches to brad@neruo.com. 41 */ 42 43/* 44 * A special note of gratitude to ATI's devrel for providing documentation, 45 * example code and hardware. Thanks Nitya. -atong and brad 46 */ 47 48 49#include <linux/module.h> 50#include <linux/moduleparam.h> 51#include <linux/kernel.h> 52#include <linux/errno.h> 53#include <linux/string.h> 54#include <linux/mm.h> 55#include <linux/slab.h> 56#include <linux/vmalloc.h> 57#include <linux/delay.h> 58#include <linux/interrupt.h> 59#include <asm/uaccess.h> 60#include <linux/fb.h> 61#include <linux/init.h> 62#include <linux/pci.h> 63#include <linux/ioport.h> 64#include <linux/console.h> 65#include <linux/backlight.h> 66#include <asm/io.h> 67 68#ifdef CONFIG_PPC_PMAC 69#include <asm/machdep.h> 70#include <asm/pmac_feature.h> 71#include <asm/prom.h> 72#include <asm/pci-bridge.h> 73#include "../macmodes.h" 74#endif 75 76#ifdef CONFIG_PMAC_BACKLIGHT 77#include <asm/backlight.h> 78#endif 79 80#ifdef CONFIG_BOOTX_TEXT 81#include <asm/btext.h> 82#endif /* CONFIG_BOOTX_TEXT */ 83 84#ifdef CONFIG_MTRR 85#include <asm/mtrr.h> 86#endif 87 88#include <video/aty128.h> 89 90/* Debug flag */ 91#undef DEBUG 92 93#ifdef DEBUG 94#define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args); 95#else 96#define DBG(fmt, args...) 97#endif 98 99#ifndef CONFIG_PPC_PMAC 100/* default mode */ 101static struct fb_var_screeninfo default_var __devinitdata = { 102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 103 640, 480, 640, 480, 0, 0, 8, 0, 104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 106 0, FB_VMODE_NONINTERLACED 107}; 108 109#else /* CONFIG_PPC_PMAC */ 110/* default to 1024x768 at 75Hz on PPC - this will work 111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 112static struct fb_var_screeninfo default_var = { 113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 114 1024, 768, 1024, 768, 0, 0, 8, 0, 115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 118 FB_VMODE_NONINTERLACED 119}; 120#endif /* CONFIG_PPC_PMAC */ 121 122/* default modedb mode */ 123/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 124static struct fb_videomode defaultmode __devinitdata = { 125 .refresh = 60, 126 .xres = 640, 127 .yres = 480, 128 .pixclock = 39722, 129 .left_margin = 48, 130 .right_margin = 16, 131 .upper_margin = 33, 132 .lower_margin = 10, 133 .hsync_len = 96, 134 .vsync_len = 2, 135 .sync = 0, 136 .vmode = FB_VMODE_NONINTERLACED 137}; 138 139/* Chip generations */ 140enum { 141 rage_128, 142 rage_128_pci, 143 rage_128_pro, 144 rage_128_pro_pci, 145 rage_M3, 146 rage_M3_pci, 147 rage_M4, 148 rage_128_ultra, 149}; 150 151/* Must match above enum */ 152static const char *r128_family[] __devinitdata = { 153 "AGP", 154 "PCI", 155 "PRO AGP", 156 "PRO PCI", 157 "M3 AGP", 158 "M3 PCI", 159 "M4 AGP", 160 "Ultra AGP", 161}; 162 163/* 164 * PCI driver prototypes 165 */ 166static int aty128_probe(struct pci_dev *pdev, 167 const struct pci_device_id *ent); 168static void aty128_remove(struct pci_dev *pdev); 169static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state); 170static int aty128_pci_resume(struct pci_dev *pdev); 171static int aty128_do_resume(struct pci_dev *pdev); 172 173/* supported Rage128 chipsets */ 174static struct pci_device_id aty128_pci_tbl[] = { 175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, 177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, 179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, 198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, 200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, 202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, 204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, 206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, 210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, 212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, 214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, 216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, 218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, 220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, 222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, 224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, 226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, 228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, 230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, 232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, 234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, 236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, 238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, 240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, 242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, 244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, 246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, 248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, 250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, 252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, 254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, 264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, 266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, 268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 269 { 0, } 270}; 271 272MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); 273 274static struct pci_driver aty128fb_driver = { 275 .name = "aty128fb", 276 .id_table = aty128_pci_tbl, 277 .probe = aty128_probe, 278 .remove = __devexit_p(aty128_remove), 279 .suspend = aty128_pci_suspend, 280 .resume = aty128_pci_resume, 281}; 282 283/* packed BIOS settings */ 284#ifndef CONFIG_PPC 285typedef struct { 286 u8 clock_chip_type; 287 u8 struct_size; 288 u8 accelerator_entry; 289 u8 VGA_entry; 290 u16 VGA_table_offset; 291 u16 POST_table_offset; 292 u16 XCLK; 293 u16 MCLK; 294 u8 num_PLL_blocks; 295 u8 size_PLL_blocks; 296 u16 PCLK_ref_freq; 297 u16 PCLK_ref_divider; 298 u32 PCLK_min_freq; 299 u32 PCLK_max_freq; 300 u16 MCLK_ref_freq; 301 u16 MCLK_ref_divider; 302 u32 MCLK_min_freq; 303 u32 MCLK_max_freq; 304 u16 XCLK_ref_freq; 305 u16 XCLK_ref_divider; 306 u32 XCLK_min_freq; 307 u32 XCLK_max_freq; 308} __attribute__ ((packed)) PLL_BLOCK; 309#endif /* !CONFIG_PPC */ 310 311/* onboard memory information */ 312struct aty128_meminfo { 313 u8 ML; 314 u8 MB; 315 u8 Trcd; 316 u8 Trp; 317 u8 Twr; 318 u8 CL; 319 u8 Tr2w; 320 u8 LoopLatency; 321 u8 DspOn; 322 u8 Rloop; 323 const char *name; 324}; 325 326/* various memory configurations */ 327static const struct aty128_meminfo sdr_128 = 328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" }; 329static const struct aty128_meminfo sdr_64 = 330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" }; 331static const struct aty128_meminfo sdr_sgram = 332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" }; 333static const struct aty128_meminfo ddr_sgram = 334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" }; 335 336static struct fb_fix_screeninfo aty128fb_fix __devinitdata = { 337 .id = "ATY Rage128", 338 .type = FB_TYPE_PACKED_PIXELS, 339 .visual = FB_VISUAL_PSEUDOCOLOR, 340 .xpanstep = 8, 341 .ypanstep = 1, 342 .mmio_len = 0x2000, 343 .accel = FB_ACCEL_ATI_RAGE128, 344}; 345 346static char *mode_option __devinitdata = NULL; 347 348#ifdef CONFIG_PPC_PMAC 349static int default_vmode __devinitdata = VMODE_1024_768_60; 350static int default_cmode __devinitdata = CMODE_8; 351#endif 352 353static int default_crt_on __devinitdata = 0; 354static int default_lcd_on __devinitdata = 1; 355 356#ifdef CONFIG_MTRR 357static int mtrr = 1; 358#endif 359 360#ifdef CONFIG_PMAC_BACKLIGHT 361static int backlight __devinitdata = 1; 362#else 363static int backlight __devinitdata = 0; 364#endif 365 366/* PLL constants */ 367struct aty128_constants { 368 u32 ref_clk; 369 u32 ppll_min; 370 u32 ppll_max; 371 u32 ref_divider; 372 u32 xclk; 373 u32 fifo_width; 374 u32 fifo_depth; 375}; 376 377struct aty128_crtc { 378 u32 gen_cntl; 379 u32 h_total, h_sync_strt_wid; 380 u32 v_total, v_sync_strt_wid; 381 u32 pitch; 382 u32 offset, offset_cntl; 383 u32 xoffset, yoffset; 384 u32 vxres, vyres; 385 u32 depth, bpp; 386}; 387 388struct aty128_pll { 389 u32 post_divider; 390 u32 feedback_divider; 391 u32 vclk; 392}; 393 394struct aty128_ddafifo { 395 u32 dda_config; 396 u32 dda_on_off; 397}; 398 399/* register values for a specific mode */ 400struct aty128fb_par { 401 struct aty128_crtc crtc; 402 struct aty128_pll pll; 403 struct aty128_ddafifo fifo_reg; 404 u32 accel_flags; 405 struct aty128_constants constants; /* PLL and others */ 406 void __iomem *regbase; /* remapped mmio */ 407 u32 vram_size; /* onboard video ram */ 408 int chip_gen; 409 const struct aty128_meminfo *mem; /* onboard mem info */ 410#ifdef CONFIG_MTRR 411 struct { int vram; int vram_valid; } mtrr; 412#endif 413 int blitter_may_be_busy; 414 int fifo_slots; /* free slots in FIFO (64 max) */ 415 416 int pm_reg; 417 int crt_on, lcd_on; 418 struct pci_dev *pdev; 419 struct fb_info *next; 420 int asleep; 421 int lock_blank; 422 423 u8 red[32]; /* see aty128fb_setcolreg */ 424 u8 green[64]; 425 u8 blue[32]; 426 u32 pseudo_palette[16]; /* used for TRUECOLOR */ 427}; 428 429 430#define round_div(n, d) ((n+(d/2))/d) 431 432static int aty128fb_check_var(struct fb_var_screeninfo *var, 433 struct fb_info *info); 434static int aty128fb_set_par(struct fb_info *info); 435static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 436 u_int transp, struct fb_info *info); 437static int aty128fb_pan_display(struct fb_var_screeninfo *var, 438 struct fb_info *fb); 439static int aty128fb_blank(int blank, struct fb_info *fb); 440static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); 441static int aty128fb_sync(struct fb_info *info); 442 443 /* 444 * Internal routines 445 */ 446 447static int aty128_encode_var(struct fb_var_screeninfo *var, 448 const struct aty128fb_par *par); 449static int aty128_decode_var(struct fb_var_screeninfo *var, 450 struct aty128fb_par *par); 451static void aty128_timings(struct aty128fb_par *par); 452static void aty128_init_engine(struct aty128fb_par *par); 453static void aty128_reset_engine(const struct aty128fb_par *par); 454static void aty128_flush_pixel_cache(const struct aty128fb_par *par); 455static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); 456static void wait_for_fifo(u16 entries, struct aty128fb_par *par); 457static void wait_for_idle(struct aty128fb_par *par); 458static u32 depth_to_dst(u32 depth); 459 460#ifdef CONFIG_FB_ATY128_BACKLIGHT 461static void aty128_bl_set_power(struct fb_info *info, int power); 462#endif 463 464#define BIOS_IN8(v) (readb(bios + (v))) 465#define BIOS_IN16(v) (readb(bios + (v)) | \ 466 (readb(bios + (v) + 1) << 8)) 467#define BIOS_IN32(v) (readb(bios + (v)) | \ 468 (readb(bios + (v) + 1) << 8) | \ 469 (readb(bios + (v) + 2) << 16) | \ 470 (readb(bios + (v) + 3) << 24)) 471 472 473static struct fb_ops aty128fb_ops = { 474 .owner = THIS_MODULE, 475 .fb_check_var = aty128fb_check_var, 476 .fb_set_par = aty128fb_set_par, 477 .fb_setcolreg = aty128fb_setcolreg, 478 .fb_pan_display = aty128fb_pan_display, 479 .fb_blank = aty128fb_blank, 480 .fb_ioctl = aty128fb_ioctl, 481 .fb_sync = aty128fb_sync, 482 .fb_fillrect = cfb_fillrect, 483 .fb_copyarea = cfb_copyarea, 484 .fb_imageblit = cfb_imageblit, 485}; 486 487 /* 488 * Functions to read from/write to the mmio registers 489 * - endian conversions may possibly be avoided by 490 * using the other register aperture. TODO. 491 */ 492static inline u32 _aty_ld_le32(volatile unsigned int regindex, 493 const struct aty128fb_par *par) 494{ 495 return readl (par->regbase + regindex); 496} 497 498static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 499 const struct aty128fb_par *par) 500{ 501 writel (val, par->regbase + regindex); 502} 503 504static inline u8 _aty_ld_8(unsigned int regindex, 505 const struct aty128fb_par *par) 506{ 507 return readb (par->regbase + regindex); 508} 509 510static inline void _aty_st_8(unsigned int regindex, u8 val, 511 const struct aty128fb_par *par) 512{ 513 writeb (val, par->regbase + regindex); 514} 515 516#define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) 517#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) 518#define aty_ld_8(regindex) _aty_ld_8(regindex, par) 519#define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) 520 521 /* 522 * Functions to read from/write to the pll registers 523 */ 524 525#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) 526#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) 527 528 529static u32 _aty_ld_pll(unsigned int pll_index, 530 const struct aty128fb_par *par) 531{ 532 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 533 return aty_ld_le32(CLOCK_CNTL_DATA); 534} 535 536 537static void _aty_st_pll(unsigned int pll_index, u32 val, 538 const struct aty128fb_par *par) 539{ 540 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 541 aty_st_le32(CLOCK_CNTL_DATA, val); 542} 543 544 545/* return true when the PLL has completed an atomic update */ 546static int aty_pll_readupdate(const struct aty128fb_par *par) 547{ 548 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 549} 550 551 552static void aty_pll_wait_readupdate(const struct aty128fb_par *par) 553{ 554 unsigned long timeout = jiffies + HZ/100; // should be more than enough 555 int reset = 1; 556 557 while (time_before(jiffies, timeout)) 558 if (aty_pll_readupdate(par)) { 559 reset = 0; 560 break; 561 } 562 563 if (reset) /* reset engine?? */ 564 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 565} 566 567 568/* tell PLL to update */ 569static void aty_pll_writeupdate(const struct aty128fb_par *par) 570{ 571 aty_pll_wait_readupdate(par); 572 573 aty_st_pll(PPLL_REF_DIV, 574 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 575} 576 577 578/* write to the scratch register to test r/w functionality */ 579static int __devinit register_test(const struct aty128fb_par *par) 580{ 581 u32 val; 582 int flag = 0; 583 584 val = aty_ld_le32(BIOS_0_SCRATCH); 585 586 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 587 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 588 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 589 590 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 591 flag = 1; 592 } 593 594 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 595 return flag; 596} 597 598 599/* 600 * Accelerator engine functions 601 */ 602static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) 603{ 604 int i; 605 606 for (;;) { 607 for (i = 0; i < 2000000; i++) { 608 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 609 if (par->fifo_slots >= entries) 610 return; 611 } 612 aty128_reset_engine(par); 613 } 614} 615 616 617static void wait_for_idle(struct aty128fb_par *par) 618{ 619 int i; 620 621 do_wait_for_fifo(64, par); 622 623 for (;;) { 624 for (i = 0; i < 2000000; i++) { 625 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 626 aty128_flush_pixel_cache(par); 627 par->blitter_may_be_busy = 0; 628 return; 629 } 630 } 631 aty128_reset_engine(par); 632 } 633} 634 635 636static void wait_for_fifo(u16 entries, struct aty128fb_par *par) 637{ 638 if (par->fifo_slots < entries) 639 do_wait_for_fifo(64, par); 640 par->fifo_slots -= entries; 641} 642 643 644static void aty128_flush_pixel_cache(const struct aty128fb_par *par) 645{ 646 int i; 647 u32 tmp; 648 649 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 650 tmp &= ~(0x00ff); 651 tmp |= 0x00ff; 652 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 653 654 for (i = 0; i < 2000000; i++) 655 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 656 break; 657} 658 659 660static void aty128_reset_engine(const struct aty128fb_par *par) 661{ 662 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 663 664 aty128_flush_pixel_cache(par); 665 666 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 667 mclk_cntl = aty_ld_pll(MCLK_CNTL); 668 669 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 670 671 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 672 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 673 aty_ld_le32(GEN_RESET_CNTL); 674 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 675 aty_ld_le32(GEN_RESET_CNTL); 676 677 aty_st_pll(MCLK_CNTL, mclk_cntl); 678 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 679 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 680 681 /* use old pio mode */ 682 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 683 684 DBG("engine reset"); 685} 686 687 688static void aty128_init_engine(struct aty128fb_par *par) 689{ 690 u32 pitch_value; 691 692 wait_for_idle(par); 693 694 /* 3D scaler not spoken here */ 695 wait_for_fifo(1, par); 696 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 697 698 aty128_reset_engine(par); 699 700 pitch_value = par->crtc.pitch; 701 if (par->crtc.bpp == 24) { 702 pitch_value = pitch_value * 3; 703 } 704 705 wait_for_fifo(4, par); 706 /* setup engine offset registers */ 707 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 708 709 /* setup engine pitch registers */ 710 aty_st_le32(DEFAULT_PITCH, pitch_value); 711 712 /* set the default scissor register to max dimensions */ 713 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 714 715 /* set the drawing controls registers */ 716 aty_st_le32(DP_GUI_MASTER_CNTL, 717 GMC_SRC_PITCH_OFFSET_DEFAULT | 718 GMC_DST_PITCH_OFFSET_DEFAULT | 719 GMC_SRC_CLIP_DEFAULT | 720 GMC_DST_CLIP_DEFAULT | 721 GMC_BRUSH_SOLIDCOLOR | 722 (depth_to_dst(par->crtc.depth) << 8) | 723 GMC_SRC_DSTCOLOR | 724 GMC_BYTE_ORDER_MSB_TO_LSB | 725 GMC_DP_CONVERSION_TEMP_6500 | 726 ROP3_PATCOPY | 727 GMC_DP_SRC_RECT | 728 GMC_3D_FCN_EN_CLR | 729 GMC_DST_CLR_CMP_FCN_CLEAR | 730 GMC_AUX_CLIP_CLEAR | 731 GMC_WRITE_MASK_SET); 732 733 wait_for_fifo(8, par); 734 /* clear the line drawing registers */ 735 aty_st_le32(DST_BRES_ERR, 0); 736 aty_st_le32(DST_BRES_INC, 0); 737 aty_st_le32(DST_BRES_DEC, 0); 738 739 /* set brush color registers */ 740 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 741 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 742 743 /* set source color registers */ 744 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 745 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 746 747 /* default write mask */ 748 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 749 750 /* Wait for all the writes to be completed before returning */ 751 wait_for_idle(par); 752} 753 754 755/* convert depth values to their register representation */ 756static u32 depth_to_dst(u32 depth) 757{ 758 if (depth <= 8) 759 return DST_8BPP; 760 else if (depth <= 15) 761 return DST_15BPP; 762 else if (depth == 16) 763 return DST_16BPP; 764 else if (depth <= 24) 765 return DST_24BPP; 766 else if (depth <= 32) 767 return DST_32BPP; 768 769 return -EINVAL; 770} 771 772/* 773 * PLL informations retreival 774 */ 775 776 777#ifndef __sparc__ 778static void __iomem * __devinit aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev) 779{ 780 u16 dptr; 781 u8 rom_type; 782 void __iomem *bios; 783 size_t rom_size; 784 785 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ 786 unsigned int temp; 787 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 788 temp &= 0x00ffffffu; 789 temp |= 0x04 << 24; 790 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); 791 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 792 793 bios = pci_map_rom(dev, &rom_size); 794 795 if (!bios) { 796 printk(KERN_ERR "aty128fb: ROM failed to map\n"); 797 return NULL; 798 } 799 800 /* Very simple test to make sure it appeared */ 801 if (BIOS_IN16(0) != 0xaa55) { 802 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " 803 " be 0xaa55\n", BIOS_IN16(0)); 804 goto failed; 805 } 806 807 /* Look for the PCI data to check the ROM type */ 808 dptr = BIOS_IN16(0x18); 809 810 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM 811 * for now, until I've verified this works everywhere. The goal here is more 812 * to phase out Open Firmware images. 813 * 814 * Currently, we only look at the first PCI data, we could iteratre and deal with 815 * them all, and we should use fb_bios_start relative to start of image and not 816 * relative start of ROM, but so far, I never found a dual-image ATI card 817 * 818 * typedef struct { 819 * u32 signature; + 0x00 820 * u16 vendor; + 0x04 821 * u16 device; + 0x06 822 * u16 reserved_1; + 0x08 823 * u16 dlen; + 0x0a 824 * u8 drevision; + 0x0c 825 * u8 class_hi; + 0x0d 826 * u16 class_lo; + 0x0e 827 * u16 ilen; + 0x10 828 * u16 irevision; + 0x12 829 * u8 type; + 0x14 830 * u8 indicator; + 0x15 831 * u16 reserved_2; + 0x16 832 * } pci_data_t; 833 */ 834 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 835 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", 836 BIOS_IN32(dptr)); 837 goto anyway; 838 } 839 rom_type = BIOS_IN8(dptr + 0x14); 840 switch(rom_type) { 841 case 0: 842 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); 843 break; 844 case 1: 845 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); 846 goto failed; 847 case 2: 848 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); 849 goto failed; 850 default: 851 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type); 852 goto failed; 853 } 854 anyway: 855 return bios; 856 857 failed: 858 pci_unmap_rom(dev, bios); 859 return NULL; 860} 861 862static void __devinit aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios) 863{ 864 unsigned int bios_hdr; 865 unsigned int bios_pll; 866 867 bios_hdr = BIOS_IN16(0x48); 868 bios_pll = BIOS_IN16(bios_hdr + 0x30); 869 870 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); 871 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); 872 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 873 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); 874 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); 875 876 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 877 par->constants.ppll_max, par->constants.ppll_min, 878 par->constants.xclk, par->constants.ref_divider, 879 par->constants.ref_clk); 880 881} 882 883#ifdef CONFIG_X86 884static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par) 885{ 886 /* I simplified this code as we used to miss the signatures in 887 * a lot of case. It's now closer to XFree, we just don't check 888 * for signatures at all... Something better will have to be done 889 * if we end up having conflicts 890 */ 891 u32 segstart; 892 unsigned char __iomem *rom_base = NULL; 893 894 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 895 rom_base = ioremap(segstart, 0x10000); 896 if (rom_base == NULL) 897 return NULL; 898 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 899 break; 900 iounmap(rom_base); 901 rom_base = NULL; 902 } 903 return rom_base; 904} 905#endif 906#endif /* ndef(__sparc__) */ 907 908/* fill in known card constants if pll_block is not available */ 909static void __devinit aty128_timings(struct aty128fb_par *par) 910{ 911#ifdef CONFIG_PPC_OF 912 /* instead of a table lookup, assume OF has properly 913 * setup the PLL registers and use their values 914 * to set the XCLK values and reference divider values */ 915 916 u32 x_mpll_ref_fb_div; 917 u32 xclk_cntl; 918 u32 Nx, M; 919 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; 920#endif 921 922 if (!par->constants.ref_clk) 923 par->constants.ref_clk = 2950; 924 925#ifdef CONFIG_PPC_OF 926 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 927 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 928 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 929 M = x_mpll_ref_fb_div & 0x0000ff; 930 931 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 932 (M * PostDivSet[xclk_cntl])); 933 934 par->constants.ref_divider = 935 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 936#endif 937 938 if (!par->constants.ref_divider) { 939 par->constants.ref_divider = 0x3b; 940 941 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 942 aty_pll_writeupdate(par); 943 } 944 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); 945 aty_pll_writeupdate(par); 946 947 /* from documentation */ 948 if (!par->constants.ppll_min) 949 par->constants.ppll_min = 12500; 950 if (!par->constants.ppll_max) 951 par->constants.ppll_max = 25000; /* 23000 on some cards? */ 952 if (!par->constants.xclk) 953 par->constants.xclk = 0x1d4d; /* same as mclk */ 954 955 par->constants.fifo_width = 128; 956 par->constants.fifo_depth = 32; 957 958 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 959 case 0: 960 par->mem = &sdr_128; 961 break; 962 case 1: 963 par->mem = &sdr_sgram; 964 break; 965 case 2: 966 par->mem = &ddr_sgram; 967 break; 968 default: 969 par->mem = &sdr_sgram; 970 } 971} 972 973 974 975/* 976 * CRTC programming 977 */ 978 979/* Program the CRTC registers */ 980static void aty128_set_crtc(const struct aty128_crtc *crtc, 981 const struct aty128fb_par *par) 982{ 983 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 984 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 985 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 986 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 987 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 988 aty_st_le32(CRTC_PITCH, crtc->pitch); 989 aty_st_le32(CRTC_OFFSET, crtc->offset); 990 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 991 /* Disable ATOMIC updating. Is this the right place? */ 992 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 993} 994 995 996static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, 997 struct aty128_crtc *crtc, 998 const struct aty128fb_par *par) 999{ 1000 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 1001 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 1002 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 1003 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1004 u32 depth, bytpp; 1005 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 1006 1007 /* input */ 1008 xres = var->xres; 1009 yres = var->yres; 1010 vxres = var->xres_virtual; 1011 vyres = var->yres_virtual; 1012 xoffset = var->xoffset; 1013 yoffset = var->yoffset; 1014 bpp = var->bits_per_pixel; 1015 left = var->left_margin; 1016 right = var->right_margin; 1017 upper = var->upper_margin; 1018 lower = var->lower_margin; 1019 hslen = var->hsync_len; 1020 vslen = var->vsync_len; 1021 sync = var->sync; 1022 vmode = var->vmode; 1023 1024 if (bpp != 16) 1025 depth = bpp; 1026 else 1027 depth = (var->green.length == 6) ? 16 : 15; 1028 1029 /* check for mode eligibility 1030 * accept only non interlaced modes */ 1031 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 1032 return -EINVAL; 1033 1034 /* convert (and round up) and validate */ 1035 xres = (xres + 7) & ~7; 1036 xoffset = (xoffset + 7) & ~7; 1037 1038 if (vxres < xres + xoffset) 1039 vxres = xres + xoffset; 1040 1041 if (vyres < yres + yoffset) 1042 vyres = yres + yoffset; 1043 1044 /* convert depth into ATI register depth */ 1045 dst = depth_to_dst(depth); 1046 1047 if (dst == -EINVAL) { 1048 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 1049 return -EINVAL; 1050 } 1051 1052 /* convert register depth to bytes per pixel */ 1053 bytpp = mode_bytpp[dst]; 1054 1055 /* make sure there is enough video ram for the mode */ 1056 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { 1057 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 1058 return -EINVAL; 1059 } 1060 1061 h_disp = (xres >> 3) - 1; 1062 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 1063 1064 v_disp = yres - 1; 1065 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 1066 1067 /* check to make sure h_total and v_total are in range */ 1068 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 1069 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 1070 return -EINVAL; 1071 } 1072 1073 h_sync_wid = (hslen + 7) >> 3; 1074 if (h_sync_wid == 0) 1075 h_sync_wid = 1; 1076 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 1077 h_sync_wid = 0x3f; 1078 1079 h_sync_strt = (h_disp << 3) + right; 1080 1081 v_sync_wid = vslen; 1082 if (v_sync_wid == 0) 1083 v_sync_wid = 1; 1084 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 1085 v_sync_wid = 0x1f; 1086 1087 v_sync_strt = v_disp + lower; 1088 1089 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1090 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1091 1092 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1093 1094 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 1095 1096 crtc->h_total = h_total | (h_disp << 16); 1097 crtc->v_total = v_total | (v_disp << 16); 1098 1099 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | 1100 (h_sync_pol << 23); 1101 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 1102 (v_sync_pol << 23); 1103 1104 crtc->pitch = vxres >> 3; 1105 1106 crtc->offset = 0; 1107 1108 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 1109 crtc->offset_cntl = 0x00010000; 1110 else 1111 crtc->offset_cntl = 0; 1112 1113 crtc->vxres = vxres; 1114 crtc->vyres = vyres; 1115 crtc->xoffset = xoffset; 1116 crtc->yoffset = yoffset; 1117 crtc->depth = depth; 1118 crtc->bpp = bpp; 1119 1120 return 0; 1121} 1122 1123 1124static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 1125{ 1126 1127 /* fill in pixel info */ 1128 var->red.msb_right = 0; 1129 var->green.msb_right = 0; 1130 var->blue.offset = 0; 1131 var->blue.msb_right = 0; 1132 var->transp.offset = 0; 1133 var->transp.length = 0; 1134 var->transp.msb_right = 0; 1135 switch (pix_width) { 1136 case CRTC_PIX_WIDTH_8BPP: 1137 var->bits_per_pixel = 8; 1138 var->red.offset = 0; 1139 var->red.length = 8; 1140 var->green.offset = 0; 1141 var->green.length = 8; 1142 var->blue.length = 8; 1143 break; 1144 case CRTC_PIX_WIDTH_15BPP: 1145 var->bits_per_pixel = 16; 1146 var->red.offset = 10; 1147 var->red.length = 5; 1148 var->green.offset = 5; 1149 var->green.length = 5; 1150 var->blue.length = 5; 1151 break; 1152 case CRTC_PIX_WIDTH_16BPP: 1153 var->bits_per_pixel = 16; 1154 var->red.offset = 11; 1155 var->red.length = 5; 1156 var->green.offset = 5; 1157 var->green.length = 6; 1158 var->blue.length = 5; 1159 break; 1160 case CRTC_PIX_WIDTH_24BPP: 1161 var->bits_per_pixel = 24; 1162 var->red.offset = 16; 1163 var->red.length = 8; 1164 var->green.offset = 8; 1165 var->green.length = 8; 1166 var->blue.length = 8; 1167 break; 1168 case CRTC_PIX_WIDTH_32BPP: 1169 var->bits_per_pixel = 32; 1170 var->red.offset = 16; 1171 var->red.length = 8; 1172 var->green.offset = 8; 1173 var->green.length = 8; 1174 var->blue.length = 8; 1175 var->transp.offset = 24; 1176 var->transp.length = 8; 1177 break; 1178 default: 1179 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1180 return -EINVAL; 1181 } 1182 1183 return 0; 1184} 1185 1186 1187static int aty128_crtc_to_var(const struct aty128_crtc *crtc, 1188 struct fb_var_screeninfo *var) 1189{ 1190 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1191 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1192 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1193 u32 pix_width; 1194 1195 /* fun with masking */ 1196 h_total = crtc->h_total & 0x1ff; 1197 h_disp = (crtc->h_total >> 16) & 0xff; 1198 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1199 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1200 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1201 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1202 v_total = crtc->v_total & 0x7ff; 1203 v_disp = (crtc->v_total >> 16) & 0x7ff; 1204 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1205 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1206 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1207 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1208 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1209 1210 /* do conversions */ 1211 xres = (h_disp + 1) << 3; 1212 yres = v_disp + 1; 1213 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1214 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1215 hslen = h_sync_wid << 3; 1216 upper = v_total - v_sync_strt - v_sync_wid; 1217 lower = v_sync_strt - v_disp; 1218 vslen = v_sync_wid; 1219 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1220 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1221 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1222 1223 aty128_pix_width_to_var(pix_width, var); 1224 1225 var->xres = xres; 1226 var->yres = yres; 1227 var->xres_virtual = crtc->vxres; 1228 var->yres_virtual = crtc->vyres; 1229 var->xoffset = crtc->xoffset; 1230 var->yoffset = crtc->yoffset; 1231 var->left_margin = left; 1232 var->right_margin = right; 1233 var->upper_margin = upper; 1234 var->lower_margin = lower; 1235 var->hsync_len = hslen; 1236 var->vsync_len = vslen; 1237 var->sync = sync; 1238 var->vmode = FB_VMODE_NONINTERLACED; 1239 1240 return 0; 1241} 1242 1243static void aty128_set_crt_enable(struct aty128fb_par *par, int on) 1244{ 1245 if (on) { 1246 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON); 1247 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN)); 1248 } else 1249 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON); 1250} 1251 1252static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) 1253{ 1254 u32 reg; 1255#ifdef CONFIG_FB_ATY128_BACKLIGHT 1256 struct fb_info *info = pci_get_drvdata(par->pdev); 1257#endif 1258 1259 if (on) { 1260 reg = aty_ld_le32(LVDS_GEN_CNTL); 1261 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1262 reg &= ~LVDS_DISPLAY_DIS; 1263 aty_st_le32(LVDS_GEN_CNTL, reg); 1264#ifdef CONFIG_FB_ATY128_BACKLIGHT 1265 aty128_bl_set_power(info, FB_BLANK_UNBLANK); 1266#endif 1267 } else { 1268#ifdef CONFIG_FB_ATY128_BACKLIGHT 1269 aty128_bl_set_power(info, FB_BLANK_POWERDOWN); 1270#endif 1271 reg = aty_ld_le32(LVDS_GEN_CNTL); 1272 reg |= LVDS_DISPLAY_DIS; 1273 aty_st_le32(LVDS_GEN_CNTL, reg); 1274 mdelay(100); 1275 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1276 aty_st_le32(LVDS_GEN_CNTL, reg); 1277 } 1278} 1279 1280static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par) 1281{ 1282 u32 div3; 1283 1284 unsigned char post_conv[] = /* register values for post dividers */ 1285 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; 1286 1287 /* select PPLL_DIV_3 */ 1288 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1289 1290 /* reset PLL */ 1291 aty_st_pll(PPLL_CNTL, 1292 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1293 1294 /* write the reference divider */ 1295 aty_pll_wait_readupdate(par); 1296 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); 1297 aty_pll_writeupdate(par); 1298 1299 div3 = aty_ld_pll(PPLL_DIV_3); 1300 div3 &= ~PPLL_FB3_DIV_MASK; 1301 div3 |= pll->feedback_divider; 1302 div3 &= ~PPLL_POST3_DIV_MASK; 1303 div3 |= post_conv[pll->post_divider] << 16; 1304 1305 /* write feedback and post dividers */ 1306 aty_pll_wait_readupdate(par); 1307 aty_st_pll(PPLL_DIV_3, div3); 1308 aty_pll_writeupdate(par); 1309 1310 aty_pll_wait_readupdate(par); 1311 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1312 aty_pll_writeupdate(par); 1313 1314 /* clear the reset, just in case */ 1315 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1316} 1317 1318 1319static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1320 const struct aty128fb_par *par) 1321{ 1322 const struct aty128_constants c = par->constants; 1323 unsigned char post_dividers[] = {1,2,4,8,3,6,12}; 1324 u32 output_freq; 1325 u32 vclk; /* in .01 MHz */ 1326 int i = 0; 1327 u32 n, d; 1328 1329 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1330 1331 /* adjust pixel clock if necessary */ 1332 if (vclk > c.ppll_max) 1333 vclk = c.ppll_max; 1334 if (vclk * 12 < c.ppll_min) 1335 vclk = c.ppll_min/12; 1336 1337 pll->post_divider = -1; 1338 1339 /* now, find an acceptable divider */ 1340 for (i = 0; i < sizeof(post_dividers); i++) { 1341 output_freq = post_dividers[i] * vclk; 1342 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { 1343 pll->post_divider = post_dividers[i]; 1344 break; 1345 } 1346 } 1347 1348 if (pll->post_divider < 0) 1349 return -EINVAL; 1350 1351 /* calculate feedback divider */ 1352 n = c.ref_divider * output_freq; 1353 d = c.ref_clk; 1354 1355 pll->feedback_divider = round_div(n, d); 1356 pll->vclk = vclk; 1357 1358 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1359 "vclk_per: %d\n", pll->post_divider, 1360 pll->feedback_divider, vclk, output_freq, 1361 c.ref_divider, period_in_ps); 1362 1363 return 0; 1364} 1365 1366 1367static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var) 1368{ 1369 var->pixclock = 100000000 / pll->vclk; 1370 1371 return 0; 1372} 1373 1374 1375static void aty128_set_fifo(const struct aty128_ddafifo *dsp, 1376 const struct aty128fb_par *par) 1377{ 1378 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1379 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1380} 1381 1382 1383static int aty128_ddafifo(struct aty128_ddafifo *dsp, 1384 const struct aty128_pll *pll, 1385 u32 depth, 1386 const struct aty128fb_par *par) 1387{ 1388 const struct aty128_meminfo *m = par->mem; 1389 u32 xclk = par->constants.xclk; 1390 u32 fifo_width = par->constants.fifo_width; 1391 u32 fifo_depth = par->constants.fifo_depth; 1392 s32 x, b, p, ron, roff; 1393 u32 n, d, bpp; 1394 1395 /* round up to multiple of 8 */ 1396 bpp = (depth+7) & ~7; 1397 1398 n = xclk * fifo_width; 1399 d = pll->vclk * bpp; 1400 x = round_div(n, d); 1401 1402 ron = 4 * m->MB + 1403 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1404 2 * m->Trp + 1405 m->Twr + 1406 m->CL + 1407 m->Tr2w + 1408 x; 1409 1410 DBG("x %x\n", x); 1411 1412 b = 0; 1413 while (x) { 1414 x >>= 1; 1415 b++; 1416 } 1417 p = b + 1; 1418 1419 ron <<= (11 - p); 1420 1421 n <<= (11 - p); 1422 x = round_div(n, d); 1423 roff = x * (fifo_depth - 4); 1424 1425 if ((ron + m->Rloop) >= roff) { 1426 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1427 return -EINVAL; 1428 } 1429 1430 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1431 p, m->Rloop, x, ron, roff); 1432 1433 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1434 dsp->dda_on_off = ron << 16 | roff; 1435 1436 return 0; 1437} 1438 1439 1440/* 1441 * This actually sets the video mode. 1442 */ 1443static int aty128fb_set_par(struct fb_info *info) 1444{ 1445 struct aty128fb_par *par = info->par; 1446 u32 config; 1447 int err; 1448 1449 if ((err = aty128_decode_var(&info->var, par)) != 0) 1450 return err; 1451 1452 if (par->blitter_may_be_busy) 1453 wait_for_idle(par); 1454 1455 /* clear all registers that may interfere with mode setting */ 1456 aty_st_le32(OVR_CLR, 0); 1457 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1458 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1459 aty_st_le32(OV0_SCALE_CNTL, 0); 1460 aty_st_le32(MPP_TB_CONFIG, 0); 1461 aty_st_le32(MPP_GP_CONFIG, 0); 1462 aty_st_le32(SUBPIC_CNTL, 0); 1463 aty_st_le32(VIPH_CONTROL, 0); 1464 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1465 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1466 aty_st_le32(CAP0_TRIG_CNTL, 0); 1467 aty_st_le32(CAP1_TRIG_CNTL, 0); 1468 1469 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1470 1471 aty128_set_crtc(&par->crtc, par); 1472 aty128_set_pll(&par->pll, par); 1473 aty128_set_fifo(&par->fifo_reg, par); 1474 1475 config = aty_ld_le32(CONFIG_CNTL) & ~3; 1476 1477#if defined(__BIG_ENDIAN) 1478 if (par->crtc.bpp == 32) 1479 config |= 2; /* make aperture do 32 bit swapping */ 1480 else if (par->crtc.bpp == 16) 1481 config |= 1; /* make aperture do 16 bit swapping */ 1482#endif 1483 1484 aty_st_le32(CONFIG_CNTL, config); 1485 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1486 1487 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1488 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1489 : FB_VISUAL_DIRECTCOLOR; 1490 1491 if (par->chip_gen == rage_M3) { 1492 aty128_set_crt_enable(par, par->crt_on); 1493 aty128_set_lcd_enable(par, par->lcd_on); 1494 } 1495 if (par->accel_flags & FB_ACCELF_TEXT) 1496 aty128_init_engine(par); 1497 1498#ifdef CONFIG_BOOTX_TEXT 1499 btext_update_display(info->fix.smem_start, 1500 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1501 ((par->crtc.v_total>>16) & 0x7ff)+1, 1502 par->crtc.bpp, 1503 par->crtc.vxres*par->crtc.bpp/8); 1504#endif /* CONFIG_BOOTX_TEXT */ 1505 1506 return 0; 1507} 1508 1509/* 1510 * encode/decode the User Defined Part of the Display 1511 */ 1512 1513static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par) 1514{ 1515 int err; 1516 struct aty128_crtc crtc; 1517 struct aty128_pll pll; 1518 struct aty128_ddafifo fifo_reg; 1519 1520 if ((err = aty128_var_to_crtc(var, &crtc, par))) 1521 return err; 1522 1523 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) 1524 return err; 1525 1526 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) 1527 return err; 1528 1529 par->crtc = crtc; 1530 par->pll = pll; 1531 par->fifo_reg = fifo_reg; 1532 par->accel_flags = var->accel_flags; 1533 1534 return 0; 1535} 1536 1537 1538static int aty128_encode_var(struct fb_var_screeninfo *var, 1539 const struct aty128fb_par *par) 1540{ 1541 int err; 1542 1543 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1544 return err; 1545 1546 if ((err = aty128_pll_to_var(&par->pll, var))) 1547 return err; 1548 1549 var->nonstd = 0; 1550 var->activate = 0; 1551 1552 var->height = -1; 1553 var->width = -1; 1554 var->accel_flags = par->accel_flags; 1555 1556 return 0; 1557} 1558 1559 1560static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1561{ 1562 struct aty128fb_par par; 1563 int err; 1564 1565 par = *(struct aty128fb_par *)info->par; 1566 if ((err = aty128_decode_var(var, &par)) != 0) 1567 return err; 1568 aty128_encode_var(var, &par); 1569 return 0; 1570} 1571 1572 1573/* 1574 * Pan or Wrap the Display 1575 */ 1576static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb) 1577{ 1578 struct aty128fb_par *par = fb->par; 1579 u32 xoffset, yoffset; 1580 u32 offset; 1581 u32 xres, yres; 1582 1583 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1584 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1585 1586 xoffset = (var->xoffset +7) & ~7; 1587 yoffset = var->yoffset; 1588 1589 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1590 return -EINVAL; 1591 1592 par->crtc.xoffset = xoffset; 1593 par->crtc.yoffset = yoffset; 1594 1595 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7; 1596 1597 if (par->crtc.bpp == 24) 1598 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1599 1600 aty_st_le32(CRTC_OFFSET, offset); 1601 1602 return 0; 1603} 1604 1605 1606/* 1607 * Helper function to store a single palette register 1608 */ 1609static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1610 struct aty128fb_par *par) 1611{ 1612 if (par->chip_gen == rage_M3) { 1613 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL); 1614 } 1615 1616 aty_st_8(PALETTE_INDEX, regno); 1617 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1618} 1619 1620static int aty128fb_sync(struct fb_info *info) 1621{ 1622 struct aty128fb_par *par = info->par; 1623 1624 if (par->blitter_may_be_busy) 1625 wait_for_idle(par); 1626 return 0; 1627} 1628 1629#ifndef MODULE 1630static int __devinit aty128fb_setup(char *options) 1631{ 1632 char *this_opt; 1633 1634 if (!options || !*options) 1635 return 0; 1636 1637 while ((this_opt = strsep(&options, ",")) != NULL) { 1638 if (!strncmp(this_opt, "lcd:", 4)) { 1639 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1640 continue; 1641 } else if (!strncmp(this_opt, "crt:", 4)) { 1642 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1643 continue; 1644 } else if (!strncmp(this_opt, "backlight:", 10)) { 1645 backlight = simple_strtoul(this_opt+10, NULL, 0); 1646 continue; 1647 } 1648#ifdef CONFIG_MTRR 1649 if(!strncmp(this_opt, "nomtrr", 6)) { 1650 mtrr = 0; 1651 continue; 1652 } 1653#endif 1654#ifdef CONFIG_PPC_PMAC 1655 /* vmode and cmode deprecated */ 1656 if (!strncmp(this_opt, "vmode:", 6)) { 1657 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1658 if (vmode > 0 && vmode <= VMODE_MAX) 1659 default_vmode = vmode; 1660 continue; 1661 } else if (!strncmp(this_opt, "cmode:", 6)) { 1662 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1663 switch (cmode) { 1664 case 0: 1665 case 8: 1666 default_cmode = CMODE_8; 1667 break; 1668 case 15: 1669 case 16: 1670 default_cmode = CMODE_16; 1671 break; 1672 case 24: 1673 case 32: 1674 default_cmode = CMODE_32; 1675 break; 1676 } 1677 continue; 1678 } 1679#endif /* CONFIG_PPC_PMAC */ 1680 mode_option = this_opt; 1681 } 1682 return 0; 1683} 1684#endif /* MODULE */ 1685 1686/* Backlight */ 1687#ifdef CONFIG_FB_ATY128_BACKLIGHT 1688#define MAX_LEVEL 0xFF 1689 1690static int aty128_bl_get_level_brightness(struct aty128fb_par *par, 1691 int level) 1692{ 1693 struct fb_info *info = pci_get_drvdata(par->pdev); 1694 int atylevel; 1695 1696 /* Get and convert the value */ 1697 /* No locking of bl_curve since we read a single value */ 1698 atylevel = MAX_LEVEL - 1699 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); 1700 1701 if (atylevel < 0) 1702 atylevel = 0; 1703 else if (atylevel > MAX_LEVEL) 1704 atylevel = MAX_LEVEL; 1705 1706 return atylevel; 1707} 1708 1709/* We turn off the LCD completely instead of just dimming the backlight. 1710 * This provides greater power saving and the display is useless without 1711 * backlight anyway 1712 */ 1713#define BACKLIGHT_LVDS_OFF 1714/* That one prevents proper CRT output with LCD off */ 1715#undef BACKLIGHT_DAC_OFF 1716 1717static int aty128_bl_update_status(struct backlight_device *bd) 1718{ 1719 struct aty128fb_par *par = class_get_devdata(&bd->class_dev); 1720 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 1721 int level; 1722 1723 if (bd->props.power != FB_BLANK_UNBLANK || 1724 bd->props.fb_blank != FB_BLANK_UNBLANK || 1725 !par->lcd_on) 1726 level = 0; 1727 else 1728 level = bd->props.brightness; 1729 1730 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 1731 if (level > 0) { 1732 reg |= LVDS_DIGION; 1733 if (!(reg & LVDS_ON)) { 1734 reg &= ~LVDS_BLON; 1735 aty_st_le32(LVDS_GEN_CNTL, reg); 1736 aty_ld_le32(LVDS_GEN_CNTL); 1737 mdelay(10); 1738 reg |= LVDS_BLON; 1739 aty_st_le32(LVDS_GEN_CNTL, reg); 1740 } 1741 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1742 reg |= (aty128_bl_get_level_brightness(par, level) << LVDS_BL_MOD_LEVEL_SHIFT); 1743#ifdef BACKLIGHT_LVDS_OFF 1744 reg |= LVDS_ON | LVDS_EN; 1745 reg &= ~LVDS_DISPLAY_DIS; 1746#endif 1747 aty_st_le32(LVDS_GEN_CNTL, reg); 1748#ifdef BACKLIGHT_DAC_OFF 1749 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 1750#endif 1751 } else { 1752 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1753 reg |= (aty128_bl_get_level_brightness(par, 0) << LVDS_BL_MOD_LEVEL_SHIFT); 1754#ifdef BACKLIGHT_LVDS_OFF 1755 reg |= LVDS_DISPLAY_DIS; 1756 aty_st_le32(LVDS_GEN_CNTL, reg); 1757 aty_ld_le32(LVDS_GEN_CNTL); 1758 udelay(10); 1759 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 1760#endif 1761 aty_st_le32(LVDS_GEN_CNTL, reg); 1762#ifdef BACKLIGHT_DAC_OFF 1763 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 1764#endif 1765 } 1766 1767 return 0; 1768} 1769 1770static int aty128_bl_get_brightness(struct backlight_device *bd) 1771{ 1772 return bd->props.brightness; 1773} 1774 1775static struct backlight_ops aty128_bl_data = { 1776 .get_brightness = aty128_bl_get_brightness, 1777 .update_status = aty128_bl_update_status, 1778}; 1779 1780static void aty128_bl_set_power(struct fb_info *info, int power) 1781{ 1782 if (info->bl_dev) { 1783 info->bl_dev->props.power = power; 1784 backlight_update_status(info->bl_dev); 1785 } 1786} 1787 1788static void aty128_bl_init(struct aty128fb_par *par) 1789{ 1790 struct fb_info *info = pci_get_drvdata(par->pdev); 1791 struct backlight_device *bd; 1792 char name[12]; 1793 1794 /* Could be extended to Rage128Pro LVDS output too */ 1795 if (par->chip_gen != rage_M3) 1796 return; 1797 1798#ifdef CONFIG_PMAC_BACKLIGHT 1799 if (!pmac_has_backlight_type("ati")) 1800 return; 1801#endif 1802 1803 snprintf(name, sizeof(name), "aty128bl%d", info->node); 1804 1805 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data); 1806 if (IS_ERR(bd)) { 1807 info->bl_dev = NULL; 1808 printk(KERN_WARNING "aty128: Backlight registration failed\n"); 1809 goto error; 1810 } 1811 1812 info->bl_dev = bd; 1813 fb_bl_default_curve(info, 0, 1814 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, 1815 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); 1816 1817 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 1818 bd->props.brightness = bd->props.max_brightness; 1819 bd->props.power = FB_BLANK_UNBLANK; 1820 backlight_update_status(bd); 1821 1822 printk("aty128: Backlight initialized (%s)\n", name); 1823 1824 return; 1825 1826error: 1827 return; 1828} 1829 1830static void aty128_bl_exit(struct backlight_device *bd) 1831{ 1832 backlight_device_unregister(bd); 1833 printk("aty128: Backlight unloaded\n"); 1834} 1835#endif /* CONFIG_FB_ATY128_BACKLIGHT */ 1836 1837/* 1838 * Initialisation 1839 */ 1840 1841#ifdef CONFIG_PPC_PMAC 1842static void aty128_early_resume(void *data) 1843{ 1844 struct aty128fb_par *par = data; 1845 1846 if (try_acquire_console_sem()) 1847 return; 1848 aty128_do_resume(par->pdev); 1849 release_console_sem(); 1850} 1851#endif /* CONFIG_PPC_PMAC */ 1852 1853static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) 1854{ 1855 struct fb_info *info = pci_get_drvdata(pdev); 1856 struct aty128fb_par *par = info->par; 1857 struct fb_var_screeninfo var; 1858 char video_card[DEVICE_NAME_SIZE]; 1859 u8 chip_rev; 1860 u32 dac; 1861 1862 /* Get the chip revision */ 1863 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F; 1864 1865 strcpy(video_card, "Rage128 XX "); 1866 video_card[8] = ent->device >> 8; 1867 video_card[9] = ent->device & 0xFF; 1868 1869 /* range check to make sure */ 1870 if (ent->driver_data < ARRAY_SIZE(r128_family)) 1871 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card)); 1872 1873 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1874 1875 if (par->vram_size % (1024 * 1024) == 0) 1876 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); 1877 else 1878 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); 1879 1880 par->chip_gen = ent->driver_data; 1881 1882 /* fill in info */ 1883 info->fbops = &aty128fb_ops; 1884 info->flags = FBINFO_FLAG_DEFAULT; 1885 1886 par->lcd_on = default_lcd_on; 1887 par->crt_on = default_crt_on; 1888 1889 var = default_var; 1890#ifdef CONFIG_PPC_PMAC 1891 if (machine_is(powermac)) { 1892 /* Indicate sleep capability */ 1893 if (par->chip_gen == rage_M3) { 1894 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1895 pmac_set_early_video_resume(aty128_early_resume, par); 1896 } 1897 1898 /* Find default mode */ 1899 if (mode_option) { 1900 if (!mac_find_mode(&var, info, mode_option, 8)) 1901 var = default_var; 1902 } else { 1903 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1904 default_vmode = VMODE_1024_768_60; 1905 1906 /* iMacs need that resolution 1907 * PowerMac2,1 first r128 iMacs 1908 * PowerMac2,2 summer 2000 iMacs 1909 * PowerMac4,1 january 2001 iMacs "flower power" 1910 */ 1911 if (machine_is_compatible("PowerMac2,1") || 1912 machine_is_compatible("PowerMac2,2") || 1913 machine_is_compatible("PowerMac4,1")) 1914 default_vmode = VMODE_1024_768_75; 1915 1916 /* iBook SE */ 1917 if (machine_is_compatible("PowerBook2,2")) 1918 default_vmode = VMODE_800_600_60; 1919 1920 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1921 if (machine_is_compatible("PowerBook3,1") || 1922 machine_is_compatible("PowerBook4,1")) 1923 default_vmode = VMODE_1024_768_60; 1924 1925 /* PowerBook Titanium */ 1926 if (machine_is_compatible("PowerBook3,2")) 1927 default_vmode = VMODE_1152_768_60; 1928 1929 if (default_cmode > 16) 1930 default_cmode = CMODE_32; 1931 else if (default_cmode > 8) 1932 default_cmode = CMODE_16; 1933 else 1934 default_cmode = CMODE_8; 1935 1936 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 1937 var = default_var; 1938 } 1939 } else 1940#endif /* CONFIG_PPC_PMAC */ 1941 { 1942 if (mode_option) 1943 if (fb_find_mode(&var, info, mode_option, NULL, 1944 0, &defaultmode, 8) == 0) 1945 var = default_var; 1946 } 1947 1948 var.accel_flags &= ~FB_ACCELF_TEXT; 1949// var.accel_flags |= FB_ACCELF_TEXT; 1950 1951 if (aty128fb_check_var(&var, info)) { 1952 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 1953 return 0; 1954 } 1955 1956 /* setup the DAC the way we like it */ 1957 dac = aty_ld_le32(DAC_CNTL); 1958 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 1959 dac |= DAC_MASK; 1960 if (par->chip_gen == rage_M3) 1961 dac |= DAC_PALETTE2_SNOOP_EN; 1962 aty_st_le32(DAC_CNTL, dac); 1963 1964 /* turn off bus mastering, just in case */ 1965 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 1966 1967 info->var = var; 1968 fb_alloc_cmap(&info->cmap, 256, 0); 1969 1970 var.activate = FB_ACTIVATE_NOW; 1971 1972 aty128_init_engine(par); 1973 1974 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM); 1975 par->pdev = pdev; 1976 par->asleep = 0; 1977 par->lock_blank = 0; 1978 1979#ifdef CONFIG_FB_ATY128_BACKLIGHT 1980 if (backlight) 1981 aty128_bl_init(par); 1982#endif 1983 1984 if (register_framebuffer(info) < 0) 1985 return 0; 1986 1987 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n", 1988 info->node, info->fix.id, video_card); 1989 1990 return 1; /* success! */ 1991} 1992 1993#ifdef CONFIG_PCI 1994/* register a card ++ajoshi */ 1995static int __devinit aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1996{ 1997 unsigned long fb_addr, reg_addr; 1998 struct aty128fb_par *par; 1999 struct fb_info *info; 2000 int err; 2001#ifndef __sparc__ 2002 void __iomem *bios = NULL; 2003#endif 2004 2005 /* Enable device in PCI config */ 2006 if ((err = pci_enable_device(pdev))) { 2007 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2008 err); 2009 return -ENODEV; 2010 } 2011 2012 fb_addr = pci_resource_start(pdev, 0); 2013 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2014 "aty128fb FB")) { 2015 printk(KERN_ERR "aty128fb: cannot reserve frame " 2016 "buffer memory\n"); 2017 return -ENODEV; 2018 } 2019 2020 reg_addr = pci_resource_start(pdev, 2); 2021 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2022 "aty128fb MMIO")) { 2023 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2024 goto err_free_fb; 2025 } 2026 2027 /* We have the resources. Now virtualize them */ 2028 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); 2029 if (info == NULL) { 2030 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n"); 2031 goto err_free_mmio; 2032 } 2033 par = info->par; 2034 2035 info->pseudo_palette = par->pseudo_palette; 2036 2037 /* Virtualize mmio region */ 2038 info->fix.mmio_start = reg_addr; 2039 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2)); 2040 if (!par->regbase) 2041 goto err_free_info; 2042 2043 /* Grab memory size from the card */ 2044 // How does this relate to the resource length from the PCI hardware? 2045 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF; 2046 2047 /* Virtualize the framebuffer */ 2048 info->screen_base = ioremap(fb_addr, par->vram_size); 2049 if (!info->screen_base) 2050 goto err_unmap_out; 2051 2052 /* Set up info->fix */ 2053 info->fix = aty128fb_fix; 2054 info->fix.smem_start = fb_addr; 2055 info->fix.smem_len = par->vram_size; 2056 info->fix.mmio_start = reg_addr; 2057 2058 /* If we can't test scratch registers, something is seriously wrong */ 2059 if (!register_test(par)) { 2060 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2061 goto err_out; 2062 } 2063 2064#ifndef __sparc__ 2065 bios = aty128_map_ROM(par, pdev); 2066#ifdef CONFIG_X86 2067 if (bios == NULL) 2068 bios = aty128_find_mem_vbios(par); 2069#endif 2070 if (bios == NULL) 2071 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); 2072 else { 2073 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); 2074 aty128_get_pllinfo(par, bios); 2075 pci_unmap_rom(pdev, bios); 2076 } 2077#endif /* __sparc__ */ 2078 2079 aty128_timings(par); 2080 pci_set_drvdata(pdev, info); 2081 2082 if (!aty128_init(pdev, ent)) 2083 goto err_out; 2084 2085#ifdef CONFIG_MTRR 2086 if (mtrr) { 2087 par->mtrr.vram = mtrr_add(info->fix.smem_start, 2088 par->vram_size, MTRR_TYPE_WRCOMB, 1); 2089 par->mtrr.vram_valid = 1; 2090 /* let there be speed */ 2091 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n"); 2092 } 2093#endif /* CONFIG_MTRR */ 2094 return 0; 2095 2096err_out: 2097 iounmap(info->screen_base); 2098err_unmap_out: 2099 iounmap(par->regbase); 2100err_free_info: 2101 framebuffer_release(info); 2102err_free_mmio: 2103 release_mem_region(pci_resource_start(pdev, 2), 2104 pci_resource_len(pdev, 2)); 2105err_free_fb: 2106 release_mem_region(pci_resource_start(pdev, 0), 2107 pci_resource_len(pdev, 0)); 2108 return -ENODEV; 2109} 2110 2111static void __devexit aty128_remove(struct pci_dev *pdev) 2112{ 2113 struct fb_info *info = pci_get_drvdata(pdev); 2114 struct aty128fb_par *par; 2115 2116 if (!info) 2117 return; 2118 2119 par = info->par; 2120 2121 unregister_framebuffer(info); 2122 2123#ifdef CONFIG_FB_ATY128_BACKLIGHT 2124 aty128_bl_exit(info->bl_dev); 2125#endif 2126 2127#ifdef CONFIG_MTRR 2128 if (par->mtrr.vram_valid) 2129 mtrr_del(par->mtrr.vram, info->fix.smem_start, 2130 par->vram_size); 2131#endif /* CONFIG_MTRR */ 2132 iounmap(par->regbase); 2133 iounmap(info->screen_base); 2134 2135 release_mem_region(pci_resource_start(pdev, 0), 2136 pci_resource_len(pdev, 0)); 2137 release_mem_region(pci_resource_start(pdev, 2), 2138 pci_resource_len(pdev, 2)); 2139 framebuffer_release(info); 2140} 2141#endif /* CONFIG_PCI */ 2142 2143 2144 2145 /* 2146 * Blank the display. 2147 */ 2148static int aty128fb_blank(int blank, struct fb_info *fb) 2149{ 2150 struct aty128fb_par *par = fb->par; 2151 u8 state; 2152 2153 if (par->lock_blank || par->asleep) 2154 return 0; 2155 2156 switch (blank) { 2157 case FB_BLANK_NORMAL: 2158 state = 4; 2159 break; 2160 case FB_BLANK_VSYNC_SUSPEND: 2161 state = 6; 2162 break; 2163 case FB_BLANK_HSYNC_SUSPEND: 2164 state = 5; 2165 break; 2166 case FB_BLANK_POWERDOWN: 2167 state = 7; 2168 break; 2169 case FB_BLANK_UNBLANK: 2170 default: 2171 state = 0; 2172 break; 2173 } 2174 aty_st_8(CRTC_EXT_CNTL+1, state); 2175 2176 if (par->chip_gen == rage_M3) { 2177 aty128_set_crt_enable(par, par->crt_on && !blank); 2178 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2179 } 2180 2181 return 0; 2182} 2183 2184/* 2185 * Set a single color register. The values supplied are already 2186 * rounded down to the hardware's capabilities (according to the 2187 * entries in the var structure). Return != 0 for invalid regno. 2188 */ 2189static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2190 u_int transp, struct fb_info *info) 2191{ 2192 struct aty128fb_par *par = info->par; 2193 2194 if (regno > 255 2195 || (par->crtc.depth == 16 && regno > 63) 2196 || (par->crtc.depth == 15 && regno > 31)) 2197 return 1; 2198 2199 red >>= 8; 2200 green >>= 8; 2201 blue >>= 8; 2202 2203 if (regno < 16) { 2204 int i; 2205 u32 *pal = info->pseudo_palette; 2206 2207 switch (par->crtc.depth) { 2208 case 15: 2209 pal[regno] = (regno << 10) | (regno << 5) | regno; 2210 break; 2211 case 16: 2212 pal[regno] = (regno << 11) | (regno << 6) | regno; 2213 break; 2214 case 24: 2215 pal[regno] = (regno << 16) | (regno << 8) | regno; 2216 break; 2217 case 32: 2218 i = (regno << 8) | regno; 2219 pal[regno] = (i << 16) | i; 2220 break; 2221 } 2222 } 2223 2224 if (par->crtc.depth == 16 && regno > 0) { 2225 /* 2226 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we 2227 * have 32 slots for R and B values but 64 slots for G values. 2228 * Thus the R and B values go in one slot but the G value 2229 * goes in a different slot, and we have to avoid disturbing 2230 * the other fields in the slots we touch. 2231 */ 2232 par->green[regno] = green; 2233 if (regno < 32) { 2234 par->red[regno] = red; 2235 par->blue[regno] = blue; 2236 aty128_st_pal(regno * 8, red, par->green[regno*2], 2237 blue, par); 2238 } 2239 red = par->red[regno/2]; 2240 blue = par->blue[regno/2]; 2241 regno <<= 2; 2242 } else if (par->crtc.bpp == 16) 2243 regno <<= 3; 2244 aty128_st_pal(regno, red, green, blue, par); 2245 2246 return 0; 2247} 2248 2249#define ATY_MIRROR_LCD_ON 0x00000001 2250#define ATY_MIRROR_CRT_ON 0x00000002 2251 2252/* out param: u32* backlight value: 0 to 15 */ 2253#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) 2254/* in param: u32* backlight value: 0 to 15 */ 2255#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) 2256 2257static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 2258{ 2259 struct aty128fb_par *par = info->par; 2260 u32 value; 2261 int rc; 2262 2263 switch (cmd) { 2264 case FBIO_ATY128_SET_MIRROR: 2265 if (par->chip_gen != rage_M3) 2266 return -EINVAL; 2267 rc = get_user(value, (__u32 __user *)arg); 2268 if (rc) 2269 return rc; 2270 par->lcd_on = (value & 0x01) != 0; 2271 par->crt_on = (value & 0x02) != 0; 2272 if (!par->crt_on && !par->lcd_on) 2273 par->lcd_on = 1; 2274 aty128_set_crt_enable(par, par->crt_on); 2275 aty128_set_lcd_enable(par, par->lcd_on); 2276 return 0; 2277 case FBIO_ATY128_GET_MIRROR: 2278 if (par->chip_gen != rage_M3) 2279 return -EINVAL; 2280 value = (par->crt_on << 1) | par->lcd_on; 2281 return put_user(value, (__u32 __user *)arg); 2282 } 2283 return -EINVAL; 2284} 2285 2286 2287static void aty128_set_suspend(struct aty128fb_par *par, int suspend) 2288{ 2289 u32 pmgt; 2290 u16 pwr_command; 2291 struct pci_dev *pdev = par->pdev; 2292 2293 if (!par->pm_reg) 2294 return; 2295 2296 /* Set the chip into the appropriate suspend mode (we use D2, 2297 * D3 would require a complete re-initialisation of the chip, 2298 * including PCI config registers, clocks, AGP configuration, ...) 2299 */ 2300 if (suspend) { 2301 /* Make sure CRTC2 is reset. Remove that the day we decide to 2302 * actually use CRTC2 and replace it with real code for disabling 2303 * the CRTC2 output during sleep 2304 */ 2305 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2306 ~(CRTC2_EN)); 2307 2308 /* Set the power management mode to be PCI based */ 2309 /* Use this magic value for now */ 2310 pmgt = 0x0c005407; 2311 aty_st_pll(POWER_MANAGEMENT, pmgt); 2312 (void)aty_ld_pll(POWER_MANAGEMENT); 2313 aty_st_le32(BUS_CNTL1, 0x00000010); 2314 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2315 mdelay(100); 2316 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); 2317 /* Switch PCI power management to D2 */ 2318 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 2319 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2); 2320 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); 2321 } else { 2322 /* Switch back PCI power management to D0 */ 2323 mdelay(100); 2324 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0); 2325 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); 2326 mdelay(100); 2327 } 2328} 2329 2330static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) 2331{ 2332 struct fb_info *info = pci_get_drvdata(pdev); 2333 struct aty128fb_par *par = info->par; 2334 2335 /* We don't do anything but D2, for now we return 0, but 2336 * we may want to change that. How do we know if the BIOS 2337 * can properly take care of D3 ? Also, with swsusp, we 2338 * know we'll be rebooted, ... 2339 */ 2340#ifndef CONFIG_PPC_PMAC 2341 /* HACK ALERT ! Once I find a proper way to say to each driver 2342 * individually what will happen with it's PCI slot, I'll change 2343 * that. On laptops, the AGP slot is just unclocked, so D2 is 2344 * expected, while on desktops, the card is powered off 2345 */ 2346 return 0; 2347#endif /* CONFIG_PPC_PMAC */ 2348 2349 if (state.event == pdev->dev.power.power_state.event) 2350 return 0; 2351 2352 printk(KERN_DEBUG "aty128fb: suspending...\n"); 2353 2354 acquire_console_sem(); 2355 2356 fb_set_suspend(info, 1); 2357 2358 /* Make sure engine is reset */ 2359 wait_for_idle(par); 2360 aty128_reset_engine(par); 2361 wait_for_idle(par); 2362 2363 /* Blank display and LCD */ 2364 aty128fb_blank(FB_BLANK_POWERDOWN, info); 2365 2366 /* Sleep */ 2367 par->asleep = 1; 2368 par->lock_blank = 1; 2369 2370#ifdef CONFIG_PPC_PMAC 2371 /* On powermac, we have hooks to properly suspend/resume AGP now, 2372 * use them here. We'll ultimately need some generic support here, 2373 * but the generic code isn't quite ready for that yet 2374 */ 2375 pmac_suspend_agp_for_card(pdev); 2376#endif /* CONFIG_PPC_PMAC */ 2377 2378 /* We need a way to make sure the fbdev layer will _not_ touch the 2379 * framebuffer before we put the chip to suspend state. On 2.4, I 2380 * used dummy fb ops, 2.5 need proper support for this at the 2381 * fbdev level 2382 */ 2383 if (state.event != PM_EVENT_ON) 2384 aty128_set_suspend(par, 1); 2385 2386 release_console_sem(); 2387 2388 pdev->dev.power.power_state = state; 2389 2390 return 0; 2391} 2392 2393static int aty128_do_resume(struct pci_dev *pdev) 2394{ 2395 struct fb_info *info = pci_get_drvdata(pdev); 2396 struct aty128fb_par *par = info->par; 2397 2398 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2399 return 0; 2400 2401 /* Wakeup chip */ 2402 aty128_set_suspend(par, 0); 2403 par->asleep = 0; 2404 2405 /* Restore display & engine */ 2406 aty128_reset_engine(par); 2407 wait_for_idle(par); 2408 aty128fb_set_par(info); 2409 fb_pan_display(info, &info->var); 2410 fb_set_cmap(&info->cmap, info); 2411 2412 /* Refresh */ 2413 fb_set_suspend(info, 0); 2414 2415 /* Unblank */ 2416 par->lock_blank = 0; 2417 aty128fb_blank(0, info); 2418 2419#ifdef CONFIG_PPC_PMAC 2420 /* On powermac, we have hooks to properly suspend/resume AGP now, 2421 * use them here. We'll ultimately need some generic support here, 2422 * but the generic code isn't quite ready for that yet 2423 */ 2424 pmac_resume_agp_for_card(pdev); 2425#endif /* CONFIG_PPC_PMAC */ 2426 2427 pdev->dev.power.power_state = PMSG_ON; 2428 2429 printk(KERN_DEBUG "aty128fb: resumed !\n"); 2430 2431 return 0; 2432} 2433 2434static int aty128_pci_resume(struct pci_dev *pdev) 2435{ 2436 int rc; 2437 2438 acquire_console_sem(); 2439 rc = aty128_do_resume(pdev); 2440 release_console_sem(); 2441 2442 return rc; 2443} 2444 2445 2446static int __devinit aty128fb_init(void) 2447{ 2448#ifndef MODULE 2449 char *option = NULL; 2450 2451 if (fb_get_options("aty128fb", &option)) 2452 return -ENODEV; 2453 aty128fb_setup(option); 2454#endif 2455 2456 return pci_register_driver(&aty128fb_driver); 2457} 2458 2459static void __exit aty128fb_exit(void) 2460{ 2461 pci_unregister_driver(&aty128fb_driver); 2462} 2463 2464module_init(aty128fb_init); 2465 2466module_exit(aty128fb_exit); 2467 2468MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); 2469MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2470MODULE_LICENSE("GPL"); 2471module_param(mode_option, charp, 0); 2472MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2473#ifdef CONFIG_MTRR 2474module_param_named(nomtrr, mtrr, invbool, 0); 2475MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); 2476#endif 2477